CN105703894B - Frequency domain time synchronization method and device - Google Patents
Frequency domain time synchronization method and device Download PDFInfo
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Abstract
The present invention relates to a kind of frequency domain time synchronization method and devices, method includes the following steps: being timed amendment to time-domain sample point signal in timing offset corrector, obtain revised output time-domain sample point signal；The time-domain sample point signal of the timing offset corrector input terminal or output end is transformed into frequency domain；It is timed synchronization in frequency domain, obtains timing phase estimated value, and the timing phase estimated value is supplied to the timing offset corrector.
Description
Technical field
The present invention relates to the simultaneous techniques field in the physical layer receiver of communication system, especially a kind of frequency domain timing is same
One step process and device.
Background technique
In the receiver of communication system, especially in the receiver of the communication system based on burst packet technology, periodically together
Step technology plays vital role.The technical difficulty that Timing Synchronization technology solves includes two o'clock, is a little thick synchronous skill
The sample point deviation generated in art acquisition procedure, on the other hand due to sample frequency and/or the error or drift of initial samples phase
Shifting cause as analog-digital converter (ADC) one kind device occur off-target sampled point and bring sampling deviation.It is thick synchronous
Technology (or be capture technique), which not can guarantee, can obtain original samples point position with high accuracy, and sampling frequency offset or
Drift and initial samples phase error are that communication system is inherent again, and all these timing error/sampling errors can only be according to
It is solved by Timing Synchronization technology.Some communication systems, especially coherent demodulation system, it is very sensitive to timing error, or even arrive
It can not allow to occur the stage of half sample point deviation.
Fig. 1 shows the timing synchronization device based on feedback method known to one kind.Refering to what is shown in Fig. 1, timing synchronization device
10 include matched filter 12, interpolation filter 14 and SNR detection module 16.The time-domain sample point signal of input is introduced into
Matched filter 12 carries out matched filtering, enters back into interpolation filter 14 and is timed amendment, obtains the revised output time
Domain sample point signal.In addition, timing phase estimated value needed for interpolation filter 14 is then from SNR detection module 16.
Fig. 2 shows known to one kind based on the timing synchronization device of feed forward method.Refering to what is shown in Fig. 2, timing synchronization device
20 include matched filter 22, interpolation filter 24 and SNR detection module 26.Fig. 2 and Fig. 1 is the difference is that timing in Fig. 1
The input of synchronization module 16 is the output from interpolation filter 14, and in Fig. 2 the input of SNR detection module 26 be from
Output with filter 22.
In general, the performance of above-mentioned known Timing Synchronization technology is satisfactory.It has however been found that this side
There are a disadvantages for case, i.e., vulnerable to the influence of matched filter, and vulnerable to some other module such as AGC of receiver system
The influence of (automatic growth control) module.Through analyzing, this scheme is based on time-domain signal, and the amplitude of time-domain signal or phase
Position vulnerable to above-mentioned module influence and change.It, can be in design matched filter and receiver when using integrated design
Timing Synchronization performance is taken into account when other modules of system；However when other modules of matched filter and receiver system are independent
When design, the shortcomings that aforementioned schemes, becomes not receiving, and under serious situation, SNR detection module 16,26 can hardly restrain,
Even converge to the direction of mistake.
For example, Fig. 3 gives the width under bluetooth (Bluetooth) system BDR (Basic Data Rate) mode
The timing phase estimated value convergence graph of time-domain SNR detection module, channel is awgn channel, but noiseless at this time.At this time
It is not most suitable matched filter with filter.In systems in practice, it also tends to be difficult to find most suitable matched filter.
From figure 3, it can be seen that the timing phase estimated has finally converged to -1 sample point, and the timing phase deviation of systemic presupposition
Value is but -0.5 sample point, it is known that above-mentioned Timing Synchronization technical solution faulty convergence.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of frequency domain time synchronization method and devices, to matched filtering
The performance of the modules such as device is less sensitive, to have more stable performance.
The present invention wraps to solve above-mentioned technical problem and the technical solution adopted is that propose a kind of frequency domain time synchronization method
It includes following steps: amendment being timed to time-domain sample point signal in timing offset corrector, when obtaining revised output
Between domain sample point signal；The time-domain sample point signal of the timing offset corrector input terminal or output end is transformed into frequency
Domain；Synchronization is timed in frequency domain, obtains timing phase estimated value, and it is inclined that the timing phase estimated value is supplied to the timing
Poor corrector.
In one embodiment of this invention, the above method further include: by time-domain sample point signal incoming timing deviation
Before corrector, so that input time domain sample point signal is entered matched filter and carry out matched filtering.
In one embodiment of this invention, which is differential filtering device.
In one embodiment of this invention, the step of time-domain sample point signal being transformed into frequency domain includes: to input
Time-domain signal successively carry out asking phase operation and operation of differentiating, output signal is frequency domain signal.
In one embodiment of this invention, being timed synchronous step in frequency domain includes: by the frequency domain sample of input
This signal carries out instantaneous Timing Error Detection；Loop filtering is carried out to the instantaneous timing error value of acquisition, obtains timing phase
Value；And be suitable for the deformation that interpolation filter uses to the timing phase value of acquisition, obtain timing phase estimated value.
In one embodiment of this invention, which is first-order linear filter.
In one embodiment of this invention, the filtering operation of the interpolation filter are as follows: y_out=y (m)+p_f* (y (m+
1)-y(m))；Wherein p is the timing phase estimated, and p_i is the integer part of p, and p_f is the fractional part of p；Y (k), k=0,
1,2 ... is the time-domain sample point signal sequence of interpolation filter input, and y (m) and y (m+1) are to select suitable y using p_i
(k) the two adjacent signaling points for the carry out interpolation that signal is used as interpolation filter, y_out are the output of interpolation filter
Sample point signal value.
In one embodiment of this invention, it is assumed that the input signal sequence of frequency domain Timing Error Detection is y_f (k), k=
0,1,2 ..., then the instantaneous timing error value estimated are as follows: E (k)={ y_f (kT+T/2)-y_f ((k-1) T+T/2) } * y_f
(kT)；Wherein, T is symbol period, at least 2 times of signal up-samplings.
In one embodiment of this invention, the function of the loop filter are as follows: E_loop (k)=E_loop (k-1)+G*E
(k)；Wherein, E_loop, which is represented, passes through the filtered timing error value of loop filter；G represents gain coefficient, determines loop
The loop bandwidth and convergence rate of filter.
In one embodiment of this invention, be suitable for the deformation that interpolation filter uses to the timing phase value of acquisition
The step of include: E_out=C-E_loop；Wherein, E_out exports timing error value for treated, and C is a constant value.
The present invention also proposes that a kind of frequency domain timing synchronization device, including timing offset corrector, time-domain turn to frequency domain
Change the mold block and SNR detection module.Timing offset corrector input time domain sample point signal and with reference to timing phase estimated value into
Row timing is corrected, and revised output time-domain sample point signal is obtained；Time-domain is inclined by the timing to frequency domain conversion module
The time-domain sample point signal of poor corrector input terminal or output end is transformed into frequency domain；SNR detection module is carried out in frequency domain
Timing Synchronization obtains timing phase estimated value, and the timing phase estimated value is supplied to the timing offset corrector.
The present invention due to using the technology described above, compared with being allowed to existing in the scheme of time-domain Timing Synchronization,
Frequency domain Timing Synchronization is insensitive to the performance of matched filter and automatic growth control module.Therefore, timing of the invention is same
Step scheme is suitable for the receiver processing module of different performance, improves the robustness of system.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1 shows the timing synchronization device based on feedback method known to one kind.
Fig. 2 shows known to one kind based on the timing synchronization device of feed forward method.
Fig. 3 shows the timing phase estimated value convergence graph of the time-domain SNR detection module under Bluetooth system BDR mode.
Fig. 4 shows the timing synchronization device based on feedback method of one embodiment of the invention.
Fig. 5 shows the timing synchronization device based on feed forward method of one embodiment of the invention.
Fig. 6 shows the time-domain of one embodiment of the invention to frequency domain conversion module structure.
Fig. 7 shows the frequency domain timing module structure of one embodiment of the invention.
Fig. 8 shows the packet format of an example according to the present invention.
Fig. 9 shows the packet format of another example according to the present invention.
Figure 10 shows the transmitter processes process of an example according to the present invention.
Figure 11 shows the receiver process flow of an example according to the present invention.
Figure 12 shows the timing phase estimated value convergence graph of one embodiment of the invention frequency domain regular synchronization scheme.
Specific embodiment
The embodiment of the present invention describes timing synchronization device, it is to modules such as matched filter, automatic growth control modules
Performance it is less sensitive, thus have more stable performance.
Fig. 4 shows the timing synchronization device based on feedback method of one embodiment of the invention.Refering to what is shown in Fig. 4, this implementation
The timing synchronization device 40 of example includes matched filter 42, timing offset corrector 44, time-domain to frequency domain conversion module 46
With SNR detection module 48.Matched filter 42 carries out matched filtering to input time domain sample point signal, by matched filtering
Time-domain sample point signal export to timing drift correction device 44.44 matching connection filter 42 of timing offset corrector, and
Input the time-domain sample point signal Jing Guo matched filtering.Timing offset corrector 44 can be with reference to from SNR detection module 48
Timing phase estimated value is timed amendment, to obtain revised output time-domain sample point signal.Time-domain is to frequency
Domain conversion module 46 is connected to the output end of matched filter 42, and the time-domain sample point signal that matched filter 42 is exported turns
Change to frequency domain.48 Connection Time of SNR detection module domain obtains frequency domain samples point signal simultaneously to frequency domain conversion module 46
Synchronization is timed in frequency domain.SNR detection module 48 obtains timing phase estimated value, and timing phase estimated value is provided
To timing drift correction device 44.
Known timing synchronization device is to carry out in time-domain, and the amplitude of time-domain signal or phase are filtered vulnerable to matching
The influence of wave device and automatic growth control module and change.The timing synchronization device of the present embodiment changes consistent way,
Frequency domain is timed synchronization, compared in time-domain Timing Synchronization, in frequency domain Timing Synchronization to matched filter and automatic
The performance of gain control module is insensitive.Therefore, the timing synchronization device of the present embodiment is suitable at the receiver of different performance
Module is managed, the robustness of system is improved.
Fig. 5 shows the timing synchronization device based on feed forward method of another embodiment of the present invention.Refering to what is shown in Fig. 5, this reality
The timing synchronization device 50 for applying example includes matched filter 52, timing offset corrector 54, time-domain to frequency domain conversion module
56 and SNR detection module 58.Matched filter 52 carries out matched filtering to input time domain sample point signal, filters through overmatching
The time-domain sample point signal of wave is exported to timing drift correction device 54.54 matching connection filter 52 of timing offset corrector,
And time-domain sample point signal of the input Jing Guo matched filtering.Timing offset corrector 54 can be with reference to from SNR detection module 58
Timing phase estimated value be timed amendment, to obtain revised output time-domain sample point signal.Time-domain is to frequently
Rate domain conversion module 56 is connected to the output end of timing offset corrector 54, the time-domain sample that timing offset corrector 54 is exported
This signal is transformed into frequency domain.58 Connection Time of SNR detection module domain obtains frequency domain sample to frequency domain conversion module 56
This signal is simultaneously timed synchronization in frequency domain.SNR detection module 58 obtains timing phase estimated value, and by timing phase
Estimated value is supplied to timing offset corrector 54.Unlike previous embodiment shown in Fig. 4, time-domain is to frequently in the present embodiment
Rate domain conversion module 56 is changed to obtain time-domain sample point signal from the output end of timing offset corrector 54.
Matched filter 42 and 52 has been used in the above-described embodiments, it will be recognized to those skilled in the art that matching
Filter 42,52 is not necessary device, but can be omitted, and sample point signal in input time domain can directly input at this time
To timing drift correction device 44,54.
In the above-described embodiments, timing offset corrector 44,54 for example can be interpolation filter.
Two above-mentioned embodiments respectively describe feedback method and feed forward method frequency domain timing synchronization device, but can
To understand, frequency domain timing synchronization device of the invention could be applicable to the timing of other methods.
By signal from time-domain be transformed into frequency domain there are many implement method, as an example, Fig. 6 provides this hair
The time-domain of a bright embodiment is to frequency domain conversion module structure.Refering to what is shown in Fig. 6, time-domain is to 46 He of frequency domain conversion module
56 may include asking phase unit 62 and derivation counting unit 64.The time-domain signal of 62 pairs of phase unit inputs is being asked to ask first
Then phase operation carries out operation of differentiating in derivation counting unit 64, output signal is frequency domain signal.For example, phase is sought
Arc tangent (ATAN) or Coordinate Rotation Digital calculation method (Coordinate Rotation specifically can be used in bit manipulation
Digital Computer, CORDIC) scheme realization.Operation i.e. " differentiating " of differentiating operates, and difference operation specifically can be used
It is approximate.
Also there are many concrete implementation methods for frequency domain Timing Synchronization, as an example, Fig. 7 provides one embodiment of the invention
Frequency domain timing module structure.Refering to what is shown in Fig. 7, frequency domain timing module includes Timing Error Detection unit 72, loop filter
Wave device 74 and timing phase processing unit 76.The frequency domain samples point signal of input is introduced into the progress of Timing Error Detection unit 72
Instantaneous Timing Error Detection.In order to increase correctness, the instantaneous timing error value that can be obtained at 74 Duis of loop filter carries out ring
Road filtering, obtains timing phase value.Then at 76 pairs of timing phase processing unit obtain timing phase value according to actual needs into
The appropriate deformation of row, to facilitate interpolation filter to use, the timing phase estimated value of final output gives interpolation filter.
For interpolation filter there are many specific implementation, a fairly simple scheme is to use first-order linear filter,
It is described in detail below.
Assuming that the timing phase estimated is p, remember that its integer part is p_i, fractional part p_f；Assuming that interpolation is filtered
Wave device input time-domain sample point signal sequence be y (k), k=0,1,2 ...；Suitable y (k) signal is selected to make using p_i
For the two adjacent signaling points for the carry out interpolation that interpolation filter uses, it is denoted as y (m) and y (m+1), then interpolation filter
Filtering operation are as follows:
Y_out=y (m)+p_f* (y (m+1)-y (m))
Wherein, y_out is the output sample point signal value of interpolation filter.
It is known that the time-domain Timing Error Detection method of Gardner is (assuming that using feedback method)
E (k)=E_I (k)+E_Q (k)
E_I (k)={ y_out_I (kT)-y_out_I ((k-1) T) } * y_out_I (kT-T/2)
E_Q (k)={ y_out_Q (kT)-y_out_Q ((k-1) T) } * y_out_Q (kT-T/2)
Wherein, y_out_I is the real part of y_out, and y_out_Q is the imaginary part of y_out, and T is symbol period；Signal at least 2
It up-samples again；E (k) is k-th of timing error estimated, consists of two parts, respectively corresponds the real part data and void of signal
Portion's data.
So, as an example, providing a kind of frequency domain Timing Error Detection scheme based on improved Gardner method.
Remember frequency domain Timing Error Detection module input signal sequence be y_f (k), k=0,1,2 ..., then, estimation
Instantaneous timing error value out are as follows:
E (k)={ y_f (kT+T/2)-y_f ((k-1) T+T/2) } * y_f (kT)
Wherein, T is symbol period, at least 2 times of signal up-samplings.
Also there are many different implementations for loop filter, as an example, a kind of relatively simple realization is given below
Scheme:
E_loop (k)=E_loop (k-1)+G*E (k)
Wherein, E_loop, which is represented, passes through the filtered timing error value of loop filter；G represents gain coefficient, determines
The loop bandwidth and convergence rate of loop filter.
Timing phase processing unit 76 can carry out " deformation " to E_loop value according to actual needs, common some " deformations "
Operation citing are as follows:
E_out=C-E_loop
Wherein, E_out exports timing error value for treated, and C is a constant value.In addition, as the case may be, may be used also
The operation such as clipping is carried out to E_out value.
Below with the BDR of bluetooth (Bluetooth, BT) (Basic Data Rate) and/or LE (Low Energy) mode
For example, detailed description of the present invention embodiment.
The BDR mode and LE mode of Bluetooth system are all made of GFSK mode and are modulated, and different has at 2 points:
1, the modulation index value range of BDR mode is h=0.28-0.35, and LE mode
Modulation index value range is h=0.45-0.55；
2, the packet format of the two is different, and Fig. 8 is the packet format of BDR mode, and Fig. 9 is the packet format of LE mode.
Figure 10 shows the transmitter processes process of an example according to the present invention.Refering to what is shown in Fig. 10, this process flow needle
To bluetooth BDR mode and/or LE mode.The bit sequence of input carry out first BPSK mapping 1001 (i.e. bit 0 is mapped as -1,
Bit 1 is mapped as+1), it then carries out up-sampling and operates 1002 (i.e. duplication operations, it is assumed that up-sampling factor F=8 will be inputted
Signal replication 7 times, the identical sample point of 8 values is obtained after up-sampling altogether), then carry out Gaussian pulse shaping, that is, gaussian filtering
Operation 1003, then successively carry out integral 1004, phase-modulation 1005 etc., until entering front end of emission 1010 obtains transmitting signal hair
Directive is aerial.
Figure 11 shows the receiver process flow of an example according to the present invention.With reference to shown in Figure 11, antenna is received from aerial
To radiofrequency signal, tuned device 1101 is down-converted to IF (intermediate frequency) signal, is then converted to by analog-digital converter (ADC) 1102
Digital signal is gone direct current (DC Notch) module 1103 to remove DC (direct current) component, then at 1104 down coversion of down conversion module
To base band, then low-pass filtered device 1105 filters out out-of-band interference, and 1106 pairs of reception signals of matched filter (MF) carry out whole
Shape processing, automatic growth control (AGC) module 1107 later obtain variable gain amplifier (VGA) gain factor, feed back to
Tuner 1101.Next, time-domain signal enters timing offset corrector 1108, the revised sample point of sampling deviation is obtained
Time signal recycles CORDIC module 1109 to obtain the phase value of input signal, difference block 1110 is entered back into, by current sample
The phase value of this point subtracts the phase value of a sample point, obtains differential phase value.Then the differential phase sequence of acquisition is sent
To frequency domain SNR detection module 1111, estimation digital baseband input signal is obtained, for the use of timing offset corrector 1108；Meanwhile
Differential phase signals also give subsequent receiving processing module 1112, finally obtain the bit sequence detected.
In specific implementation, signal can be carried out to 8 times of up-sampling treatment.
In one embodiment, matched filter 1106 can select root raised cosine (SRRC) filter.Timing offset amendment
Device 1108 can select interpolation filter, more specifically can be first-order linear filter.Specific frequency domain SNR detection module
1111 select processing method identical with above-mentioned example.
Figure 12 shows the timing phase estimated value convergence graph of one embodiment of the invention frequency domain regular synchronization scheme, believes in figure
Road is awgn channel, but noiseless.The matched filter that two width phase convergence Fig. 3 and Figure 12 are used is same matched filter,
That is the performance of matched filter is not optimal.It can be recognized from fig. 12 that the timing that frequency domain regular synchronization scheme estimates
Phase convergence has arrived correct timing phase value, i.e. -0.5 sample point.This explanation is compared with time-domain regular synchronization scheme, frequency
Rate domain regular synchronization scheme is insensitive to the performance of matched filter.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (9)
1. a kind of frequency domain time synchronization method, comprising the following steps:
Amendment is timed to time-domain sample point signal in timing offset corrector, obtains revised output time-domain sample
Point signal；
The time-domain sample point signal of the timing offset corrector input terminal or output end is transformed into frequency domain；
It is timed synchronization in frequency domain, obtains timing phase estimated value, and the timing phase estimated value is supplied to the timing
Drift correction device；
Being timed synchronous step in frequency domain includes:
The frequency domain samples point signal of input is subjected to instantaneous Timing Error Detection；
Loop filtering is carried out to the instantaneous timing error value of acquisition, obtains timing phase value；
Be suitable for the deformation that interpolation filter uses to the timing phase value of acquisition, obtain timing phase estimated value,
Wherein assume frequency domain Timing Error Detection input signal sequence be y_f (k), k=0,1,2 ..., then the wink estimated
When timing error value are as follows:
E (k)={ y_f (kT+T/2)-y_f ((k-1) T+T/2) } * y_f (kT)；
Wherein, T is symbol period, at least 2 times of signal up-samplings.
2. frequency domain time synchronization method as described in claim 1, which is characterized in that further include:
Before by time-domain sample point signal incoming timing drift correction device, input time domain sample point signal is made to enter matching
Filter carries out matched filtering.
3. frequency domain time synchronization method as described in claim 1, which is characterized in that the timing offset corrector is filtering interpolation
Device.
4. the method as described in claim 1, which is characterized in that the step of time-domain sample point signal is transformed into frequency domain packet
It includes: the time-domain signal of input successively being carried out to seek phase operation and operation of differentiating, output signal is frequency domain signal.
5. method as claimed in claim 3, which is characterized in that the interpolation filter is first-order linear filter.
6. method as claimed in claim 3, which is characterized in that the filtering operation of the interpolation filter are as follows:
Y_out=y (m)+p_f* (y (m+1)-y (m))；
Wherein p is the timing phase estimated, and p_i is the integer part of p, and p_f is the fractional part of p；Y (k), k=0,1,
2 ... be the time-domain sample point signal sequence of interpolation filter input, and y (m) and y (m+1) are to select suitable y using p_i
(k) the two adjacent signaling points for the carry out interpolation that signal is used as interpolation filter, y_out are the output of interpolation filter
Sample point signal value.
7. the method as described in claim 1, which is characterized in that the function of the loop filter for the loop filtering are as follows:
E_loop (k)=E_loop (k-1)+G*E (k)；
Wherein, E_loop, which is represented, passes through the filtered timing error value of loop filter；G represents gain coefficient, determines loop
The loop bandwidth and convergence rate of filter.
8. the method for claim 7, which is characterized in that carry out being suitable for interpolation filter to the timing phase value of acquisition
The step of deformation used includes:
E_out=C-E_loop；
Wherein, E_out exports timing error value for treated, and C is a constant value.
9. a kind of frequency domain timing synchronization device, comprising:
Timing offset corrector, input time domain sample point signal are simultaneously timed amendment with reference to timing phase estimated value, obtain
Revised output time-domain sample point signal；
Time-domain is to frequency domain conversion module, by the timing offset corrector input terminal or the time-domain sample point signal of output end
It is transformed into frequency domain；And
SNR detection module is timed synchronization in frequency domain, obtains timing phase estimated value, and by the timing phase estimated value
It is supplied to the timing offset corrector；
The SNR detection module is timed synchronous step in frequency domain
The frequency domain samples point signal of input is subjected to instantaneous Timing Error Detection；
Loop filtering is carried out to the instantaneous timing error value of acquisition, obtains timing phase value；
Be suitable for the deformation that interpolation filter uses to the timing phase value of acquisition, obtain timing phase estimated value,
Wherein assume frequency domain Timing Error Detection input signal sequence be y_f (k), k=0,1,2 ..., then the wink estimated
When timing error value are as follows:
E (k)={ y_f (kT+T/2)-y_f ((k-1) T+T/2) } * y_f (kT)；
Wherein, T is symbol period, at least 2 times of signal up-samplings.
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