CN105700462A - Method for realizing high-speed data acquisition and storage with upper computer through PLC - Google Patents
Method for realizing high-speed data acquisition and storage with upper computer through PLC Download PDFInfo
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- CN105700462A CN105700462A CN201610279649.0A CN201610279649A CN105700462A CN 105700462 A CN105700462 A CN 105700462A CN 201610279649 A CN201610279649 A CN 201610279649A CN 105700462 A CN105700462 A CN 105700462A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/12—Plc mp multi processor system
- G05B2219/1208—Communication, exchange of control, I-O data between different plc
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Abstract
The invention discloses a method for realizing high-speed data acquisition and storage with an upper computer through a PLC. According to the method, the size of a data buffer area and a sampling period are set through the upper computer, and multiple registers are selected in the PLC to act as indicating bits for data acquisition and storage so that the PLC and the upper computer are enabled to cooperatively work, and relatively high sampling frequency can be achieved. Overflow of the data is determined by monitoring the value of the registers in the PLC so as to be more accurate and reliable; meanwhile, use of a data acquisition card is avoided so that funds can be saved and space of acquisition equipment can be saved; and the method is suitable for various occasions.
Description
Technical field
The present invention relates to data acquisition and storage method, particularly relate to a kind of by the PLC method realizing high-speed data acquisition and storage with host computer。
Background technology
Data acquisition is by the indispensable link of Digital Signal Processing, in actual production, it is frequently necessary to realize the instantaneous acquiring of data, to complete monitoring and the process of data, therefore, the effect that data acquisition is played in whole automated system is more and more crucial, and its application has been deep in the every field of signal processing。At high speed, high-precision data acquisition is increasingly becoming the application trend of automation control area。
Conventional collecting method is that host computer provides acquisition instructions, the instant data read in are passed to host computer by PLC (programmable logic controller (PLC)), host computer one data of one scan period storage, the method shortcoming is will data to be processed host computer each scan period, the too much time spends in the data transmission of host computer and PLC and processes, and is difficulty with high-speed data acquisition。At present, high-speed data acquisition mainly utilizes data collecting card to realize, the method advantage be data acquisition up to upper frequency, shortcoming is that capture card price is higher, and its buffer size is not easily self-defined, and capture card takies unnecessary hardware space；Further, since capture card gathers data dependence in host computer procedure, it is easily caused data during host computer job insecurity and overflows, it is thus achieved that invalid data。
After existing patent and document are retrieved, research finds, notification number be the patent disclosure of 102413035 " a kind of method realizing rapid data collection ", data in plc data relief area are carried out the compression of basic data type by this invention, by the packet that the Ethernet reception PLC cycle sends, shortcoming is in that need to data block format and order be defined, exploitation service-specific, adds the difficulty of host computer storage data；Liu Yueyin is published in paper on " industrial control computer " (21 volume the 6th phases in 2008) " design of high-speed data acquistion system based on S7-400PLC and WinCC " and Cheng Weijing is published in the paper " high-speed data acquistion system based on S7 400PLC " on " electrical applications " (30 volume the 4th phases in 2011) and describes employing specialty Configuration software WinCC and coordinate PLC to realize data high-speed collection, owing to WinCC is expensive, and during operating system refitting, WinCC need to be reinstalled and monitor system, be not easy to user and use。
Summary of the invention
Goal of the invention: the present invention is directed to prior art Problems existing, it is provided that a kind of method of Data acquisition and storage, the method realizes data high-speed collection and storage by PLC with host computer, is user-friendly to。
Technical scheme: of the present invention realize the method for high-speed data acquisition by PLC and host computer and include:
(1) PLC chooses internal register I as indicating bit I, internal register II is as indicating bit II, internal register III is as indicating bit III, internal register IV is as indicating bit IV, internal register U arranges position as buffer size, internal register V arranges position as sampling period parameter, and internal register Z stores position as present sample signal, and timer internal T1, T2 are as intervalometer；
(2) host computer writes indicating bit I, indicating bit II, indicating bit III, indicating bit IV by 0,1,0,0 respectively, buffer size n is write internal register U, determine that PLC internal register X1, X2, X3 ..., Xn are as the first relief area, internal register Y1, Y2, Y3 ..., Yn are as the second relief area, sampling period parameter k is write internal register V, it is determined that the timing of T1, T2 is k and T1, the product of T2 minimum timing time；
(3) host computer writes indicating bit I by 1, and starts to gather data；
(4), after the analog signals collected is converted into digital quantity by PLC, internal register Z is write；
(5) using T1 as intervalometer, the data of internal register Z are collected in the internal register of the first relief area by timing successively, and the value of indicating bit II is set to 2；
(6) if now the value of indicating bit III is 2, then the value of indicating bit IV is set to 1；Otherwise the value of indicating bit III is set to 1；
(7) using T2 as intervalometer, the data of internal register Z are collected in the internal register of the second relief area by timing successively, and the value of indicating bit II is set to 1；
(8) if now the value of indicating bit III is 1, then the value of indicating bit IV is set to 1；Otherwise the value of indicating bit III is set to 2；Return execution (5) and be circulated data acquisition；
(9), while loop-around data gathers, host computer is with the time t value for interval scan once each indicating bit；When the value that host computer scans indicating bit III is 1, the data that disposable storage the first relief area gathers, then write indicating bit III by 0；When the value that host computer scans indicating bit III is 2, the data that disposable storage the second relief area gathers, then write indicating bit III by 0；Send data when the value that described host computer scans IV is 1 and overflow warning；To stop data collection, then host computer writes indicating bit I by 0。
Further, step (5) specifically includes:
(51) T1 starts working, and T2 does not work；
(52) when T1 timing then, PLC by the internal register Z data acquisition read in internal register X1, T1 reset and reclocking；
(53) when T1 timing then, PLC by the internal register Z data acquisition read in internal register X2, T1 reset and reclocking；
(54) circulate according to this, until by the internal register Z data acquisition read in internal register Xn；
(55) value of indicating bit II is set to 2 by PLC。
Further, step (7) specifically includes:
(71) T2 starts working, and T1 does not work；
(72) when T2 timing then, PLC by the internal register Z data acquisition read in internal register Y1, T2 reset and reclocking；
(73) when T2 timing then, PLC by the internal register Z data acquisition read in internal register Y2, T2 reset and reclocking；
(74) circulate according to this, until by the internal register Z data acquisition read in internal register Yn；
(75) value of indicating bit II is set to 1 by PLC。
Wherein, PLC passes through indexed mode by data acquisition to the first relief area and the second relief area。
Beneficial effect: compared with prior art, it has the remarkable advantages that the present invention: 1, high-speed data acquisition and storage can be realized by PLC with host computer。2, the size of relief area and sampling period are arranged by host computer, convenient and swift。3, because of host computer duty susceptible, and PLC stable working state, determine whether data overflow by monitoring PLC internal register value, more accurately and reliably。4, avoid the use of data collecting card, save fund, save the space of collecting device simultaneously。Due to the industrial control equipment that PLC and host computer are most-often used, it is adaptable to various places。
Accompanying drawing explanation
Fig. 1 is the connection diagram of the system configuration of the present embodiment；
Fig. 2 is the workflow schematic diagram of PLC；
Fig. 3 is the workflow schematic diagram of host computer。
Detailed description of the invention
As it is shown in figure 1, the hardware configuration that the present embodiment is based on includes: pressure transducer 1, A/D modular converter 2, PLC main frame 3, host computer 4。Described pressure transducer 1 is for gathering the analogue signal of pressure；A/D modular converter 2 is connected with pressure transducer 1 and the analog signals of collection is converted to digital quantity；Described PLC main frame 3 is connected for gathering digital quantity with A/D modular converter 2；Described host computer 4 and PLC main frame 3 communication are used for storing data after connecting。
The main frame that PLC main frame 3 selects Delta model to be DVP12SE11T, the high-Speed Data-Acquisition Module that A/D modular converter 2 selects Delta model to be DVP04AD-SL。Ethernet communication pattern is adopted between PLC main frame 3 and host computer 4。PLC main frame 3 adopts Delta special programming software ISPSoft2.05 to be programmed, it is achieved the function of high-speed data acquisition；Receive the command signal that host computer 4 sends over, with host computer 4 collaborative work, it is achieved the function of high-speed data processing simultaneously。Host computer 4 is PC industrial computer, described host computer 4 program is developed by VisualStudio2012, and the program function of host computer 4 exploitation mainly includes arranging with PLC main frame 3 communication, buffer size, the sampling period is arranged, beginning and the stopping of high-speed data acquisition and storage, scan or arrange indicator bit value, successively memory buffer data。
As shown in Figures 2 and 3, the method for the present embodiment specifically includes following steps:
S101, PLC choose internal register I as indicating bit I, internal register II is as indicating bit II, internal register III is as indicating bit III, internal register IV is as indicating bit IV, internal register U arranges position as buffer size, internal register V arranges position as sampling period parameter, and internal register Z stores position as present sample signal, and timer internal T1, T2 are as intervalometer。
Such as, during enforcement, PLC can choose internal register D1 as indicating bit I, internal register D2 is as indicating bit II, internal register D3 as indicating bit III, and internal register D4 is as indicating bit IV, internal register D5 arranges position as buffer size, internal register D6 arranges position as sampling period parameter, and internal register D100 stores position as present sample signal, and timer internal T246, T247 are as intervalometer。
S102, host computer are set up after communication is connected with PLC, host computer writes indicating bit I, indicating bit II, indicating bit III, indicating bit IV by 0,1,0,0 respectively, buffer size n is write internal register U, determine that PLC internal register X1, X2, X3 ..., Xn are as the first relief area, internal register Y1, Y2, Y3 ..., Yn are as the second relief area, sampling period parameter k is write internal register V, it is determined that the timing of T1, T2 is k and T1, the product of T2 minimum timing time。
Such as, during enforcement, if buffer size n is 100, then buffer size 100 is write internal register D5, determining that PLC internal register D201, D202 ..., D300 are as the first relief area, internal register D401, D402 ..., D500 are as the second relief area；The minimum timing time of two timer internals T246, T247 choosing is 1 millisecond, if sampling period parameter k is 10, then write internal register D6 by 10, then the timing of T246, T247 is 10 milliseconds, it may be achieved the function by PLC main frame with host computer collection with 100 data of storage per second。
S103, host computer write indicating bit I by 1, and start to gather data。
After the analog signals collected is converted into digital quantity by A/D modular converter by S104, PLC, write internal register Z。
Such as, during enforcement, after the analog signals collected can being converted into digital quantity by A/D modular converter by PLC, write internal register D100。
S105, using T1 as intervalometer, the data of internal register Z are collected in the internal register of the first relief area by timing successively, and the value of indicating bit II is set to 2。
This step specifically includes step: T1 starts working, and T2 does not work；When T1 timing then, PLC by the internal register Z data acquisition read in internal register X1, T1 reset and reclocking；When T1 timing then, PLC by the internal register Z data acquisition read in internal register X2, T1 reset and reclocking；Circulate according to this, until by the internal register Z data acquisition read in internal register Xn；The value of indicating bit II is set to 2 by PLC。Wherein, PLC passes through indexed mode by data acquisition to the first relief area, concretely comprises the following steps: PLC chooses index register X1+E1；Wherein, E1 initial value is 0；When T1 timing then, PLC is by the internal register Z data acquisition read in index register X1+E1, and by E1=E1+ △ E, wherein, △ E is increment；Mode according to this, until by the internal register Z data acquisition read in Xn；The value of E1 is set to 0 by PLC。
Such as, during enforcement, the internal register D100 data acquisition read in can be 0 to index register D201+E1, E1 by PLC, and after then E1 adds 1 by addition instruction, value is 1, is not equal to the value of internal register D5；T246 is resetted by PLC, reclocking, until by the internal register D100 data acquisition read in internal register D201+99, after then E1 adds 1 by addition instruction, value is 100, equal to the value of internal register D5, then the value of E1 is set to 0。
If the value of S106 now indicating bit III is 2, then the value of indicating bit IV is set to 1；Otherwise the value of indicating bit III is set to 1。
S107, using T2 as intervalometer, the data of internal register Z are collected in the internal register of the second relief area by timing successively, and the value of indicating bit II is set to 1。
This step specifically includes: T2 starts working, and T1 does not work；When T2 timing then, PLC by the internal register Z data acquisition read in internal register Y1, T2 reset and reclocking；When T2 timing then, PLC by the internal register Z data acquisition read in internal register Y2, T2 reset and reclocking；Circulate according to this, until by the internal register Z data acquisition read in internal register Yn；The value of indicating bit II is set to 1 by PLC。Wherein, PLC passes through indexed mode by data acquisition to the second relief area, and its concrete steps are similar with the first relief area, particularly as follows: PLC chooses index register Y1+E2；Wherein, E2 initial value is 0；When T2 timing then, PLC is by the internal register Z data acquisition read in index register Y1+E2, and by E2=E2+ △ E, wherein, △ E is increment；Mode according to this, until by the internal register Z data acquisition read in Yn；The value of E2 is set to 0 by PLC。
Such as, during enforcement, the internal register D100 data acquisition read in can be 0 to index register D401+E2, E2 by PLC, and after then E2 adds 1 by addition instruction, value is 1, is not equal to the value of internal register D5；T247 is resetted by PLC, reclocking, until by the internal register D100 data acquisition read in internal register D401+99, after then E2 adds 1 by addition instruction, value is 100, equal to the value of internal register D5, then the value of E2 is set to 0。
If the value of S108 now indicating bit III is 1, then the value of indicating bit IV is set to 1；Otherwise the value of indicating bit III is set to 2；Return execution S105 and be circulated data acquisition。
While S109, loop-around data gather, host computer is with the time t value for interval scan once each indicating bit；When the value that host computer scans indicating bit III is 1, the data that disposable storage the first relief area gathers, then write indicating bit III by 0；When the value that host computer scans indicating bit III is 2, the data that disposable storage the second relief area gathers, then write indicating bit III by 0；Send data when the value that host computer scans IV is 1 and overflow warning；To stop data collection, then host computer writes indicating bit I by 0。Such as, during enforcement, host computer can with the time t=200ms value for interval scan once each indicating bit；When the value that host computer scans indicating bit III is 1, the data that disposable storage the first relief area D201, D202, D203 ..., D300 gather, then write indicating bit III by 0；When the value that host computer scans indicating bit III is 2, the data that disposable storage the second relief area D401, D402, D403 ..., D500 gather, then write indicating bit III by 0；Send data when the value that host computer scans IV is 1 and overflow warning；To stop data collection, then host computer writes indicating bit I by 0。
Should be noted that, step S105 to step S108 is a circulation, while step S105 to step S108 circulation, step S109 is also performing, namely while PLC is circulated data acquisition, host computer, also in the value of scan round indicating bit, storage data and change indicating bit, when host computer writes indicating bit I by 0, stops data acquisition。
Claims (7)
1. the method realizing high-speed data acquisition and storage by PLC and host computer, it is characterised in that the method includes:
(1) PLC chooses internal register I as indicating bit I, internal register II is as indicating bit II, internal register III is as indicating bit III, internal register IV is as indicating bit IV, internal register U arranges position as buffer size, internal register V arranges position as sampling period parameter, and internal register Z stores position as present sample signal, and timer internal T1, T2 are as intervalometer；
(2) host computer writes indicating bit I, indicating bit II, indicating bit III, indicating bit IV by 0,1,0,0 respectively, buffer size n is write internal register U, determine that PLC internal register X1, X2, X3 ..., Xn are as the first relief area, internal register Y1, Y2, Y3 ..., Yn are as the second relief area, sampling period parameter k is write internal register V, it is determined that the timing of T1, T2 is k and T1, the product of T2 minimum timing time；
(3) host computer writes indicating bit I by 1, and starts to gather data；
(4), after the analog signals collected is converted into digital quantity by PLC, internal register Z is write；
(5) using T1 as intervalometer, the data of internal register Z are collected in the internal register of the first relief area by timing successively, and the value of indicating bit II is set to 2；
(6) if now the value of indicating bit III is 2, then the value of indicating bit IV is set to 1；Otherwise the value of indicating bit III is set to 1；
(7) using T2 as intervalometer, the data of internal register Z are collected in the internal register of the second relief area by timing successively, and the value of indicating bit II is set to 1；
(8) if now the value of indicating bit III is 1, then the value of indicating bit IV is set to 1；Otherwise the value of indicating bit III is set to 2；Return execution (5) and be circulated data acquisition；
(9), while loop-around data gathers, host computer is with the time t value for interval scan once each indicating bit；When the value that host computer scans indicating bit III is 1, the data that disposable storage the first relief area gathers, then write indicating bit III by 0；When the value that host computer scans indicating bit III is 2, the data that disposable storage the second relief area gathers, then write indicating bit III by 0；Send data when the value that host computer scans IV is 1 and overflow warning；To stop data collection, then host computer writes indicating bit I by 0。
2. according to claim 1 by the PLC method realizing high-speed data acquisition and storage with host computer, it is characterised in that: step (5) specifically includes:
(51) T1 starts working, and T2 does not work；
(52) when T1 timing then, PLC by the internal register Z data acquisition read in internal register X1, T1 reset and reclocking；
(53) when T1 timing then, PLC by the internal register Z data acquisition read in internal register X2, T1 reset and reclocking；
(54) circulate according to this, until by the internal register Z data acquisition read in internal register Xn；
(55) value of indicating bit II is set to 2 by PLC。
3. according to claim 1 by the PLC method realizing high-speed data acquisition and storage with host computer, it is characterised in that: step (7) specifically includes:
(71) T2 starts working, and T1 does not work；
(72) when T2 timing then, PLC by the internal register Z data acquisition read in internal register Y1, T2 reset and reclocking；
(73) when T2 timing then, PLC by the internal register Z data acquisition read in internal register Y2, T2 reset and reclocking；
(74) circulate according to this, until by the internal register Z data acquisition read in internal register Yn；
(75) value of indicating bit II is set to 1 by PLC。
4. according to claim 1 by the PLC method realizing high-speed data acquisition and storage with host computer, it is characterised in that: PLC passes through indexed mode by data acquisition to the first relief area。
5. according to claim 4 by the PLC method realizing high-speed data acquisition and storage with host computer, it is characterised in that: described PLC passes through indexed mode by data acquisition to the first relief area, specifically includes:
PLC chooses index register X1+E1；Wherein, E1 initial value is 0；
When T1 timing then, PLC is by the internal register Z data acquisition read in index register X1+E1, and by E1=E1+ △ E, wherein, △ E is increment；
Mode according to this, until by the internal register Z data acquisition read in Xn；
The value of E1 is set to 0 by PLC。
6. according to claim 1 by the PLC method realizing high-speed data acquisition and storage with host computer, it is characterised in that: PLC passes through indexed mode by data acquisition to the second relief area。
7. according to claim 6 by the PLC method realizing high-speed data acquisition and storage with host computer, it is characterised in that: described PLC passes through indexed mode by data acquisition to the first relief area, specifically includes:
PLC chooses index register Y1+E2；Wherein, E2 initial value is 0；
When T2 timing then, PLC is by the internal register Z data acquisition read in index register Y1+E2, and by E2=E2+ △ E, wherein, △ E is increment；
Mode according to this, until by the internal register Z data acquisition read in Yn；
The value of E2 is set to 0 by PLC。
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