CN105677595A

CN105677595A - FPGA method achieving computation speedup and PCIESSD storage simultaneously

Info

Publication number: CN105677595A
Application number: CN201610039292.9A
Authority: CN
Inventors: 肖飞
Original assignee: One Way Information Technology (shanghai) Co Ltd
Current assignee: One Way Information Technology (shanghai) Co Ltd
Priority date: 2016-01-21
Filing date: 2016-01-21
Publication date: 2016-06-15

Abstract

The invention discloses an FPGA method achieving computation speedup and PCIE SSD storage simultaneously. An FPGA is used, an SSD controller and an algorithm accelerator are integrated in the FPGA, the FPGA is further internally provided with a DDR controller and a direct memory read module DMA, and the direct memory read module DMA is connected with the SSD controller, the DDR controller and the algorithm accelerator respectively. According to the FPGA method achieving computation speedup and PCIE SSD storage simultaneously, the two functions of computation speedup and SSD storage are achieved on PCIE equipment, the layout difficult is reduced, overall power consumption of server nodes is reduced, and the cost of an enterprise is reduced.

Description

A kind of simultaneously realization calculates the FPGA method accelerated with PCIESSD stores

Technical field

The present invention relates to a kind of FPGA method, specifically a kind of simultaneously realization calculates the FPGA method accelerated with PCIESSD stores.

Background technology

Along with the fast development of informationization, high-density computation requirement gets more and more, and computing power and storage IO (I/O) Capability Requirement to Single-Server node are more and more higher. At present, enterprise market extensively adopts PCIESSD to improve the IO ability stored; And for computing power, generally adopt GPU(GraphicsProcessingUnit) accelerate card or FPGA acceleration card. Although it is strong that enterprise-level GPU accelerates card computing power, but price is expensive, power consumption height, adds enterprise cost. And FPGA acceleration card relative GPU acceleration card price is lower, low in energy consumption, but use PCIESSD and FPGA to accelerate to block simultaneously, not only to be taken multiple server slot, and increase more power consumption, add the cost of enterprise.

Summary of the invention

It is an object of the invention to provide a kind of simultaneously realization and calculate the FPGA method accelerated with PCIESSD stores, to solve in above-mentioned background technology the problem proposed.

For achieving the above object, the present invention provides following technical scheme:

A kind of simultaneously realization calculates the FPGA method accelerated with PCIESSD stores, employ a slice FPGA, SSD controller and algorithm accelerator it is integrated with in FPGA, SSD controller is further comprises in FPGA, described SSD controller is by logic realization in FPGA, the flash array of management and control SSD, SSD controller is by PCIE interface and server node communication.

As the scheme that the present invention is further: described algorithm accelerator is realized by fpga logic, by PCIE interface and server node communication.

As the scheme that the present invention is further: further comprises DDR controller in described FPGA.

As the present invention's further scheme: further comprises direct internal memory read module DMA in described FPGA, direct internal memory read module DMA connects SSD controller, DDR controller and algorithm accelerator respectively.

Compared with prior art, the invention has the beneficial effects as follows: the present invention achieves algorithm in a PCIE device and accelerates to store two functions with SSD, decreases layout difficulty, reduces the overall power of server node, reduces the cost of enterprise.

Accompanying drawing explanation

Fig. 1 realizes calculating the structural representation accelerating the FPGA method with PCIESSD storage simultaneously; Fig. 2 realizes calculating the schema accelerating the FPGA method with PCIESSD storage simultaneously.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.

Refer to Fig. 1, in the embodiment of the present invention, a kind of simultaneously realization calculates the FPGA method accelerated with PCIESSD stores, employ a slice FPGA, being integrated with SSD controller and algorithm accelerator in FPGA, further comprises SSD controller in FPGA, described SSD controller is by logic realization in FPGA, the flash array of management and control SSD, SSD controller is by PCIE interface and server node communication; Described algorithm accelerator is realized by fpga logic, by PCIE interface and server node communication; DDR controller is further comprises in described FPGA; Further comprises direct internal memory read module DMA in described FPGA, direct internal memory read module DMA connects SSD controller, DDR controller and algorithm accelerator respectively.

The principle of work of the present invention is: refer to Fig. 1, and server node is communicated with FPGA by PCIE interface; The inner directly internal memory read module DMA of FPGA realizes PCIETLP(TransactionLayerPackage) agreement layer encapsulation and resolving, obtain order, distribution and converge data, reporting interruption; SSD controller receives order and the data that direct internal memory read module DMA distributes, according to order control NANDFLASH array; Algorithm accelerator receives order and the data that direct internal memory read module DMA distributes, and does the calculating of respective algorithms according to order; DDR controller is that direct internal memory read module DMA and algorithm accelerator are data cached.

The performing step of the present invention is as follows: 1, according to FPGA, NANDFLASH, DDRSDRAM of actual computation density demand and SSD Capacity Selection appropriate resources, according to, shown in Fig. 1, designing hardware.

2, FPGA workflow diagram according to Fig. 2 writes the RTL(RegisterTransferLevel of the direct internal memory read module DMA of key modules) code.

3, according to Fig. 1 definition FPGA internal structure in FPGA top layer exampleization, connect each function module, write the RTL top code of FPGA.

4, FPGA workflow diagram according to Fig. 2 writes emulation platform, completes system emulation.

5, adding temporal constraint in FPGA compiling instrument, compiling RTL code, obtains recordable paper.

6, schema according to Fig. 2 writes corresponding software-driven.

To those skilled in the art, it is clear that the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit or the essential characteristic of the present invention, it is possible to realize the present invention in other specific forms. Therefore, no matter from which point, embodiment all should be regarded as exemplary, and right and wrong are restrictive, the scope of the present invention is limited by claims instead of above-mentioned explanation, it is intended that all changes in the implication of the equivalent important document dropping on claim and scope included in the present invention. Any Reference numeral in claim should be considered as the claim involved by limiting.

In addition, it is to be understood that, although this specification sheets is described according to enforcement mode, but not each enforcement mode only comprises an independent technical scheme, this kind of narrating mode of specification sheets is only for clarity sake, those skilled in the art should by specification sheets integrally, and the technical scheme in each embodiment through appropriately combined, can also form other enforcement modes that it will be appreciated by those skilled in the art that.

Claims

1. one kind realizes calculating the FPGA method accelerated with PCIESSD stores simultaneously, it is characterized in that, employ a slice FPGA, SSD controller and algorithm accelerator it is integrated with in FPGA, SSD controller is further comprises in FPGA, described SSD controller is by logic realization in FPGA, and the flash array of management and control SSD, SSD controller is by PCIE interface and server node communication.

2. according to claim 1 simultaneously realization calculates the FPGA method accelerated with PCIESSD stores, it is characterised in that, described algorithm accelerator is realized by fpga logic, by PCIE interface and server node communication.

3. according to claim 1 simultaneously realization calculates the FPGA method accelerated with PCIESSD stores, it is characterised in that, further comprises DDR controller in described FPGA.

4. according to claim 1 simultaneously realization calculates the FPGA method accelerated with PCIESSD stores, it is characterized in that, further comprises direct internal memory read module DMA in described FPGA, direct internal memory read module DMA connects SSD controller, DDR controller and algorithm accelerator respectively.