CN105677298A - Method and device for extending immediate operand in computer instruction - Google Patents
Method and device for extending immediate operand in computer instruction Download PDFInfo
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- CN105677298A CN105677298A CN201511028580.6A CN201511028580A CN105677298A CN 105677298 A CN105677298 A CN 105677298A CN 201511028580 A CN201511028580 A CN 201511028580A CN 105677298 A CN105677298 A CN 105677298A
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
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Abstract
The invention discloses a method and device for extending an immediate operand in a computer instruction. At least one immediate operand extending instruction is newly increased in an RISC instruction system, during the programming process, an immediate operand the digit number of which is larger than the length of an immediate operand domain of an execution instruction is divided into a high-order immediate operand field and a low-order immediate operand field, the high-order immediate operand field is subjected to signed extension or unsigned extension and then is stored in the immediate operand domain of the immediate operand extending instruction, and the low-order immediate operand field just fills up the immediate operand domain of the execution instruction; during the instruction fetching process, the newly-increased immediate operand extending instruction and the execution instruction following closely are sent into respective decoders synchronously to carry out decoding; during the decoding process, the immediate operand output by the immediate operand extending instruction decoder is subjected to logical left shift and then is merged with the immediate operand output by the execution instruction decoder, after the merging process, the immediate operand the digit number of which is larger than the length of the immediate operand domain of the execution instruction is obtained. By employing the method for extending the immediate operand in the computer instruction, the program execution efficiency can be greatly improved, and time and space are saved.
Description
Technical field
The invention belongs to computer realm, be specifically related to a kind of by the method and apparatus of immediate extension in computer instruction so that RISC computer instruction can obtain figure place more than the immediate performing instruction number field immediately.
Background technology
Currently, computer system is broadly divided into CISC system and RISC system, has the instruction specification of two kinds of different-styles respectively corresponding to both systems. CISC system occurs the earliest, and it is relatively larger that its instruction set is characterized as being scale, and the immediate that instruction can be carried can be very big, and each instruction is different in size causes, and most representativeness is exactly x86 instruction set; And RISC system occurs that ratio is later, it is smaller that its instruction set is characterized as being scale, only includes conventional instruction, and each command length is all consistent, and the immediate that instruction can be carried is smaller, and most representativeness is exactly ARM instruction set and MISP instruction set. Although CISC system is different with the instruction style of RISC system, but they common ground are all include operation code and some operands in instruction, and these operands are probably register name and are also likely to be immediate. Computer instruction structure such as table 1. Wherein operation code is used for controlling decoder, makes decoder output perform the operation switch of this instruction, also isolates each operand simultaneously.
Table 1 computer instruction structure
| Operation code | Some operands (or immediate) |
Instruction is read out current computer systems conventional circuit shown in Fig. 1 and decoding processes.
In FIG, instruction fetch circuit is to be made up of U1, U2, U3, U4, wherein U1 is data selector, it is used for selecting relatively to redirect PC increment, and U2 is adder, completes the calculating of next instruction address, U3 is data selector, it is for selecting the pointer of next instruction, and U4 is PC depositor, and it has instruction address value; U5 is memory under program, the inside computer program stored instruction; U6 performs command register; U7 is carried out command decoder, and its function is that the instruction performing command register output is decoded.
In FIG, the work process of its circuit is:
The first step is the instruction fetch phase: after being completed the calculating of next instruction address by U1, U2, U3, U4, PC (U4) is to the address value of memory under program (U5) output order, then memory under program (U5) output order on its output bus.
Second step is the decoding stage: the instruction that memory under program (U5) exports is latched in execution command register (U6), perform command decoder (U7) directly the instruction performing command register (U6) inner to be decoded, decode out the information such as the operation signal (OP) of this instruction, destination register number (Rd), source register number (Rs), source register number (Rt), immediate (#imm).
Instruction reading and decoding treatment process from the description above are it can be seen that in cisc instruction system, owing to CISC data processing instructions can carry the immediate of several byte, as long as so sufficiently fast for instruction fetch circuit operation cisc instruction system, obtaining big immediate is not difficult matter, harm is due to each bar command length inconsistent (from 1 byte to 15 bytes not etc.), in order to read complete instruction, instruction fetch circuit must be analyzed the operation code of every instruction and just can determine that the length of this instruction, then complete instruction could be read, the instruction fetch circuit of obvious CISC is considerably complicated, furthermore owing to CISC data processing instructions needs expression to carry several byte immediate length, so cisc instruction set quantity is quite huge, more much bigger than RISC instruction scale, benefit is able to save the space of instruction storage. and RISC instruction system is just different, due in the instruction system of RISC the length specification of instruction only have 1,2 kind, such as ARM, MIPS of 32, its command length is all 32 (i.e. 4 bytes), its benefit is to simplify instruction fetch circuit so that instruction fetch circuit just can read complete instruction without the operation code of analysis instruction. but owing to command length is not long, so the carry-on immediate of the instruction of RISC is general all little, immediate that the data operation instruction of such as ARM is carried is maximum is 12, and immediate that the data operation instruction of MIPS instruction system is carried maximum be 16, it is impossible for wanting the immediate that these RISC instruction systems carry 32, because its command length only has 32, so to obtain 32 immediates in RISC instruction system just take many twists and turns, method conventional at present has two kinds: the first is that method is read in segmentation, specifically first read the immediate of high 16, read the immediate of low 16 again, thus forming 32 immediates, in order to support that method is read in this segmentation, the corresponding instruction that has been all tailor of almost all of RISC instruction system, MOVW and the MOVT instruction of such as ARM, LUI and the ADDIU instruction of MIPS, the second is memory access method, specifically 32 immediates is placed on from the not far place of current PC value as constant, then use the access instruction relevant to a PC reading it. but whether use which kind of read method, the immediate that will obtain 32 is all time-consuming, and 2 cycles how will be spent just to complete.
Such as to process expression formula: R2=R3&0x12345678, wherein immediate 0x12345678 is 32 unsigned numbers, for MIPS, due to logic and operation instruction ANDI $ d, $ s, the number field immediately of #imm16 only has 16, and the figure place of above-mentioned expression formula immediate 0x12345678 is obviously more than 16, and 32 immediate 0x12345678 are cannot load ANDI d, $ s, the number field immediately of #imm16, so instruction ANDI d, s cannot directly be used, #imm16, instruction AND $ d, $ s, $ t can only be used.The way of so current MIPS is:
1, segmentation is used to read method:
LUI $ 1, #1234H; (obtaining high 16 bit constants, 1 cycle time will be spent)
ADDIU $ 1, #5678H; (obtaining low 16 bit constants, 1 cycle time will be spent)
AND $ 2, $ 3, $ 1;
2, memory access method is used:
LWPC $ 1, [PC, #offest]; (2 cycle times are spent in this instruction)
AND $ 2, $ 3, $ 1;
As can be seen here, no matter using which kind of method, MIPS processes R2=R3&0x12345678 to be needed to spend 3 cycle times altogether, and wherein obtaining 32 bit constant 0x12345678 needs to spend 2 cycle times.
Summary of the invention
The deficiency that big immediate execution efficiency is low is obtained in order to solve existing RISC instruction system, maintain again RISC instruction system simplify, the advantage of uniform length, the present invention proposes a kind of by the method for immediate extension in computer instruction, and profit RISC computer instruction in this way also is able to quickly obtain a units and exceedes the immediate performing instruction number field immediately.
A kind of by the method for immediate extension in computer instruction, at least setting up an immediate extended instruction and a corresponding immediate extended instruction decoder in existing RISC computer instruction system, this immediate extended instruction includes operation code and number field immediately; Detailed process is as follows:
In instruction compiling procedure, more than the immediate of the length of the number field immediately performing instruction, one units being divided into two fields, one is high-order immediate field, and another is low level immediate field; Described high-order immediate field is further filled with the number field immediately of above-mentioned newly-increased immediate extended instruction after signed number or unsigned number extend, described low level immediate field then inserts the number field immediately of described execution instruction, and requires the length length equal to the number field immediately of described execution instruction of described low level immediate field; Additionally above-mentioned newly-increased immediate extended instruction wants preposition in the described execution instruction carrying this low level immediate field, and other instruction can not be inserted in centre;
In instruction fetch process, above-mentioned newly-increased immediate extended instruction is sent into immediate extended instruction depositor and the execution instruction followed closely after this immediate extended instruction is sent into execution command register by instruction fetch circuit synchronization;
In Instruction decoding process, while the instruction that immediate extended instruction depositor exports is decoded by immediate extended instruction decoder, perform command decoder also the instruction performing command register output to be decoded, the immediate of immediate extended instruction decoder output merges with the immediate performing command decoder output after logic left shifts again, amalgamation result obtains the units immediate more than the length of the number field immediately performing instruction, and the numerical value of this immediate is equal with the numerical value of the immediate being split in above-mentioned instruction compiling procedure.
Described immediate extended instruction is a non-executive instruction, and only to decoding this stage just termination, it need not experience the stage of execution, write-back.
By arranging a buffer in instruction fetch circuit, described newly-increased immediate extended instruction is postponed a location of instruction, to wait the arrival performing instruction following closely so that above-mentioned newly-increased immediate extended instruction and execution instruction following closely can be synchronized to be respectively fed to respective decoder and decode by instruction fetch circuit; Described buffer is depositor.
Described immediate extended instruction decoder is controlled by the symbolic number marking signal that execution command decoder is sent here when decoding, finally decoding one immediate of output and a decoded state marking signal, and perform following process: if the instruction of above-mentioned newly-increased immediate extended instruction depositor output is above-mentioned newly-increased immediate extended instruction, then it is true for arranging this decoded state marking signal;Otherwise, if the instruction of above-mentioned newly-increased immediate extended instruction depositor output is not above-mentioned newly-increased immediate extended instruction, then arranging this decoded state marking signal is false and to arrange the immediate of this immediate extended instruction decoder output be 0 value; It is described that to perform the symbolic number marking signal that command decoder sends here be signed number or unsigned number for selecting the immediate that this immediate extended instruction decoder for decoding exports.
Described execution command decoder decodes the figure place and a symbolic number marking signal that export a logic left displacement in decoding process according to the current operation code performing instruction decoded, the figure place of described logic left displacement is equal to the length of its number field immediately performing instruction currently decoded, and described symbolic number marking signal indicates that the immediate represented by executing instruction operations code of current decoding is signed number or unsigned number; Additionally being controlled by the decoded state marking signal of above-mentioned immediate extended instruction decoder output, its controlled process is: if this decoded state marking signal is true, then the immediate performing command decoder decoding output is a unsigned number; This decoded state marking signal is false else if, then performing command decoder has symbol or without symbol immediate by decoding output one according to the requirement of operation code.
A kind of device realizing described method, including instruction fetch circuit, performs command register, execution command decoder, described execution command decoder, and it, for the instruction performing command register output is decoded, is characterized in that:
One immediate extended instruction depositor, for storing the instruction sent here by instruction fetch circuit;
One immediate extended instruction decoder, for the instruction of above-mentioned immediate extended instruction depositor output is decoded, additionally it is also controlled by the symbolic number marking signal performing command decoder output of above-mentioned improvement, finally decoding one immediate of output and a decoded state marking signal;
One logic left shift circuit, for receiving the figure place from the logic left displacement performing command decoder output, and can complete the immediate of above-mentioned immediate extended instruction decoder output is carried out logic left displacement according to the requirement of the figure place that this logic left shifts, result one immediate of output;
One data consolidation circuit is for carrying out logic or computing or additive operation by the immediate performing command decoder output of the immediate of above-mentioned logic left shift circuit output and improvement, and operation result exports an immediate;
Described execution command decoder is also controlled by the decoded state marking signal of above-mentioned immediate extended instruction decoder output, one immediate of finally decoding output, the figure place of a logic left displacement and a symbolic number marking signal.
Described instruction fetch circuit is additionally provided with the buffer for above-mentioned immediate extended instruction postpones a location of instruction.
The method of the application of the invention, to process the expression formula described in background technology: R2=R3&0x12345678 equally, and wherein immediate 0x12345678 is 32 unsigned numbers. For MIPS, here execution instruction ANDI $ d, $ s, the #imm16 of MPS can directly be used, its method is: being split as high-order immediate field 1234h and low level immediate field 5678h by 32 without symbol immediate 0x12345678, wherein low level immediate field 5678h is 16.High-order immediate field 1234h inserting the number field immediately of above-mentioned newly-increased immediate extended instruction after unsigned number extends, and low level immediate field 5678h just fills up the number field immediately performing instruction ANDI d, s, #imm16, result is as follows:
HIMM#1234h; (this is newly-increased immediate extended instruction, and it carries high-order immediate field #1234h)
ANDI $ 2, $ 3, #5678h; (perform instruction and carry low 16 immediate field #5678h)
The effect of its execution is equal to: ANDI $ 2, $ 3, #12345678h;
If memory under program can only export 1 instruction on its interface bus every time----i.e. single speed instruction fetch pattern, then process R2=R3&0x12345678 to need altogether to spend 2 cycle times, wherein immediate extended instruction (HIMM#1234h) needs to postpone the time of 1 instruction, to wait marquis execution instruction (ANDI $ 2 following closely, $ 3, arrival #5678h), could simultaneous decoding.
If memory under program can export 2 instructions on its interface bus every time----i.e. double-speed instruction fetch pattern, then process R2=R3&0x12345678 only to need to spend 1 cycle time, now immediate extended instruction (HIMM#1234h) need not any delay just can with execution instruction (ANDI $ 2 following closely, $ 3, #5678h) simultaneous decoding, so it is not spent any time!
From previous example it can be seen that use the method for the present invention can greatly improve the efficiency that program performs, not only save the time but also save space.
Accompanying drawing explanation
Fig. 1 is instruction fetch and the instruction decoding circuit schematic diagram of existing computer system.
Fig. 2 is that the big immediate illustrating the inventive method splits and the schematic diagram merged.
Fig. 3 is the memory under program output interface highway width embodiment circuit diagram equal to the situation of 1 instruction width.
Fig. 4 is the memory under program output interface highway width embodiment circuit diagram equal to the situation of 2 instruction widths.
Detailed description of the invention
The inventive method is mainly by setting up an immediate extended instruction and a corresponding immediate extended instruction decoder in existing RISC computer instruction system, and this immediate extended instruction includes operation code and number field immediately; Immediate extended instruction is a non-executive instruction, and only to decoding this stage just termination, it need not experience the stage of execution, write-back. In instruction compiling procedure, more than the immediate of the length of the number field immediately performing instruction, one units being divided into two fields, one is high-order immediate field, and another is low level immediate field; High-order immediate field is further filled with the number field immediately of above-mentioned newly-increased immediate extended instruction after signed number or unsigned number extend, low level immediate field then inserts the number field immediately of described execution instruction, and requires the length length equal to the number field immediately of described execution instruction of low level immediate field; Additionally above-mentioned newly-increased immediate extended instruction wants preposition in the described execution instruction carrying this low level immediate, and other instruction can not be inserted in centre; Have symbol immediate 0x12345678 to be illustrated a big immediate for example with one 32 in fig. 2 to split and the process merged. When programming, one units is divided into two fields more than the immediate of the length of the number field immediately performing instruction, one is high-order immediate field, another is low level immediate field, the length of low level immediate field is equal to the length of the number field immediately of this execution instruction, and remaining high-order immediate field to be further filled with the number field immediately of above-mentioned newly-increased immediate extended instruction after signed number or unsigned number extend. When decoding, the figure place that the immediate of above-mentioned newly-increased immediate extended instruction decoder output needs logic left to shift is equal to the length of the number field immediately of this execution instruction, that is, if the number field immediately performing instruction is n position, then splitting the low level immediate field obtained is n position, and the figure place that the immediate of above-mentioned newly-increased immediate extended instruction decoder output needs logic left to shift is equal to n position.In actual applications, when required immediate length more than perform instruction number field immediately time just can use above-mentioned newly-increased immediate extended instruction, so above-mentioned improvement perform command decoder decoding time have to the above-mentioned newly-increased immediate extended instruction of check whether there is at above-mentioned newly-increased immediate extended instruction decoder simultaneous decoding, if the command decoder that performs of above-mentioned improvement finds there is above-mentioned newly-increased immediate extended instruction at above-mentioned newly-increased immediate extended instruction decoder simultaneous decoding when decoding, explanation has high-order immediate field, the immediate performing command decoder decoding output of so above-mentioned improvement is unsigned number, the command decoder that performs of above-mentioned improvement does not find there is above-mentioned newly-increased immediate extended instruction at above-mentioned newly-increased immediate extended instruction decoder simultaneous decoding when decoding else if, explanation does not have high-order immediate field, the command decoder that performs of so above-mentioned improvement is have symbol or without symbol immediate by decoding, according to the requirement of operation code, the immediate exported.
In fig. 2, be the number field immediately of 16 and newly-increased immediate extended instruction 4 it it is 26 owing to performing the number field immediately of instruction 5, so there is symbol immediate 1 (0x12345678) to be split as the high-order immediate field 2 (0x1234) of 26 signed numbers and one 16 signless low level immediate fields 3 (0x5678) by 32, the number field immediately (Immediate) that high-order immediate field 2 (0x1234) embeds newly-increased immediate extended instruction 4 obtains immediate extended instruction 6, and low level immediate field 3 (0x5678) embeds the number field immediately (Immediate) performing instruction 5 and obtains performing instruction 7. during instruction fetch, the instruction fetch circuit synchronization ground of above-mentioned improvement is sent newly-increased immediate extended instruction 6 into newly-increased immediate extended instruction depositor (U11) and sends performing instruction 7 into execution command register (U6). the instruction of U11 is decoded by newly-increased immediate extended instruction decoder (U12), decoding obtains 32 symbol immediate 8 (0x1234), and the instruction of U6 is decoded by the execution command decoder (U7a) improved, decoding obtains 32 without symbol immediate 10 (0x5678). immediate 8 through newly-increased logic left shift circuit (U13) carry out obtaining after logic left shifts 16 32 have symbol immediate 9 (0x12340000), newly-increased data consolidation circuit (U14) obtains 32 after immediate 9 and immediate 10 are merged (i.e. logic or computing) symbol immediate 11 (0x12345678). immediate 11 is identical with immediate 1. if it should be understood that the immediate 1 to split is unsigned number, then high-order immediate field to reinstall the number field immediately of newly-increased immediate extended instruction 4 after carrying out unsigned number extension, otherwise, if the immediate 1 to split is signed number, then high-order immediate field to reinstall the number field immediately of newly-increased immediate extended instruction 4 after carrying out signed number extension.
In real world applications, owing to memory under program output interface highway width has the width equal to 1 instruction, also there is the width equal to 2 instructions, or the width even equal to more a plurality of instruction, so the present embodiment is divided into two situations to illustrate: the first application scenarios is the memory under program output interface highway width width equal to 1 instruction; The second application scenarios is the memory under program output interface highway width width equal to 2 instructions. The method being referred to the second application scenarios more than the situation of 2 instruction widths for memory under program output interface highway width improves existing instruction fetch circuit, no longer illustrates at this.
For the first above-mentioned application scenarios, its implementing circuit is as shown in Figure 3.
In figure 3, instruction fetch circuit is to be made up of circuit such as U1, U2, U3, U4, U8, U9, U10, wherein U1, U2, U3, U4 and Fig. 1 effect identical, herein be not repeated describe. U5 is memory under program. U8, U9, U10, U11, U12, U13, U14 are circuit newly-increased on the basis of Fig. 1, wherein U8, U9 are buffers, these 2 buffers are all depositors, its effect is that the instruction allowing and flowing through them can postpone a location of instruction, one of them buffer works in program normal execution mode, and another buffer is then operate on instruction fetch page fault exception execution state. U10 is data selector, system is in normal execution mode according to present procedure and is in instruction fetch page fault exception execution state and controls U10, U10 is made to select corresponding buffer as the buffer of work at present, it not that the buffer of work at present is at halted state, if U8 is in running order, then U10 chooses U8 to input as its data, otherwise, if U9 is in running order, then U10 chooses U9 to input as its data, do so can realize the system when there is instruction fetch page fault and can switch to work in the buffer of instruction fetch page fault exception execution state, thus protection has been brought into working in the above-mentioned newly-increased immediate extended instruction of the buffer of program normal execution mode. U6 is existing execution command register, for storing the instruction of current decoding. U7a is the execution command decoder improved. U11 is newly-increased immediate extended instruction depositor. U12 is newly-increased immediate extended instruction decoder. U13 is newly-increased logic left shift circuit. U14 is newly-increased data consolidation circuit.
In figure 3, the work process of its circuit is:
The first step is the instruction fetch phase: completed after next instruction address calculates PC (U4) to the address value of memory under program (U5) output order by U1, U2, U3, U4, then memory under program (U5) exports 1 instruction on its output bus, this instruction is sent into and is performed command register (U6), simultaneously: if now U8 is in running order, then U10 chooses U8 to input as its data, U8 is sent in instruction on U5 interface bus, and the old instruction of U8 sends into immediate extended instruction depositor (U11) by U10; If now U9 is in running order, then U10 chooses U9 to input as its data, and U9 is sent in instruction on U5 interface bus, and the old instruction of U9 sends into immediate extended instruction depositor (U11) by U10.
Second step is the decoding stage: the instruction that immediate extended instruction depositor (U11) is exported by immediate extended instruction decoder (U12) decodes, and the state of the symbolic number marking signal (SG) exported in conjunction with the execution command decoder (U7a) of improvement, decoding one immediate (#ib) of output and a decoded state marking signal RDY, this decoded state marking signal RDY is defined such that if the instruction of U11 output is above-mentioned newly-increased immediate extended instruction, then this decoded state marking signal RDY is true, the immediate (#ib) of U12 decoding output is effective immediate, if and the instruction of U11 output is not above-mentioned newly-increased immediate extended instruction, then this decoded state marking signal RDY is false, and the immediate of U12 decoding output is 0 value. wherein the symbolic number marking signal (SG) of U7a output is the immediate (#ib) exported for controlling U12 decoding is signed number or unsigned number.The task of above-mentioned newly-increased immediate extended instruction is to just completing here. The instruction that execution command register (U6) is exported by the execution command decoder (U7a) improved decodes, the decoded state marking signal RDY that it exports herein in connection with immediate extended instruction decoder (U12), decoding exports the figure place (LSL) of execution operation signal (OP) of this execution instruction, destination register (Rd), source register (Rs), source register (Rt), immediate (#ia), symbolic number marking signal (SG) and logic left displacement. If the decoded state marking signal RDY that immediate extended instruction decoder (U12) exports is true, then the immediate (#ia) performing command decoder (U7a) decoding output is a unsigned number; The decoded state marking signal RDY that otherwise immediate extended instruction decoder (U12) exports is false, then perform command decoder (U12) and will decode the immediate (#ia) of output according to the normal requirement of executing instruction operations code. If the instruction of U6 output is above-mentioned newly-increased immediate extended instruction, then U7a will according to non-operation instruction (i.e. NOP instruction) decoding output. U7a controls U13 by the figure place (LSL) shifted left to logic left shift circuit (U13) output logic, the immediate (#ib) that U12 is exported by the requirement of the U13 figure place (LSL) shifted according to this logic left is made to carry out logic left displacement, result after displacement is exported immediate (#ic) by U13, then the immediate (#ia) exported by U7a by data consolidation circuit (U14) and U13 export immediate (#ic) and merge (i.e. logic or computing or additive operation), finally obtain immediate (#imm).
For above-mentioned the second application scenarios, its implementing circuit is as shown in Figure 4.
In the diagram, instruction fetch circuit is to be made up of circuit such as U1, U2, U3, U4, U8, U9, U10, U15, U16, U17, U18, U19, wherein U1, U2, U3, U4 and Fig. 1 effect identical, the PC increment that simply order of U1 input performs is changed into variable (APC) by constant (1). U5 is memory under program. U8, U9, U10, U11, U12, U13, U14, U15, U16, U17, U18, U19 are the circuit increased on the basis of Fig. 1, wherein U8, U9 are buffers, these 2 buffers are all depositors, its effect is that the instruction allowing and flowing through them can postpone a location of instruction, one of them buffer works in program normal execution mode, and another buffer is then operate on instruction fetch page fault exception execution state. U10 is data selector, system is in normal execution mode according to present procedure and is in instruction fetch page fault exception execution state and controls U10, U10 is made to select corresponding buffer as the buffer of work at present, it not that the buffer of work at present is at halted state, if U8 is in running order, then U10 chooses U8 to input as its data, otherwise, if U9 is in running order, then U10 chooses U9 to input as its data, do so can realize the system when there is instruction fetch page fault and can switch to work in the buffer of instruction fetch page fault exception execution state, thus protection has been brought into working in the above-mentioned newly-increased immediate extended instruction of the buffer of program normal execution mode. U6 is existing execution command register, for storing the instruction of current decoding. U7a is the execution command decoder improved. U11 is newly-increased immediate extended instruction depositor. U12 is newly-increased immediate extended instruction decoder. U13 is newly-increased logic left shift circuit.U14 is newly-increased data consolidation circuit. U15, U16 are newly-increased data selectors. U17, U18 are newly-increased digital comparators. U19 is newly-increased combinational logic circuit.
In the diagram, the work process of its circuit is:
The first step is the instruction fetch phase: completed after next instruction address calculates PC (U4) to the address value of memory under program (U5) output order by U1, U2, U3, U4, then memory under program (U5) 2 instructions of output simultaneously respectively on its interface bus IBUS0 and IBUS1, wherein bus IBUS0 exports the instruction of even address, and bus IBUS1 exports the instruction of odd address. In order to express easily, at this, instruction of bus IBUS0 output is called Article 1 instruction, and the instruction that bus IBUS1 exports is called Article 2 instruction, from the position of programmed instruction, before Article 1 instruction is in Article 2 instruction. Article 1, port 0 place of U15 is delivered in instruction, Article 1, the operation code of instruction delivers to an input port of digital comparator U18, compares with the operation code of the above-mentioned newly-increased immediate extended instruction of another input of U18, if comparative result is equal, then U18 output terminals A is 1, and otherwise A is 0. Port 1 place of U16 is delivered in Article 2 instruction, the operation code of Article 2 instruction delivers to an input port of digital comparator U17, compares with the operation code of the above-mentioned newly-increased immediate extended instruction of another input of U17, if comparative result is equal, then U17 outfan B is 1, and otherwise B is 0. If now U8 is in running order, then U10 chooses U8 to input as its data, and Article 2 instruction is sent into the old instruction of U8, U8 and sent into port 1 place of data selector U15 by U10; If now U9 is in running order, then U10 chooses U9 to input as its data, and Article 2 instruction is sent into the old instruction of U9, U9 and sent into port 1 place of data selector U15 by U10. Instruction sends into immediate extended instruction depositor (U11) after selecting then through U15. Combinational logic circuit (U19) realizes logical relation as shown in table 2 according to the state of the lowest order PC.2 of the instruction fetch address of output signal B and the program pointer depositor PC output of output signal A, U17 of U18 and result exports port S1, S2, APC. When wherein signal PC.2 is 0, represents that PC points to Article 1 instruction, and when PC.2 is 1, represent that PC points to Article 2 instruction. U19 output port signal S1 controls data selector (U15) and completes instruction to be exported after data select immediate extended instruction depositor (U11), wherein: if S1 is 1, then choosing the U10 old instruction exported is data inputs, and otherwise choosing Article 1 instruction is data inputs. U19 output port signal S2 controls data selector (U16) and completes instruction to be exported after data input selects execution command register (U6), wherein: if S2 is 1, then choosing Article 2 instruction is data inputs, and otherwise choosing Article 1 instruction is data inputs. U19 port signal APC is the numerical value that order performs PC increment: if APC is 1, then PC increment is 1 instruction, if APC is 2, then PC increment is 2 instructions.
Table 2U19 combinational logic circuit truth table
Second step is decoding stage (this stage is identical with the decoding stage of Fig. 3): the instruction that immediate extended instruction depositor (U11) is exported by immediate extended instruction decoder (U12) decodes, and the state of the symbolic number marking signal (SG) exported in conjunction with the execution command decoder (U7a) of improvement, decoding one immediate (#ib) of output and a Status Flag signal RDY, this Status Flag signal RDY is defined such that if the instruction of U11 output is above-mentioned newly-increased immediate extended instruction, then this Status Flag signal RDY is true, the immediate (#ib) of U12 decoding output is effective immediate,And if the instruction of U11 output is not above-mentioned newly-increased immediate extended instruction, then this Status Flag signal RDY is false, and the immediate of U12 decoding output is 0 value. Wherein the symbolic number marking signal (SG) of U7a output is the immediate (#ib) exported for selecting U12 to decode is signed number or unsigned number. The task of above-mentioned newly-increased immediate extended instruction is to just completing here. The instruction that execution command register (U6) is exported by the execution command decoder (U7a) improved decodes, the Status Flag signal RDY that it exports herein in connection with immediate extended instruction decoder (U12), decoding exports the figure place (LSL) of execution operation signal (OP) of this execution instruction, destination register (Rd), source register (Rs), source register (Rt), immediate (#ia), symbolic number marking signal (SG) and logic left displacement. If the decoded state marking signal RDY that immediate extended instruction decoder (U12) exports is true, then the immediate (#ia) performing command decoder (U7a) decoding output is a unsigned number; The decoded state marking signal RDY that otherwise immediate extended instruction decoder (U12) exports is false, then perform command decoder (U12) and will decode the immediate (#ia) of output according to the normal requirement of executing instruction operations code. If the instruction of U6 output is above-mentioned newly-increased immediate extended instruction, then U7a will according to non-operation instruction (i.e. NOP instruction) decoding output. U7a controls U13 by the figure place (LSL) shifted left to logic left shift circuit (U13) output logic, the immediate (#ib) that U12 is exported by the requirement of the U13 figure place (LSL) shifted according to this logic left is made to carry out logic left displacement, result after displacement is exported immediate (#ic) by U13, then the immediate (#ia) exported by U7a by data consolidation circuit (U14) and U13 export immediate (#ic) and merge (i.e. logic or computing or additive operation), finally obtain immediate (#imm).
Embodiments of the present invention are not limited to this; foregoing according to the present invention; utilize ordinary technical knowledge and the customary means of this area; without departing under the above-mentioned basic fundamental thought premise of the present invention; the present invention can also make the amendment of other various ways, replacement or change, all falls within rights protection scope of the present invention.
Claims (7)
1., by a method for immediate extension in computer instruction, it is characterized in that:
At least setting up an immediate extended instruction and a corresponding immediate extended instruction decoder in existing RISC computer instruction system, this immediate extended instruction includes operation code and number field immediately; Detailed process is as follows:
In instruction programming process, more than the immediate of the length of the number field immediately performing instruction, one units being split into two fields, one is high-order immediate field, and another is low level immediate field; Described high-order immediate field is further filled with the number field immediately of above-mentioned newly-increased immediate extended instruction after signed number or unsigned number extend, described low level immediate field then inserts the number field immediately of described execution instruction, and requires that the length of described low level immediate field is necessarily equal to the length of the number field immediately of described execution instruction; Additionally above-mentioned newly-increased immediate extended instruction wants preposition in the described execution instruction carrying this low level immediate field, and other instruction can not be inserted in centre;
In instruction fetch process, above-mentioned newly-increased immediate extended instruction is sent into immediate extended instruction depositor and the execution instruction followed closely after this immediate extended instruction is sent into execution command register by instruction fetch circuit synchronization;
In Instruction decoding process, while the instruction that immediate extended instruction depositor exports is decoded by immediate extended instruction decoder, perform command decoder also the instruction performing command register output to be decoded, the immediate of immediate extended instruction decoder output merges with the immediate performing command decoder output after logic left shifts again, and amalgamation result obtains the units immediate more than the length of the number field immediately performing instruction; The numerical value of this immediate is equal with the numerical value of the immediate being split in above-mentioned instruction compiling procedure.
2. method according to claim 1, is characterized in that: described immediate extended instruction is a non-executive instruction, and only to decoding this stage just termination, it need not experience the stage of execution, write-back.
3. method according to claim 1, it is characterized in that: by arranging a buffer in instruction fetch circuit, described newly-increased immediate extended instruction is postponed a location of instruction, to wait the arrival performing instruction following closely so that above-mentioned newly-increased immediate extended instruction and execution instruction following closely can be synchronized to be respectively fed to respective decoder and decode by instruction fetch circuit; Described buffer is depositor.
4. method according to claim 1, it is characterized in that: described immediate extended instruction decoder is controlled by the symbolic number marking signal that execution command decoder is sent here when decoding, finally decoding one immediate of output and a decoded state marking signal, and perform following process: if the instruction of above-mentioned newly-increased immediate extended instruction depositor output is above-mentioned newly-increased immediate extended instruction, then it is true for arranging this decoded state marking signal; Otherwise, if the instruction of above-mentioned newly-increased immediate extended instruction depositor output is not above-mentioned newly-increased immediate extended instruction, then arranging this decoded state marking signal is false and to arrange the immediate of this immediate extended instruction decoder output be 0 value; It is described that to perform the symbolic number marking signal that command decoder sends here be signed number or unsigned number for selecting the immediate that this immediate extended instruction decoder for decoding exports.
5. method according to claim 4, it is characterized in that: described execution command decoder decodes the figure place and a symbolic number marking signal that export a logic left displacement in decoding process according to the current operation code performing instruction decoded, the figure place of described logic left displacement is equal to the length of its number field immediately performing instruction currently decoded, and the immediate represented by executing instruction operations code that described symbolic number marking signal is exactly current decoding is signed number or unsigned number; Additionally being controlled by the decoded state marking signal of above-mentioned immediate extended instruction decoder output, its controlled process is: if this decoded state marking signal is true, then the immediate performing command decoder decoding output is a unsigned number; This decoded state marking signal is false else if, then performing command decoder has symbol or without symbol immediate by decoding output one according to the requirement of operation code.
6. realize a device for method described in claim 1, including instruction fetch circuit, perform command register, execution command decoder, described execution command decoder, it, for the instruction performing command register output is decoded, is characterized in that also including:
One immediate extended instruction depositor, for storing the instruction sent here by instruction fetch circuit;
One immediate extended instruction decoder, for the instruction of above-mentioned immediate extended instruction depositor output is decoded, additionally it is also controlled by the symbolic number marking signal performing command decoder output of above-mentioned improvement, finally decoding one immediate of output and a decoded state marking signal;
One logic left shift circuit, for receiving the figure place from the logic left displacement performing command decoder output, and can complete the immediate of above-mentioned immediate extended instruction decoder output is carried out logic left displacement according to the requirement of the figure place that this logic left shifts, result one immediate of output;
One data consolidation circuit, the immediate performing command decoder output for the immediate exported by above-mentioned logic left shift circuit and improvement carries out logic or computing or additive operation, operation result one immediate of output;
Described execution command decoder is also controlled by the decoded state marking signal of above-mentioned immediate extended instruction decoder output, one immediate of finally decoding output, the figure place of a logic left displacement and a symbolic number marking signal.
7. device according to claim 6, it is characterised in that be additionally provided with the buffer for immediate extended instruction being postponed a location of instruction in described instruction fetch circuit.
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