CN105634725B - A kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable - Google Patents
A kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable Download PDFInfo
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- CN105634725B CN105634725B CN201610118818.2A CN201610118818A CN105634725B CN 105634725 B CN105634725 B CN 105634725B CN 201610118818 A CN201610118818 A CN 201610118818A CN 105634725 B CN105634725 B CN 105634725B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
Abstract
The present invention provides a kind of Lorenz type hyperchaotic system construction methods and circuit convenient for ultimate boundary estimation of different variables,Utilize operational amplifier U1,Operational amplifier U2 and resistance,Capacitance realizes addition and integral operation,Reverse phase operation is realized using operational amplifier U3 and resistance,Multiplying in multiplier U4 and multiplier U5 realization systems,The operational amplifier U1 connection operational amplifiers U2,Operational amplifier U3 and multiplier U5,The operational amplifier U2 connection operational amplifier U3 and multiplier U4,The operational amplifier U1,U2 and U3 uses LF347BN,The multiplier U4 and U5 uses AD633JN,The present invention is on the basis of Lorenz type chaos systems,Design a kind of different variable convenient for ultimate boundary estimation Lorenz type hyperchaotic system construction methods and circuit construction method and design an analog circuit and carry out realizing this chaos system,New hyperchaotic system signal source is provided for the synchronization and control of chaos.
Description
Technical field
The present invention relates to a kind of chaos system and circuit, more particularly to a kind of different variables are conducive to what ultimate boundary was estimated
Lorenz type hyperchaotic system construction methods and circuit.
Background technology
The boundary estimation of hyperchaotic system in the control of chaos, the engineer applications such as synchronize in terms of have great importance, when
Before, the method for four dimension ultra-chaos of construction mainly on the basis of three-dimensional chaotic system, increases by four dimension ultra-chaos systems of one-dimensional composition
System, but the hyperchaotic system constituted is not easy to carry out ultimate boundary estimation, can carry out the hyperchaos system of ultimate boundary estimation
System has the characteristic that：The all negative values of characteristic element of Jacobian matrix leading diagonal, the hyperchaotic system that the present invention constructs
Have the characteristics that all negative values of the characteristic element of Jacobian matrix leading diagonal, ultimate boundary estimation can be carried out, this for
The control of hyperchaos synchronizes etc. and to have important job applications foreground.
Invention content
The technical problem to be solved in the present invention is to provide a kind of Lorenz types for being conducive to ultimate boundary estimation of different variables
Hyperchaotic system construction method and circuit：
1. a kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable, feature exist
In including the following steps：
(1) Lorenz types chaos system i is：
X in formula, y, z are state variable, and a, b, c, d are systematic parameter；
(2) the variable w that structure one is reformed1：
dw1/ dt=-kx-rw1W in k=5, r=0.1 ii formulas1For state variable, k, r are systematic parameter；
(3) the variable w that structure one is reformed2：
dw2/ dt=-ky-rw2W in k=5, r=0.1 iii formulas2For state variable, k, r are systematic parameter；
(4) it constructs a switching function iv and ii and iii is formed into one-dimensional switching variable w：
W is state variable in dw/dt=kf (x)-rw k=5, r=0.1 v formulas, and f (x) is switching function, and k, r are systematic parameter；
(5) it using variable w as unidimensional system variable, is added in the second equation of Lorenz type chaos systems i, obtains a kind of
Conducive to ultimate boundary estimation Lorenz type hyperchaotic systems vi be：
X in formula, y, z, w are state variable, and f (x) is switching function, parameter value a=12, b=23, c=1, d=2.1, k
=5, r=0.1；
(6) circuit based on system vi constructions, is realized using operational amplifier U1, operational amplifier U2 and resistance, capacitance
Addition and integral operation realize that system is realized in reverse phase operation, multiplier U4 and multiplier U5 using operational amplifier U3 and resistance
In multiplying, operational amplifier U6 and selector U7 realize switching function operation, described operational amplifier U1, U2, U3 and
U6 uses LF347BN, the multiplier U4 and U5 that AD633JN, the selector U7 is used to use ADG409；
The operational amplifier U1 connection operational amplifiers U3, operational amplifier U6 and multiplier U5, the operation amplifier
Device U2 connection multipliers U4, operational amplifier U1 and operational amplifier U3, the operational amplifier U3 connection operational amplifiers U1,
Operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, the multiplier U4 connections operational amplifier U1, institute
State multiplier U5 connection operational amplifiers U2；The operational amplifier U6 connection selectors U7, the selector U7 connections operation
Amplifier U2；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, and operation is put
The 2nd pin of big device U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, the 3rd pin of operational amplifier U1, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 connect VCC, the 11st pin of operational amplifier U1
VEE is met, the 6th pin of operational amplifier U1 is connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1
The 7th pin connected with the 13rd pin of operational amplifier U1 by resistance Rx2, the 7th pin and multiplication of operational amplifier U1
The 1st pin of device U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3,
The 8th pin that the 7th pin of operational amplifier U1 meets output y, operational amplifier U1 passes through capacitance Cx's and operational amplifier U1
9th pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, operation
The 8th pin of amplifier U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1
Connect with the 3rd pin of multiplier U5, the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operation
The 8th pin of amplifier U1 connects the 13rd pin of output x, operational amplifier U1 by the 14th of resistance Rx and operational amplifier U1
Pin connects, and the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, and operation is put
The 2nd pin of big device U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, the 3rd pin of operational amplifier U2, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pin of operational amplifier U2
Connected with the 7th pin of operational amplifier U2 by capacitance Cw, the 7th pin of operational amplifier U2 passes through resistance Ry4 and operation
The 2nd pin of amplifier U1 connects, and the 7th pin of operational amplifier U2 is drawn by resistance R11 and the 13rd of operational amplifier U3
Foot connects, and the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operation amplifier
The 9th pin of device U2 connects, and the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, operational amplifier U2's
8th pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 connects output z, fortune
The 13rd pin for calculating amplifier U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, and the 14th of operational amplifier U2 the
Pin is connected by resistance R3 with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, operation
The 1st pin of amplifier U3 connects with the 4th pin of selector U7, the 1st pin of operational amplifier U3 and the 1st of multiplier U4 the
Pin connects, and the 2nd pin of operational amplifier U3 is connected by resistance R6 with the 1st pin of operational amplifier U3, operation amplifier
The 3rd pin of device U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and operation is put
The 6th pin of big device U3 is connected by resistance R8 with the 7th pin of operational amplifier U3, and the 7th pin of operational amplifier U3 is logical
It crosses resistance Ry2 with the 2nd pin of operational amplifier U1 to connect, the 5th pin of the 7th pin and selector U7 of operational amplifier U3
Connect, the 8th pin of operational amplifier U3 is connected by resistance R10 with the 9th pin of operational amplifier U3, operational amplifier U3
The 8th pin connected with the 13rd pin of operational amplifier U2 by resistance Rz2, the 13rd pin of operational amplifier U3 passes through electricity
Resistance R12 connects with the 14th pin of operational amplifier U3, and the 14th pin of operational amplifier U3 passes through resistance Rw2 and operation amplifier
The 2nd pin of device U2 connects；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operation amplifier
The 1st pin of device U6 is connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th
Pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th
Pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are hanging.
The 2nd pin and the 14th pin of the selector U7 meets VCC, and the 3rd pin of selector U7 meets VEE, selector U7
The 15th pin and the 16th pin ground connection, the 2nd pin that the 8th pin of selector U7 passes through resistance Rw1 and operational amplifier U2
Connect, the 6th pin, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin of selector U7 is outstanding
It is empty.
2. a kind of Lorenz type hyperchaotic system circuits for being conducive to ultimate boundary estimation of difference variable, which is characterized in that
Realize addition and integral operation using operational amplifier U1, operational amplifier U2 and resistance, capacitance, using operational amplifier U3 and
Resistance realizes reverse phase operation, the multiplying in multiplier U4 and multiplier U5 realization systems, operational amplifier U6 and selector
U7 realizes switching function operation, operational amplifier U1 connection operational amplifier U3 and U6, operational amplifier U1 connection multipliers U4
It is used using LF347BN, the multiplier U4 and U5 with U5 and selector U7, described operational amplifier U1, U2, U3 and U6
AD633JN, the selector U7 use ADG409；
The operational amplifier U1 connection operational amplifiers U3, operational amplifier U6 and multiplier U5, the operation amplifier
Device U2 connection multipliers U4, operational amplifier U1 and operational amplifier U3, the operational amplifier U3 connection operational amplifiers U1,
Operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, the multiplier U4 connections operational amplifier U1, institute
State multiplier U5 connection operational amplifiers U2；The operational amplifier U6 connection selectors U7, the selector U7 connections operation
Amplifier U2；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, and operation is put
The 2nd pin of big device U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, the 3rd pin of operational amplifier U1, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 connect VCC, the 11st pin of operational amplifier U1
VEE is met, the 6th pin of operational amplifier U1 is connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1
The 7th pin connected with the 13rd pin of operational amplifier U1 by resistance Rx2, the 7th pin and multiplication of operational amplifier U1
The 1st pin of device U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3,
The 8th pin that the 7th pin of operational amplifier U1 meets output y, operational amplifier U1 passes through capacitance Cx's and operational amplifier U1
9th pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, operation
The 8th pin of amplifier U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1
Connect with the 3rd pin of multiplier U5, the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operation
The 8th pin of amplifier U1 connects the 13rd pin of output x, operational amplifier U1 by the 14th of resistance Rx and operational amplifier U1
Pin connects, and the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, and operation is put
The 2nd pin of big device U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, the 3rd pin of operational amplifier U2, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pin of operational amplifier U2
Connected with the 7th pin of operational amplifier U2 by capacitance Cw, the 7th pin of operational amplifier U2 passes through resistance Ry4 and operation
The 2nd pin of amplifier U1 connects, and the 7th pin of operational amplifier U2 is drawn by resistance R11 and the 13rd of operational amplifier U3
Foot connects, and the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operation amplifier
The 9th pin of device U2 connects, and the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, operational amplifier U2's
8th pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 connects output z, fortune
The 13rd pin for calculating amplifier U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, and the 14th of operational amplifier U2 the
Pin is connected by resistance R3 with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, operation
The 1st pin of amplifier U3 connects with the 4th pin of selector U7, the 1st pin of operational amplifier U3 and the 1st of multiplier U4 the
Pin connects, and the 2nd pin of operational amplifier U3 is connected by resistance R6 with the 1st pin of operational amplifier U3, operation amplifier
The 3rd pin of device U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and operation is put
The 6th pin of big device U3 is connected by resistance R8 with the 7th pin of operational amplifier U3, and the 7th pin of operational amplifier U3 is logical
It crosses resistance Ry2 with the 2nd pin of operational amplifier U1 to connect, the 5th pin of the 7th pin and selector U7 of operational amplifier U3
Connect, the 8th pin of operational amplifier U3 is connected by resistance R10 with the 9th pin of operational amplifier U3, operational amplifier U3
The 8th pin connected with the 13rd pin of operational amplifier U2 by resistance Rz2, the 13rd pin of operational amplifier U3 passes through electricity
Resistance R12 connects with the 14th pin of operational amplifier U3, and the 14th pin of operational amplifier U3 passes through resistance Rw2 and operation amplifier
The 2nd pin of device U2 connects；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operation amplifier
The 1st pin of device U6 is connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th
Pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th
Pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are hanging.
The 2nd pin and the 14th pin of the selector U7 meets VCC, and the 3rd pin of selector U7 meets VEE, selector U7
The 15th pin and the 16th pin ground connection, the 2nd pin that the 8th pin of selector U7 passes through resistance Rw1 and operational amplifier U2
Connect, the 6th pin, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin of selector U7 is outstanding
It is empty.
Advantageous effect：The present invention devises a kind of being conducive to eventually for different variables on the basis of Lorenz type chaos systems
One analog circuit of Lorenz type hyperchaotic system construction methods and design of pole boundary estimation carries out realizing this chaos system,
New hyperchaotic system signal source is provided for the synchronization and control of chaos.
Description of the drawings
Fig. 1 is the schematic diagram of circuit connection structure of the preferred embodiment of the present invention.
Fig. 2 is the practical connection figure of circuit of multiplier U4 and operational amplifier U1.
Fig. 3 is the practical connection figure of circuit of operational amplifier U3.
Fig. 4 is the practical connection figure of circuit of multiplier U5 and operational amplifier U2.
Fig. 5 is the practical connection figure of circuit of selector U7 and operational amplifier U6.
Specific implementation mode
The present invention is further described in detail with preferred embodiment below in conjunction with the accompanying drawings, referring to Fig. 1-Fig. 5.
1. a kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable, feature exist
In including the following steps：
(1) Lorenz types chaos system i is：
X in formula, y, z are state variable, and a, b, c, d are systematic parameter；
(2) the variable w that structure one is reformed1：
dw1/ dt=-kx-rw1W in k=5, r=0.1 ii formulas1For state variable, k, r are systematic parameter；
(3) the variable w that structure one is reformed2：
dw2/ dt=-ky-rw2W in k=5, r=0.1 iii formulas2For state variable, k, r are systematic parameter；
(4) it constructs a switching function iv and ii and iii is formed into one-dimensional switching variable w：
W is state variable in dw/dt=kf (x)-rw k=5, r=0.1 v formulas, and f (x) is switching function, and k, r are systematic parameter；
(5) it using variable w as unidimensional system variable, is added in the second equation of Lorenz type chaos systems i, obtains a kind of
Conducive to ultimate boundary estimation Lorenz type hyperchaotic systems vi be：
X in formula, y, z, w are state variable, and f (x) is switching function, parameter value a=12, b=23, c=1, d=2.1, k
=5, r=0.1；
(6) circuit based on system vi constructions, is realized using operational amplifier U1, operational amplifier U2 and resistance, capacitance
Addition and integral operation realize that system is realized in reverse phase operation, multiplier U4 and multiplier U5 using operational amplifier U3 and resistance
In multiplying, operational amplifier U6 and selector U7 realize switching function operation, described operational amplifier U1, U2, U3 and
U6 uses LF347BN, the multiplier U4 and U5 that AD633JN, the selector U7 is used to use ADG409；
The operational amplifier U1 connection operational amplifiers U3, operational amplifier U6 and multiplier U5, the operation amplifier
Device U2 connection multipliers U4, operational amplifier U1 and operational amplifier U3, the operational amplifier U3 connection operational amplifiers U1,
Operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, the multiplier U4 connections operational amplifier U1, institute
State multiplier U5 connection operational amplifiers U2；The operational amplifier U6 connection selectors U7, the selector U7 connections operation
Amplifier U2；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, and operation is put
The 2nd pin of big device U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, the 3rd pin of operational amplifier U1, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 connect VCC, the 11st pin of operational amplifier U1
VEE is met, the 6th pin of operational amplifier U1 is connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1
The 7th pin connected with the 13rd pin of operational amplifier U1 by resistance Rx2, the 7th pin and multiplication of operational amplifier U1
The 1st pin of device U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3,
The 8th pin that the 7th pin of operational amplifier U1 meets output y, operational amplifier U1 passes through capacitance Cx's and operational amplifier U1
9th pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, operation
The 8th pin of amplifier U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1
Connect with the 3rd pin of multiplier U5, the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operation
The 8th pin of amplifier U1 connects the 13rd pin of output x, operational amplifier U1 by the 14th of resistance Rx and operational amplifier U1
Pin connects, and the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, and operation is put
The 2nd pin of big device U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, the 3rd pin of operational amplifier U2, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pin of operational amplifier U2
Connected with the 7th pin of operational amplifier U2 by capacitance Cw, the 7th pin of operational amplifier U2 passes through resistance Ry4 and operation
The 2nd pin of amplifier U1 connects, and the 7th pin of operational amplifier U2 is drawn by resistance R11 and the 13rd of operational amplifier U3
Foot connects, and the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operation amplifier
The 9th pin of device U2 connects, and the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, operational amplifier U2's
8th pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 connects output z, fortune
The 13rd pin for calculating amplifier U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, and the 14th of operational amplifier U2 the
Pin is connected by resistance R3 with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, operation
The 1st pin of amplifier U3 connects with the 4th pin of selector U7, the 1st pin of operational amplifier U3 and the 1st of multiplier U4 the
Pin connects, and the 2nd pin of operational amplifier U3 is connected by resistance R6 with the 1st pin of operational amplifier U3, operation amplifier
The 3rd pin of device U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and operation is put
The 6th pin of big device U3 is connected by resistance R8 with the 7th pin of operational amplifier U3, and the 7th pin of operational amplifier U3 is logical
It crosses resistance Ry2 with the 2nd pin of operational amplifier U1 to connect, the 5th pin of the 7th pin and selector U7 of operational amplifier U3
Connect, the 8th pin of operational amplifier U3 is connected by resistance R10 with the 9th pin of operational amplifier U3, operational amplifier U3
The 8th pin connected with the 13rd pin of operational amplifier U2 by resistance Rz2, the 13rd pin of operational amplifier U3 passes through electricity
Resistance R12 connects with the 14th pin of operational amplifier U3, and the 14th pin of operational amplifier U3 passes through resistance Rw2 and operation amplifier
The 2nd pin of device U2 connects；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operation amplifier
The 1st pin of device U6 is connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th
Pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th
Pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are hanging.
The 2nd pin and the 14th pin of the selector U7 meets VCC, and the 3rd pin of selector U7 meets VEE, selector U7
The 15th pin and the 16th pin ground connection, the 2nd pin that the 8th pin of selector U7 passes through resistance Rw1 and operational amplifier U2
Connect, the 6th pin, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin of selector U7 is outstanding
It is empty.
2. a kind of Lorenz type hyperchaotic system circuits for being conducive to ultimate boundary estimation of difference variable, which is characterized in that
Realize addition and integral operation using operational amplifier U1, operational amplifier U2 and resistance, capacitance, using operational amplifier U3 and
Resistance realizes reverse phase operation, the multiplying in multiplier U4 and multiplier U5 realization systems, operational amplifier U6 and selector
U7 realizes switching function operation, operational amplifier U1 connection operational amplifier U3 and U6, operational amplifier U1 connection multipliers U4
It is used using LF347BN, the multiplier U4 and U5 with U5 and selector U7, described operational amplifier U1, U2, U3 and U6
AD633JN, the selector U7 use ADG409；
The operational amplifier U1 connection operational amplifiers U3, operational amplifier U6 and multiplier U5, the operation amplifier
Device U2 connection multipliers U4, operational amplifier U1 and operational amplifier U3, the operational amplifier U3 connection operational amplifiers U1,
Operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, the multiplier U4 connections operational amplifier U1, institute
State multiplier U5 connection operational amplifiers U2；The operational amplifier U6 connection selectors U7, the selector U7 connections operation
Amplifier U2；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, and operation is put
The 2nd pin of big device U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, the 3rd pin of operational amplifier U1, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 connect VCC, the 11st pin of operational amplifier U1
VEE is met, the 6th pin of operational amplifier U1 is connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1
The 7th pin connected with the 13rd pin of operational amplifier U1 by resistance Rx2, the 7th pin and multiplication of operational amplifier U1
The 1st pin of device U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3,
The 8th pin that the 7th pin of operational amplifier U1 meets output y, operational amplifier U1 passes through capacitance Cx's and operational amplifier U1
9th pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, operation
The 8th pin of amplifier U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1
Connect with the 3rd pin of multiplier U5, the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operation
The 8th pin of amplifier U1 connects the 13rd pin of output x, operational amplifier U1 by the 14th of resistance Rx and operational amplifier U1
Pin connects, and the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, and operation is put
The 2nd pin of big device U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, the 3rd pin of operational amplifier U2, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pin of operational amplifier U2
Connected with the 7th pin of operational amplifier U2 by capacitance Cw, the 7th pin of operational amplifier U2 passes through resistance Ry4 and operation
The 2nd pin of amplifier U1 connects, and the 7th pin of operational amplifier U2 is drawn by resistance R11 and the 13rd of operational amplifier U3
Foot connects, and the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operation amplifier
The 9th pin of device U2 connects, and the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, operational amplifier U2's
8th pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 connects output z, fortune
The 13rd pin for calculating amplifier U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, and the 14th of operational amplifier U2 the
Pin is connected by resistance R3 with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, operation
The 1st pin of amplifier U3 connects with the 4th pin of selector U7, the 1st pin of operational amplifier U3 and the 1st of multiplier U4 the
Pin connects, and the 2nd pin of operational amplifier U3 is connected by resistance R6 with the 1st pin of operational amplifier U3, operation amplifier
The 3rd pin of device U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and operation is put
The 6th pin of big device U3 is connected by resistance R8 with the 7th pin of operational amplifier U3, and the 7th pin of operational amplifier U3 is logical
It crosses resistance Ry2 with the 2nd pin of operational amplifier U1 to connect, the 5th pin of the 7th pin and selector U7 of operational amplifier U3
Connect, the 8th pin of operational amplifier U3 is connected by resistance R10 with the 9th pin of operational amplifier U3, operational amplifier U3
The 8th pin connected with the 13rd pin of operational amplifier U2 by resistance Rz2, the 13rd pin of operational amplifier U3 passes through electricity
Resistance R12 connects with the 14th pin of operational amplifier U3, and the 14th pin of operational amplifier U3 passes through resistance Rw2 and operation amplifier
The 2nd pin of device U2 connects；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operation amplifier
The 1st pin of device U6 is connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th
Pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th
Pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are hanging.
The 2nd pin and the 14th pin of the selector U7 meets VCC, and the 3rd pin of selector U7 meets VEE, selector U7
The 15th pin and the 16th pin ground connection, the 2nd pin that the 8th pin of selector U7 passes through resistance Rw1 and operational amplifier U2
Connect, the 6th pin, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin of selector U7 is outstanding
It is empty.
Certainly, above description is not limitation to invention, and the present invention is also not limited to the example above, the art it is general
The variations, modifications, additions or substitutions that logical technical staff is made in the essential scope of the present invention, also belong to the protection of the present invention
Range.
Claims (1)
1. a kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable, which is characterized in that
Include the following steps：
(1) Lorenz types chaos system i is：
X in formula, y, z are state variable, and a, b, c, d are systematic parameter；
(2) the variable w that structure one is reformed1：
dw1/ dt=-kx-rw1K=5, r=0.1 ii
W in formula1For state variable, k, r are systematic parameter；
(3) the variable w that structure one is reformed2：
dw2/ dt=-ky-rw2K=5, r=0.1 iii
W in formula2For state variable, k, r are systematic parameter；
(4) it constructs a switching function iv and ii and iii is formed into one-dimensional switching variable w：
Dw/dt=kf (x)-rw k=5, r=0.1 v
W is state variable in formula, and f (x) is switching function, and k, r are systematic parameter；
(5) it using variable w as unidimensional system variable, is added in the second equation of Lorenz type chaos systems i, obtains one kind and be conducive to
Ultimate boundary estimation Lorenz type hyperchaotic systems vi be：
X in formula, y, z, w are state variable, and f (x) is switching function, parameter value a=12, b=23, c=1, d=2.1, k=5, r
=0.1；
(6) circuit based on system vi constructions realizes addition using operational amplifier U1, operational amplifier U2 and resistance, capacitance
And integral operation, reverse phase operation is realized using operational amplifier U3 and resistance, in multiplier U4 and multiplier U5 realization systems
Multiplying, operational amplifier U6 and selector U7 realize switching function operation, and described operational amplifier U1, U2, U3 and U6 are adopted
AD633JN, the selector U7 is used to use ADG409 with LF347BN, the multiplier U4 and U5；
The operational amplifier U1 connection operational amplifiers U3, operational amplifier U6 and multiplier U5, the operational amplifier U2
Connect multiplier U4, operational amplifier U1 and operational amplifier U3, the operational amplifier U3 connection operational amplifiers U1, operation
Amplifier U2, operational amplifier U6, selector U7 and multiplier U4, the multiplier U4 connection operational amplifiers U1, it is described to multiply
Musical instruments used in a Buddhist or Taoist mass U5 connection operational amplifiers U2；The operational amplifier U6 connection selectors U7, the selector U7 connections operation amplifier
Device U2；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, operational amplifier
The 2nd pin of U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, and the 3rd pin of operational amplifier U1, the 5th are drawn
Foot, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meet VCC, and the 11st pin of operational amplifier U1 connects
The 6th pin of VEE, operational amplifier U1 are connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1's
7th pin is connected by resistance Rx2 with the 13rd pin of operational amplifier U1, the 7th pin and multiplier of operational amplifier U1
The 1st pin of U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3, fortune
The 7th pin for calculating amplifier U1 connects the 8th pin of output y, operational amplifier U1 by the 9th of capacitance Cx and operational amplifier U1
Pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, operation amplifier
The 8th pin of device U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1 with multiply
The 3rd pin of musical instruments used in a Buddhist or Taoist mass U5 connects, and the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operation amplifier
The 8th pin of device U1 connects the 14th pin that the 13rd pin of output x, operational amplifier U1 pass through resistance Rx and operational amplifier U1
Connect, the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, operational amplifier
The 2nd pin of U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, and the 3rd pin of operational amplifier U2, the 5th are drawn
Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and the 6th pin of operational amplifier U2 passes through
Capacitance Cw connects with the 7th pin of operational amplifier U2, and the 7th pin of operational amplifier U2 passes through resistance Ry4 and operation amplifier
The 2nd pin of device U1 connects, the 13rd pin phase that the 7th pin of operational amplifier U2 passes through resistance R11 and operational amplifier U3
It connects, the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operational amplifier U2
The 9th pin connect, the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, the 8th of operational amplifier U2 the
Pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 meets output z, and operation is put
The 13rd pin of big device U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, the 14th pin of operational amplifier U2
Connected with the 9th pin of operational amplifier U2 by resistance R3；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, operation amplifier
The 1st pin of device U3 connects with the 4th pin of selector U7, the 1st pin of the 1st pin and multiplier U4 of operational amplifier U3
Connect, the 2nd pin of operational amplifier U3 is connected by resistance R6 with the 1st pin of operational amplifier U3, operational amplifier U3
The 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier
The 6th pin of U3 is connected by resistance R8 with the 7th pin of operational amplifier U3, and the 7th pin of operational amplifier U3 passes through electricity
Resistance Ry2 connects with the 2nd pin of operational amplifier U1, the 5th pin phase of the 7th pin and selector U7 of operational amplifier U3
It connects, the 8th pin of operational amplifier U3 is connected by resistance R10 with the 9th pin of operational amplifier U3, operational amplifier U3's
8th pin is connected by resistance Rz2 with the 13rd pin of operational amplifier U2, and the 13rd pin of operational amplifier U3 passes through resistance
R12 connects with the 14th pin of operational amplifier U3, and the 14th pin of operational amplifier U3 passes through resistance Rw2 and operational amplifier
The 2nd pin of U2 connects；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through resistance
Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through resistance
Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operational amplifier U6
The 1st pin connected with ground by resistance R13 and resistance R14, the 3rd pin of operational amplifier U6, the 5th pin, the 10th pin,
12nd pin is grounded, and the 4th pin meets VCC, and the 11st pin meets VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th pin,
9th pin, the 12nd pin, the 13rd pin, the 14th pin are hanging；
The 2nd pin and the 14th pin of the selector U7 meets VCC, and the 3rd pin of selector U7 meets VEE, and the of selector U7
15 pins and the 16th pin ground connection, the 8th pin of selector U7 are connected by resistance Rw1 with the 2nd pin of operational amplifier U2,
The 6th pin, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin of selector U7 is hanging.
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| CN201610118818.2A CN105634725B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable |
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| CN201610118818.2A CN105634725B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable |
| CN201510279463.0A CN104883253B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation of different variablees |
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| CN201510279463.0A Division CN104883253B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation of different variablees |
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| CN201510279463.0A Expired - Fee Related CN104883253B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation of different variablees |
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| CN104883252B (en) * | 2015-05-27 | 2016-11-16 | 青岛玉兰祥商务服务有限公司 | What a kind of variable was different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated |
| CN105119710A (en) * | 2015-09-09 | 2015-12-02 | 王春梅 | Lorenz type hyper-chaotic system adaptive synchronization method and circuit beneficial to ultimate edge estimation |
| CN105141411A (en) * | 2015-09-09 | 2015-12-09 | 王春梅 | Self-adaptive synchronization method of Lorenz type hyperchaotic system having different variables and circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101373563A (en) * | 2008-08-01 | 2009-02-25 | 张新国 | Lorentz chaos circuit |
| CN102332976A (en) * | 2011-09-15 | 2012-01-25 | 江西理工大学 | Different-dimensional switchable chaotic system design method and circuit |
| CN104202146A (en) * | 2014-09-09 | 2014-12-10 | 王忠林 | Yang-Chen system based automatic switching hyper-chaos system construction method and analog circuit |
| CN104378197A (en) * | 2014-12-03 | 2015-02-25 | 王忠林 | Construction method and circuit of memristor-based x-square-contained Lorenz type hyper-chaotic system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7020286B2 (en) * | 2001-02-15 | 2006-03-28 | Massachusetts Institute Of Technology | Modulation of dynamical systems for communication |
| KR100353082B1 (en) * | 2001-02-27 | 2002-09-18 | 한국과학기술원 | Random Hyperchaos signal generating circuit using HVSM model |
| CN104486061A (en) * | 2014-12-03 | 2015-04-01 | 李敏 | Construction method and circuit of classic Lorenz hyper-chaos system based on memristor |
| CN104468082B (en) * | 2014-12-03 | 2016-10-05 | 国家电网公司 | The construction method of the Lorenz type hyperchaotic system containing y side based on memristor |
-
2015
- 2015-05-27 CN CN201610118818.2A patent/CN105634725B/en active Active
- 2015-05-27 CN CN201510279463.0A patent/CN104883253B/en not_active Expired - Fee Related
- 2015-08-07 WO PCT/CN2015/000571 patent/WO2016187738A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101373563A (en) * | 2008-08-01 | 2009-02-25 | 张新国 | Lorentz chaos circuit |
| CN102332976A (en) * | 2011-09-15 | 2012-01-25 | 江西理工大学 | Different-dimensional switchable chaotic system design method and circuit |
| CN104202146A (en) * | 2014-09-09 | 2014-12-10 | 王忠林 | Yang-Chen system based automatic switching hyper-chaos system construction method and analog circuit |
| CN104378197A (en) * | 2014-12-03 | 2015-02-25 | 王忠林 | Construction method and circuit of memristor-based x-square-contained Lorenz type hyper-chaotic system |
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| CN105634725A (en) | 2016-06-01 |
| CN104883253A (en) | 2015-09-02 |
| CN104883253B (en) | 2016-05-11 |
| WO2016187738A1 (en) | 2016-12-01 |
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