CN105630825B - Data conversion method and device - Google Patents
Data conversion method and device Download PDFInfo
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- CN105630825B CN105630825B CN201410614721.1A CN201410614721A CN105630825B CN 105630825 B CN105630825 B CN 105630825B CN 201410614721 A CN201410614721 A CN 201410614721A CN 105630825 B CN105630825 B CN 105630825B
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Abstract
The invention discloses a data conversion method, which comprises the following steps: when data is input according to a first transmission mode, a write strategy is constructed according to parameters of the input data, and the input data is written into a storage module array according to the write strategy; and when the storage capacity of the storage module array reaches an output threshold value, establishing a reading strategy according to parameters of input data, and outputting and packaging the data in the storage module array according to the reading strategy in a second transmission mode. The invention also discloses a data conversion device.
Description
Technical Field
The present invention relates to data processing technologies, and in particular, to a data conversion method and apparatus.
Background
An Optical Transport Network (OTN) is a Transport Network based on a wavelength division multiplexing technology and organized in an Optical layer Network; in the 100G network era, the OTN needs to carry service data of a 100 Gigabit Ethernet (GE), and therefore, encapsulation mapping from the 100GE service to the OTN service needs to be performed; GE service is characterized by variable packet length and variable flow, and OTN service is characterized by fixed rate, so that in the process of encapsulating an ethernet packet to OTN service, GE service is adapted to fixed ONT rate through a Generic Framing Procedure (GFP); the GFP data is in a time division format, namely the data is sent according to a channel; as shown in fig. 1, F6F 6F 6282828 is a frame header, MFAS is a multiframe number, FF is an overhead part, and D is data; the ODUflex data is in a space division format, that is, the data is sent in time slots, and each byte of one beat of data input to each channel can be mapped to any one time slot.
At present, when time division format data is converted into space division format data, the corresponding relation between each channel and a time slot needs to be known; for example, a 100G OTN includes 80 time slots, and a GFP data frame includes a plurality of channels, each of which may occupy any one or more of the 80 time slots; calculating a mapping rule according to the corresponding relation between the channel number and the time slot, and converting the time division format data into space division format data according to the calculated mapping rule; the GFP data subjected to format conversion is a processed ethernet packet with a fixed rate, that is, the GFP bandwidth is fixed, the number of channels is limited, and the GFP data is framed and then mapped into the OTN service of a fixed time slot, which results in limited flexibility of the data service; in addition, when the mapping rule is calculated, a large amount of chip resources are occupied, and the cost of converting the time division format data into the space division format data is increased.
Disclosure of Invention
In view of this, embodiments of the present invention are expected to provide a data conversion method and apparatus, which can reduce the cost of data conversion and improve the flexibility of data services while realizing the conversion from time division format data to space division format data.
The technical scheme of the embodiment of the invention is realized as follows:
the embodiment of the invention provides a data conversion method, which comprises the following steps: when data is input according to a first transmission mode, a write strategy is constructed according to parameters of the input data, and the input data is written into a storage module array according to the write strategy; and when the storage capacity of the storage module array reaches an output threshold value, establishing a reading strategy according to parameters of input data, and outputting and packaging the data in the storage module array according to the reading strategy in a second transmission mode.
In the foregoing implementation scheme, after the data is input according to the first input mode, the method further includes: and sending an idle request signal according to the flow of the data output by the storage module array, wherein the idle request signal is used for informing the time of inserting an idle frame when the data is input in the first transmission mode.
In the foregoing implementation, the constructing a write strategy according to parameters of input data includes: calculating a write cycle according to the number of time slots occupied by each channel when data are input and the bit width of the input data, and constructing a write strategy according to the write cycle and the counting result of a counter in each channel; wherein the write strategy comprises: and sequentially writing the input data into storage units with storage identifications in the storage module array according to the input period, wherein the storage units with the position difference of integral multiple of the write period have the same storage identifications.
In the foregoing implementation, the constructing a read policy according to the parameters of the input data includes: calculating a reading cycle of each channel according to the number of time slots occupied by each channel when data are input and the bit width of the input data, and constructing a reading strategy according to the reading cycle; wherein the read strategy comprises: sequentially outputting the data in the storage module array at each time slot according to the sequence of the storage unit identification; and the number of the storage units occupied by the data in the storage module array output in each time slot is the value of a read cycle.
In the above implementation scheme, the number of rows of the memory module array is the number of time slots of the data frame output by the memory module array, and the number of columns of the memory module array is the bit width of the input data frame.
An embodiment of the present invention further provides a data conversion apparatus, where the apparatus includes: the device comprises a first framing module, a read-write control module, a storage module array and a second framing module; wherein the content of the first and second substances,
the first framing module is used for inputting data according to a first transmission mode and writing the data input by the first framing module according to a write strategy into the storage module array;
the read-write control module is used for constructing a write strategy according to the parameters of the input data and triggering the first framing module to write the input data into the storage module array according to the write strategy; establishing a reading strategy according to the parameters of the input data, and triggering the storage module array to output the data in the storage module array according to the reading strategy in a second transmission mode;
the storage module array is used for storing the data input by the first framing module and outputting the data stored by the storage module array according to the reading strategy in a second transmission mode;
and the second framing module is used for packaging the data output by the storage module array.
In the above implementation scheme, the second framing module is further configured to send an idle request signal according to a traffic size of data output by the storage module array;
correspondingly, the first framing module is further configured to insert an idle frame according to the idle request signal.
In the above implementation scheme, the read-write control module is specifically configured to calculate a write cycle according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and construct a write strategy according to the write cycle and a count result of a counter in each channel; wherein the content of the first and second substances,
the write strategy includes: and sequentially writing the input data into storage units with storage identifications in the storage module array according to the input period, wherein the storage units with the position difference of integral multiple of the write period have the same storage identifications.
In the above implementation scheme, the read-write control module is specifically configured to calculate a read cycle of each channel according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and construct a read strategy according to the read cycle; wherein the content of the first and second substances,
the read strategy comprises: sequentially outputting the data in the storage module array at each time slot according to the sequence of the storage unit identification; and the number of the storage units occupied by the data in the storage module array output in each time slot is the value of a read cycle.
In the above implementation scheme, the number of rows of the memory module array is the number of time slots of the memory module for outputting the data frame, and the number of columns of the memory module array is the bit width of the input data frame.
According to the data conversion method and device provided by the embodiment of the invention, when data is input according to a first transmission mode, a write strategy is constructed according to parameters of the input data, and the input data is written into a storage module array according to the write strategy; and when the storage capacity of the storage module array reaches an output threshold value, constructing a reading strategy according to parameters of input data, and outputting and packaging the data in the storage module array according to the reading strategy in a second transmission mode. Therefore, by constructing a write strategy and a read strategy in a Micro Control Unit (MCU), the use of chip resources is reduced, and the cost of converting time division format data into space division format data is reduced; the storage module array is used for storing input data, GFP data of multiple channels and any bandwidth are mapped to ODUflex frames of any rate, and flexibility of data service is improved.
Drawings
Fig. 1 is a schematic structural diagram of ODUflex data;
FIG. 2 is a schematic diagram of a basic processing flow of a data conversion method according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a memory module array;
FIG. 4 is a detailed processing flow diagram of a data conversion method according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a data storage structure of a RAM according to an embodiment of the present invention;
FIG. 6 is a detailed processing flow diagram of a second data conversion method according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a data storage structure of a second RAM according to an embodiment of the present invention;
FIG. 8 is a detailed processing flow diagram of a third data conversion method according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a data storage structure of a triple RAM according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a data conversion device according to an embodiment of the present invention.
Detailed Description
In the embodiment of the invention, when data is input according to a first transmission mode, a write strategy is constructed according to parameters of the input data, and the input data is written into a storage module array according to the write strategy; and when the storage capacity of the storage module array reaches an output threshold value, constructing a reading strategy according to parameters of input data, and outputting and packaging the data in the storage module array according to the reading strategy in a second transmission mode.
As shown in fig. 2, the basic processing flow of the data conversion method in the embodiment of the present invention includes the following steps:
specifically, a first framing module inputs data according to a first transmission mode; the read-write control module calculates a write cycle according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and configures a channel counter for each channel for counting the number of times of input data of the channel; after a write strategy is established according to the write cycle and the statistical result of the counter, a first framing module is triggered to write the input data into a storage module array according to the write strategy; the first framing module writes data input by the first framing module according to the write strategy into the storage module array in a first input mode;
the first transmission mode can be a channel-based transmission mode, and the first framing module can perform data write control in a very multiplexing mode; the writing period is a period in which the same writing strategy occurs and is represented by WriteRound, wherein the WriteRound is g _ SlotNumber/k; g _ SlotNumber represents the number of time slots occupied by each channel when data are input, W represents the bit width of the input data, and k is the greatest common divisor of W and g _ SlotNumber; the minimum writing period is 1, and the maximum writing period is determined by the number of divided time slots of the second framing module; the write strategy includes: sequentially writing input data into storage units with storage identifications in a storage module array according to an input period, wherein the storage units with position difference of integral multiple of the write period have the same storage identifications; when a plurality of channels transmit data, the writing cycles of different channels are different because the number of time slots occupied by different channels is different;
here, the Memory module array may be a Random-Access Memory (RAM) array, and a schematic structural diagram of the Memory module array is shown in fig. 3, where the Memory module array is composed of a plurality of Memory units, each Memory unit is 8-bit wide, the number of rows of the Memory module array is the number of time slots of the data frame output by the Memory module array, the number of columns of the Memory module array is the bit wide of the input data frame, data of each beat is stored in N Memory units with 8-bit wide, and each row of Memory units corresponds to X time slots one by one.
102, when the storage capacity of the storage module array reaches an output threshold value, constructing a reading strategy according to parameters of input data, and outputting and packaging data in the storage module array according to the reading strategy in a second transmission mode;
specifically, when the storage capacity of the storage module array reaches half of the total capacity of the storage module array, the read-write control module calculates the read cycle of each channel according to the number of time slots occupied by each channel when data is input and the bit width of the input data, constructs a read strategy according to the read cycle, and triggers the storage module array to output the data in the storage module array according to the read strategy and a second transmission mode; the storage module array outputs self-stored data according to the reading strategy in a second transmission mode; the second framing module encapsulates the data output by the storage module array;
the second transmission mode may be a transmission mode according to a time slot; the reading period is a period in which the same reading strategy appears and is represented by ReadRound, wherein the ReadRound is W/k; w represents the bit width of input data, g _ SlotNumber represents the number of time slots occupied by each channel when the data is input, and k is the greatest common divisor of W and g _ SlotNumber; the read strategy comprises: sequentially outputting the data in the storage module array at each time slot according to the sequence of the storage unit identification; the number of storage units occupied by the data in the storage module array output by each time slot is a value of a read cycle; when a plurality of channels transmit data, the number of time slots occupied by different channels is different, so that the reading periods of different channels are also different.
Further, when the first transmission mode is a channel-based transmission mode, the first framing module is a GFP framing module, and the input data rate is dynamically changed; when the second transmission mode is a transmission mode according to time slots, the second framing module is an ODUflex framing module, and the output data rate is constant; the second framing module divides the second framing module 14 into X time slots to ensure continuous data stream input, and the second framing module can send an idle request signal to the first framing module once according to the data flow output by the storage module array every X beats at each instant time slot, wherein the idle request signal is used for informing the first framing module of the time for inserting an idle frame so as to avoid the idle request signal collision sent by each channel; the number of times each channel sends an idle request every X beats is determined by the number of slots occupied by the channel.
Example one
For example, a data service uses one channel for transmission, the channel is mapped to timeslots 0-2, the input data bit width is 320 bits, the first framing module is a GFP framing module, the second framing module is an ODUflex framing module, and the ODUflex framing module is divided into 80 timeslots, as shown in fig. 4, a detailed processing flow of the data conversion method in the embodiment of the present invention includes the following steps:
step 201, a read-write control module calculates a first write cycle according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and constructs a first write strategy according to the first write cycle;
specifically, W320/8 40 g SlotNumber1So, k is 31Is W and g _ SlotNumber1Greatest common divisor of 1, WriteRound1＝g_SlotNumber1/k1＝3/1＝3；
The first write strategy is as follows: storing 320bit data of a first period into a storage unit of a black mark of a 1 st row and a 1 st column of a storage module array, storing 320bit data of a second period into a storage unit of a 1 st row and a 3 rd column of a storage module array, storing 320bit data of a third period into a storage unit of a 1 st row and a 2 nd column of a circular mark of the storage module array, storing 320bit data of a fourth period into a storage unit of a 1 st row and a 4 th column of the storage module array, storing 320bit data of a fifth period into a storage unit of a 1 st row and a 6 th column of a reverse oblique line mark of the storage module array, storing 320bit data of a sixth period into a storage unit of a 1 st row and a 5 th column of the storage module array, and so on; i.e. with a period of three beats.
specifically, a schematic diagram of a data storage structure of a RAM according to an embodiment of the present invention is shown in fig. 5.
in particular, the amount of the solvent to be used,W＝320/8＝40，g_SlotNumber1so, k is 31Is W and g _ SlotNumber1Greatest common divisor of 1, ReadRound1＝W/k1＝40/1＝40；
The first read strategy is: the sequence of the read addresses of the time slot 0 in the memory module array is 1 st, 4 th, 7 th, 10 th, 13 th, 16 th, 19 th, 22 th, 25 th, 28 th, 31 th, 34 th, 37 th, 40 th, 3 th, 6 th, 9 th, 12 th, 15 th, 18 th, 21 th, 24 th, 27 th, 30 th, 33 th, 36 th, 39 th, 2 th, 5 th, 8 th, 11 th, 14 th, 17 th, 20 th, 23 th, 26 th, 29 th, 32 th, 35 th and 38 th rows of the RAM array; the sequence of the read addresses of the time slot 1 in the memory module array is the 2 nd, 5 th, 8 th, 11 th, 14 th, 17 th, 20 th, 23 th, 26 th, 29 th, 32 th, 35 th, 38 th, 1 th, 4 th, 7 th, 10 th, 13 th, 16 th, 19 th, 22 th, 25 th, 28 th, 31 th, 34 th, 37 th, 40 th, 3 th, 6 th, 9 th, 12 th, 15 th, 18 th, 21 th, 24 th, 27 th, 30 th, 33 th, 36 th and 39 th rows of the RAM array; the reading order of the time slot 2 is the 3 rd, 6 th, 9 th, 12 th, 15 th, 18 th, 21 th, 24 th, 27 th, 30 th, 33 th, 36 th, 39 th, 2 th, 5 th, 8 th, 11 th, 14 th, 17 th, 20 th, 23 th, 26 th, 29 th, 32 th, 35 th, 38 th, 1 th, 4 th, 7 th, 10 th, 13 th, 16 th, 19 th, 22 th, 25 th, 28 th, 31 th, 34 th, 37 th, 40 th column of the RAM array.
In the first embodiment of the present invention, an idle request counter is set in the read/write control module, counting is performed from 0 to 80, and after receiving an idle request signal from the ODUflex framing module, the read/write control module sends an idle request signal to the GFP framing module after counting by 1 to 3 of the counter, and notifies the GFP framing module to insert an idle frame, thereby ensuring continuous stream input; wherein, the counter counts 1-3 are the mapping of the data corresponding to one channel in the first embodiment of the present invention to the slots 0-2.
Example two
For example, a data service uses one channel for transmission, the channel is mapped to timeslots 0-79, the input data bit width is 320 bits, the first framing module is a GFP framing module, the second framing module is an ODUflex framing module, and the ODUflex framing module is divided into 80 timeslots, as shown in fig. 6, a detailed processing flow of a second data conversion method according to an embodiment of the present invention includes the following steps:
step 301, the read-write control module calculates a second write cycle according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and constructs a second write strategy according to the second write cycle;
specifically, W320/8 40 g SlotNumber2So, k is 802Is W and g _ SlotNumber2Maximum common divisor of 40, WriteRound2＝g_SlotNumber2/k2＝80/40＝2；
The second write strategy is: storing 320bit data of a first period into a storage unit of a black mark of a storage module array, storing 320bit data of a second period into a storage unit of a reverse oblique line mark of the storage module array, storing 320bit data of a third period into the storage unit of the black mark of the storage module array, storing 320bit data of a fourth period into the storage unit of the reverse oblique line mark of the storage module array, and so on; i.e. with a period of two beats.
specifically, a schematic diagram of a data storage structure of a RAM according to an embodiment of the present invention is shown in fig. 7.
specifically, W320/8 40 g SlotNumber2So, k is 802Is W and g _ SlotNumber240 of greatest common divisor, ReadRound2＝W/k2＝40/40＝1；
The second read strategy is: the read address of the time slot 0 in the memory module array is row 1, column 1, the read address of the time slot 1 in the memory module array is row 2, column 2, the read address of the time slot 2 in the memory module array is row 3, column 3.. the read address of the time slot 39 in the memory module array is row 40, column 40, the read address of the time slot 40 in the memory module array is row 41, column 1, the read address of the time slot 41 in the memory module array is row 42, column 2.. the read address of the time slot 79 in the memory module array is column 40, row 80.
In the second embodiment of the present invention, an idle request counter is set in the read/write control module, counting from 0 to 80, and when receiving an idle request signal from the ODUflex framing module, the read/write control module sends an idle request signal to the GFP framing module after counting from 1 to 80 by the counter value, and notifies the GFP framing module to insert an idle frame, thereby ensuring continuous stream input; wherein, the counter counts 1-80 are the mapping of the data corresponding to one channel in the second embodiment of the present invention to the time slots 0-79.
EXAMPLE III
In an embodiment of the present invention, a data service is transmitted using two channels, where a first channel is mapped to timeslots 0 to 5, a second channel is mapped to timeslots 8, 9, and 11, an input data bit is 320 bits, a first framing module is a GFP framing module, a second framing module is an ODUflex framing module, and the ODUflex framing module is divided into 80 timeslots, as shown in fig. 8, a detailed processing flow of a data conversion method in the third embodiment of the present invention includes the following steps:
specifically, W320/8 40 g SlotNumber3So, k is 63Is W and g _ SlotNumber32, WriteRound of3＝g_SlotNumber3/k3＝6/2＝3；g_SlotNumber4＝3，k4Is W and g _ SlotNumber4Greatest common divisor of 1, WriteRound4＝g_SlotNumber4/k4＝6/1＝6；
The third write strategy is: for a first channel, storing 320bit data of a first period into a storage unit of a black mark in a first row and a first column of a storage module array, storing 320bit data of a second period into a storage unit of a reverse oblique line mark in a first row and a third column of the storage module array, storing 320bit data of a third period into a storage unit of a circular mark in a first row and a fifth column of the storage module array, storing 320bit data of a fourth period into a storage unit of a black mark in a first row and a seventh column of the storage module array, and the like; namely, storing the data in a cycle of three beats; for the second channel, storing 320bit data of the first period into a storage unit of a black mark in a first row and a first column of a ninth row of the storage module array, storing 320bit data of the second period into a storage unit of a reverse oblique line mark in a third row and a third column of the ninth row of the storage module array, storing 320bit data of the third period into a storage unit of a circular mark in a second column of the ninth row of the storage module array, storing 320bit data of the fourth period into a storage unit of a black mark in a fourth column of the ninth row of the storage module array, and so on; i.e. with a period of three beats.
specifically, a schematic diagram of a data storage structure of a triple RAM according to an embodiment of the present invention is shown in fig. 9.
specifically, W320/8 40 g SlotNumber3So, k is 63Is W and g _ SlotNumber32, ReadRound3＝W/k3＝40/2＝20；g_SlotNumber4So, k is 34Is W and g _ SlotNumber4Greatest common divisor of 1, ReadRound4＝W/k4＝40/1＝40；
The third read strategy is: the sequence of the read addresses of the time slot 0 in the memory module array is 1 st, 7 th, 13 th, 19 th, 25 th, 31 th, 37 th, 3 th, 9 th, 15 th, 21 th, 27 th, 33 th, 39 th, 5 th, 11 th, 17 th, 23 th, 29 th and 35 th columns of the RAM array; the sequence of the read addresses of the time slot 1 in the memory module array is the 2 nd row, 8 nd row, 14 nd row, 20 nd row, 26 nd row, 32 nd row, 38 nd row, 4 nd row, 10 th row, 16 nd row, 22 nd row, 28 th row, 34 th row, 40 th row, 6 th row, 12 th row, 18 th row, 24 th row, 30 th row and 36 th row of the RAM array; the sequence of the read addresses of the time slot 2 in the memory module array is the 3 rd, 9 th, 15 th, 21 th, 27 th, 33 th, 39 th, 5 th, 11 th, 17 th, 23 th, 29 th, 35 th, 1 th, 7 th, 13 th, 19 th, 25 th, 31 th and 37 th columns of the RAM array; the sequence of the read addresses of the time slot 3 in the memory module array is the 4 th, 10 th, 16 th, 22 th, 28 th, 40 th, 6 th, 12 th, 18 th, 24 th, 30 th, 36 th, 2 th, 8 th, 14 th, 20 th, 26 th, 32 th and 38 th columns of the RAM array; the sequence of the read addresses of the time slot 4 in the memory module array is the 5 th, 11 th, 17 th, 23 th, 29 th, 35 th, 41 th, 7 th, 13 th, 19 th, 25 th, 31 th, 37 th, 3 th, 9 th, 15 th, 21 th, 27 th, 33 th and 39 th columns of the RAM array; the sequence of the read address of the time slot 5 in the memory module array is the 6 th, 12, 18, 24, 30, 36, 2, 8, 14, 20, 26, 32, 38, 4, 10, 16, 22, 28, 34 and 40 th row of the RAM array;
the fourth read strategy is: the sequence of the read addresses of the time slot 8 in the memory module array is 1 st, 4 th, 7 th, 10 th, 13 th, 16 th, 19 th, 22 th, 25 th, 28 th, 31 th, 34 th, 37 th, 40 th, 3 th, 6 th, 9 th, 12 th, 15 th, 18 th, 21 th, 24 th, 27 th, 30 th, 33 th, 36 th, 39 th, 2 th, 5 th, 8 th, 11 th, 14 th, 17 th, 20 th, 23 th, 26 th, 29 th, 32 th, 35 th and 38 th rows of the RAM array; the sequence of the read addresses of the time slot 9 in the memory module array is the 10 th row 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36 and 39 of the RAM array; the sequence of the read addresses of the time slot 11 in the memory module array is the 3 rd, 6 th, 9 th, 12 th, 15 th, 18 th, 21 th, 24 th, 27 th, 30 th, 33 th, 36 th, 39 th, 2 th, 5 th, 8 th, 11 th, 14 th, 17 th, 20 th, 23 th, 26 th, 29 th, 32 th, 35 th, 38 th, 1 th, 4 th, 7 th, 10 th, 13 th, 16 th, 19 th, 22 th, 25 th, 28 th, 31 th, 34 th, 37 th and 40 th rows of the RAM array.
In the third embodiment of the present invention, an idle request counter is set in the read/write control module, counting is performed from 0 to 80, and after receiving an idle request signal from the ODUflex framing module, the first channel sends an idle request signal to the GFP framing module after the read/write control module counts 1 to 6 by the counter, and notifies the GFP framing module to insert an idle frame, thereby ensuring continuous stream input; the second channel sends an idle request signal to the GFP framing module after the read-write control module counts 9, 10 and 12 by the counter; the counter counts 1 to 6 are data mapping slots 0 to 5 corresponding to the first channel in the third embodiment of the present invention, and the counter counts 9, 10 and 12 are data mapping slots 8, 9 and 11 corresponding to the second channel in the third embodiment of the present invention.
The embodiment of the invention can be used for mapping GFP frame data with multiple channels and any bandwidth to OUDflex frame data with any rate, realizes the random pairing of channel input data and time slot input and output, and increases the flexibility of service. In the embodiment of the invention, each channel is respectively divided into a storage space for storing the data mapping rule, and the data mapping rule is updated according to the service requirement, so that each channel is completely independent and does not interfere with each other.
In order to implement the above data conversion method, an embodiment of the present invention further provides a data conversion apparatus, where a composition structure of the apparatus is shown in fig. 10, and the apparatus includes: a first framing module 11, a read-write control module 12, a storage module array 13 and a second framing module 14; wherein the content of the first and second substances,
the first framing module 11 is configured to input data according to a first transmission mode, and write data input by itself according to the first input mode into the storage module array 12 according to a write strategy;
the read-write control module 12 is configured to construct a write strategy according to the parameter of the input data, and trigger the first framing module 11 to write the input data into the storage module array 13 according to the write strategy; establishing a reading strategy according to the parameters of the input data, and triggering the storage module array 13 to output the data in the storage module array 13 according to the reading strategy in a second transmission mode;
the storage module array 13 is configured to store the data input by the first framing module 11, and output the data stored in the storage module array according to the read policy in a second transmission manner;
the second framing module 14 is configured to encapsulate data output by the storage module array 13.
In the foregoing implementation scheme, the second framing module 14 is further configured to send an idle request signal according to a flow rate of data output by the storage module array;
correspondingly, the first framing module 11 is further configured to insert an idle frame according to the idle request signal. The read-write control module 12 is specifically configured to calculate a write cycle according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and construct a write strategy according to the write cycle and the count result of the counter in each channel; wherein the content of the first and second substances,
the write strategy includes: the input data is written into the storage units with storage identifications in the storage module array 13 in sequence according to the input period, and the storage units with position difference of integral multiple of the write period have the same storage identifications.
The read-write control module 12 is specifically configured to calculate a read cycle of each channel according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and construct a read strategy according to the read cycle; wherein the content of the first and second substances,
the read strategy comprises: sequentially outputting the data in the memory module array 13 at each time slot according to the sequence of the memory unit identifier; the number of memory cells occupied by the data in the memory module array 13 output in each time slot is a value of a read cycle.
In the above implementation scheme, the number of rows of the storage module array 13 is the number of time slots of the storage module for outputting the data frame, and the number of columns of the storage module array is the bit width of the input data frame.
In the above implementation scheme, the first framing module 11 inputs data according to a first transmission mode; the read-write control module 12 calculates a write cycle according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and configures a channel counter for each channel to count the channel as the input data for the second time; after a write strategy is constructed according to the write cycle and the statistical result of the counter, triggering a first framing module 11 to write the input data into a storage module array 13 according to the write strategy; the first framing module 11 writes the data input by itself according to the first input mode into the storage module array 13 according to the write strategy;
in the above implementation scheme, the first transmission mode may be a channel-based transmission mode, and the first framing module 11 may perform data write control in a very multiplexing manner; the writing period is a period in which the same writing strategy occurs and is represented by WriteRound, wherein the WriteRound is g _ SlotNumber/k; g _ SlotNumber represents the number of time slots occupied by each channel when data are input, W represents the bit width of the input data, and k is the greatest common divisor of W and g _ SlotNumber; the minimum writing period is 1, and the maximum writing period is determined by a formula coefficient divided by the second framing module; the write strategy includes: sequentially writing input data into storage units with storage identifications in a storage module array according to an input period, wherein the storage units with position difference of integral multiple of the write period have the same storage identifications; when a plurality of channels transmit data, the writing cycles of different channels are different because the number of time slots occupied by different channels is different;
in the above implementation scheme, the storage module array 13 is composed of a plurality of storage units, each storage unit has a bit width of 8 bits, the number of rows of the storage module array is the number of time slots of the data frame output by the storage module array, the number of columns of the storage module array is the bit width of the input data frame, data of each beat is just stored in N storage units having a bit width of 8 bits, and each row of storage units corresponds to X time slots one by one.
In the above implementation scheme, when the storage capacity of the storage module array 13 reaches half of the total capacity of the storage module array, the read-write control module 12 calculates a read cycle of each channel according to the number of time slots occupied by each channel when data is input and the bit width of the input data, constructs a read policy according to the read cycle, and triggers the storage module array 13 to output data in the storage module array 13 according to the read policy in a second transmission mode; the storage module array 13 outputs the data stored by itself according to the read strategy in a second transmission mode; the second framing module encapsulates the data output by the storage module array 13;
in the foregoing implementation, the second transmission mode may be a transmission mode according to a time slot; the reading period is a period in which the same reading strategy appears and is represented by ReadRound, wherein the ReadRound is W/k; w represents the bit width of input data, g _ SlotNumber represents the number of time slots occupied by each channel when the data is input, and k is the greatest common divisor of W and g _ SlotNumber; the read strategy comprises: sequentially outputting the data in the memory module array 13 at each time slot according to the sequence of the memory unit identifier; the number of memory cells occupied by the data in the memory module array 13 output in each time slot is a value of a read cycle; when a plurality of channels transmit data, the number of time slots occupied by different channels is different, so that the reading periods of different channels are also different.
In the above implementation scheme, when the first transmission mode is a channel-based transmission mode, the first framing module 11 is a GFP framing module, and the input data rate is dynamically changed; when the second transmission mode is a transmission mode according to a time slot, the second framing module 14 is an ODUflex framing module, and the output data rate is constant; the second framing module 14 divides the second framing module 14 into X time slots to ensure continuous data stream input, and the second framing module 14 can send an idle request signal to the first framing module 11 once according to the data traffic output by the storage module array 13 every X beats at each time slot, where the idle request signal is used to notify the first framing module 11 of the time for inserting an idle frame, so as to avoid the idle request signal collision sent by each channel; the number of times each channel sends an idle request every X beats is determined by the number of slots occupied by the channel.
It should be noted that, in practical application, the functions of the first framing module 11, the read/write control module 12, the storage module array 13, and the second framing module 14 may be implemented by an MCU, a Central Processing Unit (CPU), or a microprocessor unit (MPU), or a Digital Signal Processor (DSP), or a programmable gate array (FPGA).
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A method of data conversion, the method comprising:
when data is input according to a first transmission mode, a write strategy is constructed according to parameters of the input data, the input data are sequentially written into storage units with storage identifiers in a storage module array according to an input period according to the write strategy, and the storage units with position difference of integral multiple of the write period among the storage units with the storage data have the same storage identifiers, wherein the first transmission mode comprises a channel transmission mode which comprises multiple channel transmission;
and when the storage capacity of the storage module array reaches an output threshold value, constructing a reading strategy according to parameters of input data, and sequentially outputting and packaging the data in the storage module array at each time slot according to the reading strategy and a second transmission mode according to the sequence of the storage unit identifiers, wherein the number of storage units occupied by the data in the storage module array output at each time slot is a value of a reading cycle, and the second transmission mode comprises a time slot transmission mode.
2. The data conversion method of claim 1, wherein after the data is input in the first transmission mode, the method further comprises:
and sending an idle request signal according to the flow of the data output by the storage module array, wherein the idle request signal is used for informing the moment of inserting an idle frame when the data is input in the first transmission mode.
3. The data conversion method according to claim 1, wherein the constructing a write strategy according to the parameters of the input data comprises:
and calculating a write cycle according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and constructing a write strategy according to the write cycle and the counting result of the counter in each channel.
4. The data conversion method of claim 1, wherein the constructing a read strategy according to the parameters of the input data comprises:
and calculating the reading period of each channel according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and constructing a reading strategy according to the reading period.
5. The data conversion method according to claim 1, wherein the number of rows of the memory module array is the number of time slots of the memory module array for outputting the data frame, and the number of columns of the memory module array is the bit width of the input data frame.
6. A data conversion apparatus, characterized in that the apparatus comprises: the device comprises a first framing module, a read-write control module, a storage module array and a second framing module; wherein the content of the first and second substances,
the first framing module is used for inputting data according to a first transmission mode, sequentially writing the data input by the first framing module according to a write strategy into storage units with storage identifiers in a storage module array according to an input period, wherein the storage units with position differences of integral multiples of the write period have the same storage identifiers, the first transmission mode comprises a channel transmission mode, and the channel transmission mode comprises multiple channel transmission;
the read-write control module is used for constructing a write strategy according to the parameters of the input data and triggering the first framing module to write the input data into the storage module array according to the write strategy; establishing a reading strategy according to the parameters of the input data, and triggering the storage module array to sequentially output the data in the storage module array at each time slot according to the reading strategy and a second transmission mode according to the sequence of the storage unit identifiers, wherein the number of the storage units occupied by the data in the storage module array output by each time slot is a value of a reading period, and the second transmission mode comprises a time slot transmission mode;
the storage module array is used for storing the data input by the first framing module and outputting the data stored by the storage module array according to the reading strategy in a second transmission mode;
and the second framing module is used for packaging the data output by the storage module array.
7. The data conversion apparatus according to claim 6, wherein the second framing module is further configured to send an idle request signal according to a traffic size of the data output by the storage module array;
correspondingly, the first framing module is further configured to insert an idle frame time according to the idle request signal.
8. The data conversion apparatus according to claim 6, wherein the read-write control module is specifically configured to calculate a write cycle according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and construct a write strategy according to the write cycle and a count result of a counter in each channel.
9. The data conversion apparatus according to claim 6, wherein said read/write control module,
the method is specifically used for calculating the read cycle of each channel according to the number of time slots occupied by each channel when data is input and the bit width of the input data, and establishing a read strategy according to the read cycle.
10. The apparatus of claim 6, wherein the number of rows of the memory module array is the number of slots of the memory module for outputting the data frame, and the number of columns of the memory module array is the bit width of the input data frame.
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| CN110134365B (en) * | 2019-05-21 | 2022-10-11 | 合肥工业大学 | Method and device for reading FIFO (first in first out) in parallel by multiple channels |
| CN111866579A (en) * | 2020-07-27 | 2020-10-30 | 无锡和博永新科技有限公司 | Data conversion method of V4L2 |
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| WO2012171160A1 (en) * | 2011-06-13 | 2012-12-20 | 华为技术有限公司 | Method and backplane for bit width conversion from time division to space division of optical transport network backplane |
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| US6363008B1 (en) * | 2000-02-17 | 2002-03-26 | Multi Level Memory Technology | Multi-bit-cell non-volatile memory with maximized data capacity |
| CN1571328A (en) * | 2003-07-17 | 2005-01-26 | 深圳市中兴通讯股份有限公司 | Super large-scale cross connection device and method used for synchronous digital transmission system |
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