CN105630120B - A kind of method and device of loading processing device hardware configuration word - Google Patents
A kind of method and device of loading processing device hardware configuration word Download PDFInfo
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- CN105630120B CN105630120B CN201410608256.0A CN201410608256A CN105630120B CN 105630120 B CN105630120 B CN 105630120B CN 201410608256 A CN201410608256 A CN 201410608256A CN 105630120 B CN105630120 B CN 105630120B
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Abstract
This application discloses a kind of devices of loading processing device hardware configuration word, comprising: secondary sources position output module and third class data bit output module；Secondary sources position output module includes m branch, each branch includes: resistance and driver；The input terminal of driver is pulled upward to power supply by resistance, and the output end of driver exports corresponding secondary sources position；Third class data bit output module includes: at least one resistance, at least one NOT gate, at least one switch and n driver corresponding with n third class data bit, the output end of driver exports corresponding third class data bit, the input terminal of driver realizes connection by resistance, NOT gate and switch, the low and high level combination under corresponding operating mode is realized by resistance, NOT gate and switch, and the open and close through switching realizes the switching of the low and high level combination under different working modes；The reset signal of the enable end connection processor of each driver.
Description
Technical field
This application involves digital circuit technique field more particularly to a kind of methods and dress of loading processing device hardware configuration word
It sets.
Background technique
With the development of electronics industry, the scene of processor application is more and more extensive.General processor is required upper
Hardware configuration word is provided when reset, processor according to the hardware configuration word that obtains when resetting determine how initialization processor
Hardware resource, such as the definition of processor work clock, data-interface mode, certain pins.
Processor obtains hardware configuration word when being in reset state, i.e., processor is in reset state on readout data bus
Data, determine its operating mode according to the data of acquisition.If changing the operating mode of processor, it must reset and be
System, while changing the data that processor is obtained when resetting.Existing hardware design generally determines to locate by pulling down on resistance
It manages device and is resetting the data value in time data bus.When processor changes operating mode, need to reconfigure drop-down electricity
Resistance.Although it is smaller to configure resistance change, due to being related to hardware modifications, working efficiency can be seriously affected, while also having can
It can lead to the operation of a series of complex.
Fixing a certain start-up mode of processor by resistance will affect the usage scenario of processor.In practical applications, more
Kind operating mode is a relatively common demand, and the method for changing resistance by hardware mode to realize change operating mode
It will affect production and maintenance efficiency.
It in the prior art, can also be by the storage hardware configuration words on flash memory (flash), by resistance after powering on
The address of drop-down selection flash and read-write, are output to the data for being stored in flash on data/address bus.Need to update place
When managing device operating mode, by the data of instruction modification flash internal hardware configuration words, reset processing again is completed later in modification
Device makes processor reacquire hardware configuration word.Such as in the application of system, processor needs support Three models: 16
Mode, 8 bit patterns and chip test mode.When system, which is in, to be worked normally, processor is in 16 bit patterns, when 16 bit patterns
Under when can not start (board initial power-on, flash malfunctions without code or flash code update under 16 bit patterns), need to transport
Flash code of the row under 8 bit patterns again programming, 16 bit pattern.8 bit patterns can be used as debugging mode, at this time 8 bit pattern
Under flash only need to store most basic starting code, code does not need simply to update, nonexistent code update error cause
The problem of system can not start.If the programming of flash is needed by emulator under 16 bit patterns without this mode.Meanwhile being
Better detection system hardware problem, processor also need work in chip test mode.
There is also some disadvantages in such a way that flash obtains hardware configuration word.Since hardware configuration word is to pass through flash
Output, flash is previously required to preparatory programming starting configuration words in welding.Processor must be protected when acquiring the data of data line
The data for demonstrate,proving flash output are stable correct, while needing to do upper drop-down processing on appropriate address line, to guarantee flash
Output is the data of hardware configuration word.Since hardware configuration word is modified by processor, then it must assure that processor exists
It cannot malfunction when changing configuration words, otherwise be easy to cause processor that can not start.When changing start-up mode, it is necessary at processor
In normal operating conditions, processor could issue the order of change hardware configuration word at this time.Change resets system after completing again,
Processor reacquires hardware configuration word.The process CIMS of entire hardware configuration word change is complicated, spends the time long, was modifying
It cannot be powered off in journey, be not suitable for producing in enormous quantities and maintenance period use in this way.This method needs software simultaneously
It participates in, uncertain factor can be introduced, influence the stability of system.
Summary of the invention
This application provides a kind of device of loading processing device hardware configuration word, in all hardware configuration words that need to be loaded,
Often it is low level data bit as primary sources position, is often the data bit of high level as secondary sources position, the second class
Data bit shares m；The data bit for needing height to change shares n as third class data bit, third class data bit；The device
It include: secondary sources position output module and third class data bit output module；
Secondary sources position output module includes m branch, corresponding with each secondary sources position respectively；It is described
In m branch, i-th of branch includes: resistance Ri and driver DRi；The input terminal of driver DRi is pulled upward to electricity by resistance Ri
The output end of source VCC, driver DRi export corresponding secondary sources position；
Third class data bit output module include: at least one resistance, at least one NOT gate, at least one switch and with
The corresponding n driver of n third class data bit, the output end of driver export corresponding third class data bit, driving
The input terminal of device realizes connection by resistance, NOT gate and switch, is realized under corresponding operating mode by resistance, NOT gate and switch
Low and high level combination, the open and close through switching realize the switching of the low and high level combination under different working modes；
The reset signal of the enable end connection processor of each driver.
Preferably, the value range of the resistance value of the resistance is 1000 ohm to 1000000 ohm.
Preferably, the resistance has 4700 ohm or 10000 ohm of resistance value.
Preferably, the switch is realized using jumper or toggle switch.
Preferably, the NOT gate negates the circuit of function using independent logical device or using with signal come real
It is existing.
Preferably, the corresponding data bit of the processor hardware configuration words is 16,8,32 or 64.
Preferably, the primary sources position passes through the pull down resistor output inside processor.
The embodiment of the present application also provides a kind of methods of loading processing device hardware configuration word, and this method by filling as previously described
Realization is set, this method comprises:
It is the state of closing or opening according to required processor operating mode setting switch before processor reset；
When processor reset, reset signal exports low level, and driver enables as low level, the at this time output of driver
It enables to open, driver exports the data bit of corresponding hardware configuration word；
Processor obtains hardware configuration word when resetting, completes after resetting, and reset signal exports high level, and driver makes
It can be height, the output of driver at this time is enabled to close, and the output of driver becomes high-impedance state.
As can be seen from the above technical solutions, real by the peripheral circuit including resistance, NOT gate, switch and driver device
The various configurations mode load of existing processor hardware configuration words, does not need software auxiliary, passes through hardware realization completely.System is stablized
Reliably, system start-up time can be effectively reduced, be conducive to produce in enormous quantities and is safeguarded, can effectively be improved efficiency.
Detailed description of the invention
Fig. 1 is the device circuit schematic diagram of loading processing device hardware configuration word provided by the embodiments of the present application；
Fig. 2 is the flow diagram that processor provided by the embodiments of the present application obtains hardware configuration word；
Specific embodiment
The method of loading processing device hardware configuration word provided by the present application is a kind of passes through at switch and peripheral circuit realization
The method for managing device hardware configuration word load various configurations mode, the method use following device in circuit: resistance, NOT gate,
Switch and driver realize that the different hardware configuration word of processor loads by the closing or opening of switch.In order to simplify design,
Processor configuration words can be analyzed, reduce upper pull down resistor using processor built-in function.To distinguishing data bit,
The device of signal inversion can be made to realize by NOT gate etc.；By the hardware configuration word of analysis processor, different works is found out
The rule of the corresponding hardware configuration word of operation mode can be used under weak inside processor for being often low level data bit
Pull-up resistor, outside do not need resistive pull-downs；For being often the data bit of high level, the corresponding driver of data bit can be inputted
End is pulled upward to VCC by resistance；For the different data bit of state under different mode, can analyze rule, using resistance,
The devices such as switch and NOT gate realize corresponding low and high level combination.
A kind of device of loading processing device hardware configuration word provided by the present application, in all hardware configuration words that need to be loaded,
Often it is low level data bit as primary sources position, is often the data bit of high level as secondary sources position, the second class
Data bit shares m；The data bit for needing height to change shares n as third class data bit, third class data bit；The device
It include: secondary sources position output module and third class data bit output module；
Secondary sources position output module includes m branch, corresponding with each secondary sources position respectively；It is described
In m branch, i-th of branch includes: resistance Ri and driver DRi；The input terminal of driver DRi is pulled upward to electricity by resistance Ri
The output end of source VCC, driver DRi export corresponding secondary sources position；
Third class data bit output module include: at least one resistance, at least one NOT gate, at least one switch and with
The corresponding n driver of n third class data bit, the output end of driver export corresponding third class data bit, driving
The input terminal of device realizes connection by resistance, NOT gate and switch, is realized under corresponding operating mode by resistance, NOT gate and switch
Low and high level combination, the open and close through switching realize the switching of the low and high level combination under different working modes；
The reset signal of the enable end connection processor of each driver.
The method of the loading processing device hardware configuration word provided by the present application realized by above-mentioned apparatus, in processor reset
It before, is the state of closing or opening according to required processor operating mode setting switch；
When processor reset, reset signal exports low level, and driver enables as low level, the at this time output of driver
It enables to open, driver exports the data bit of corresponding hardware configuration word；
Processor obtains hardware configuration word when resetting, completes after resetting, and reset signal exports high level, and driver makes
It can be height, the output of driver at this time is enabled to close, and the output of driver becomes high-impedance state.
To keep the technical principle, feature and technical effect of technical scheme clearer, below in conjunction with specific reality
Example is applied technical scheme is described in detail.
The corresponding hardware configuration word of a kind of Three models of processor as listed in Table 1.By analysis, D0, D2,
D3, D6, D8, D11, D13, D14, D15 are often low level, and D1, D7, D9 and D10 are often high level, and D4, D5 and D12 need basis
Operating mode makes corresponding change.
Table 1
In this example, D0, D2, D3, D6, D8, D11, D13, D14, D15 are often low level data bit, can be direct
Using the weak pull-down inside processor, circuit does not need to do special processing.
The device circuit schematic diagram of loading processing device hardware configuration word provided by the embodiments of the present application as shown in Figure 1, second
Class data bit output module 101 includes four branches, and respectively corresponding D1, D7, D9 and D10 this four often is the data of high level
, respectively with the output end 1B of driver in circuit, 2B, 3B are connected with 4B, in input terminal 1A, 2A, 3A and the 4A of driver
Respectively by resistance R1, R2, R3 and R4 are pulled upward to VCC.
The level state of D4, D5 and D12 need to make in different modes variation, when 16 bit pattern, D4, D5 and D12
It needs to configure as " 100 " state, when 8 bit pattern, D4, D5 and D12 are needed to configure as " 010 " state, D4 and D5 state just phase
Instead.Third class data bit output module 102 is used for outputs data bits D4, D5 and D12, including resistance R5 and R6, switch S1 and S2,
NAND gate V1 and V2 and three driver.
The corresponding driver input end 5A of D4 data bit is pulled upward to VCC, the corresponding driver of D5 data bit using resistance R5
Reuse R5 after input terminal 6A connection NOT gate V1 and be pulled upward to VCC, the effect of NOT gate V1 be so that driver 5A and 6A state just
On the contrary, switch S1 to earth level GND is accessed in the centre that R5 is connected with V1 again, the effect of switch S1 is the state so that 5A and 6A
It can change, when S1 is disconnected, the state of 5A and 6A are " 10 ", and when S1 closure, the state of 5A and 6A are " 01 ", in this way
The configuration variation of D4 and D5 are just realized by the disconnection and closure of S1；In chip test mode, the state of D4 and D5 are not related to
Note, D12 become high level from low level, are pulled upward to VCC by R6 resistance again after the 7A input terminal of driver is connected NOT gate V2,
Switch S2 to GND is accessed in the centre that R6 is connected with V2 again, so that the state of D12 is low level when S2 is disconnected, when S2 is closed
When D12 state be high level, chip test mode can be entered in this way.
Circuit concrete form in Fig. 1 is merely illustrative, not to limit application scheme.Those skilled in the art can be with
The technical inspiration provided according to Fig. 1, the circuit for designing entirely different form based on present techniques thought realize various hardware
The load of configuration words.
According to above-mentioned example as can be seen that when the data bit that the output end of driver connects needs high level, then it will correspond to
Input terminal VCC is pulled upward to by resistance, the data bit of the output end connection of driver needs high level or low level change
When change, then corresponding input terminal is realized to the configuration variation of corresponding low and high level by resistance, NOT gate and switch combination.
The effect of the output enable end (EN) of driver is: when EN is low level, driver output is enabled to be opened, and EN is height
When level, driver output is enabled to be closed.By the EN of driver and processor reset signals in circuit used in this application
(HRESET) it connects, when processor reset, HRESET exports low level, and processor obtains hardware configuration word, and EN is low level,
Driver is enabled to be opened, and output end can be with output signal；When processor reset is completed, HRESET signal becomes high level, and EN is
High level, driver is enabled to close, and output end is high-impedance state, and driver will not influence processor data bus at this time.
Processor output reset signal HRESET when resetting indicates that processor is resetting when HRESET is low level,
After the completion of processor reset, HRESET becomes high level.
The variation of processor hardware configuration words may be implemented by open and close by switch S1 and S2, can in circuit realization
It is realized in a manner of using wire jumper, toggle switch can be used also to realize.The open and close of switch must be multiple in processor
It is provided with before position.
Resistance value range of choice can choose 4700 ohm or 10000 from 1000 ohm to 1000000 ohm
Ohm etc..
The effect of NOT gate V1 and V2 are to realize that logical zero arrives the reverse phase of logical zero to logic 1 or logic 1, can in circuit realization
It is realized with using individual logic chip, also can be used and negate the circuit of function with signal to realize.
Processor provided by the embodiments of the present application obtain the process of hardware configuration word as shown in Fig. 2,
When processor needs work in 16 bit pattern, disconnection S1 disconnects S2, resetting processor, and processor acquires data
The hardware configuration word of bus；
When processor needs work in 8 bit pattern, closure S1 disconnects S2, and resetting processor, it is total that processor acquires data
The hardware configuration word of line；
When processor needs work in chip test mode, closure S2, the state of S1 is not concerned with.Resetting processor, place
Manage the hardware configuration word of device acquisition data/address bus.
The corresponding data bit of processor hardware configuration words mentioned in above embodiments is D0-D15 totally 16, but this method
16 are not limited to, is also possible to 8 hardware configuration words of D0-D7 or 32 hardware configuration words of D0-D31, is also possible to more
Situations such as more such as 64 hardware configuration words.
The different configuration mode loading methods for the processor hardware configuration words mentioned in above embodiments may be implemented at 3 kinds
Manage the switching of device operating mode, but the application method be not limited to the above embodiments in 3 kinds of modes being previously mentioned, can also be used to
Processor configures other operating modes or interface rate state etc., such as: the PLL parameter of processor, the work of processor
Dominant frequency, the DDR operating mode of processor, DDR rate, bus clock selection, start flash type, USB interface master slave mode and
The speed grade of support, Ethernet, the 1X of SRIO high-speed interface, 2X, 4X mode etc..Mode hardware configuration words as needed are done
It analyzes out, finds out identical and different data bit, switch, resistance, NOT gate and driver etc. are used for the data bit of variation
Device combines to be combined into multiple hardwares configuration words, and adding for different hardware configuration words can be realized using the above method
It carries.
The foregoing is merely the preferred embodiments of the application, not to limit the protection scope of the application, it is all
Within the spirit and principle of technical scheme, any modification, equivalent substitution, improvement and etc. done should be included in this Shen
Within the scope of please protecting.
Claims (8)
1. a kind of device of loading processing device hardware configuration word, which is characterized in that in all hardware configuration words that need to be loaded, Chang Wei
Low level data bit is often the data bit of high level as secondary sources position, secondary sources as primary sources position
Position shares m；The data bit for needing height to change shares n as third class data bit, third class data bit；The device packet
It includes: secondary sources position output module and third class data bit output module；
Secondary sources position output module includes m branch, corresponding with each secondary sources position respectively；The m
In branch, i-th of branch includes: resistance Ri and driver DRi；The input terminal of driver DRi is pulled upward to power supply by resistance Ri
The output end of VCC, driver DRi export corresponding secondary sources position；
Third class data bit output module include: at least one resistance, at least one NOT gate, at least one switch and with n
The output end of the corresponding n driver of third class data bit, driver exports corresponding third class data bit, driver
Input terminal realizes connection by resistance, NOT gate and switch, realizes the height under corresponding operating mode by resistance, NOT gate and switch
Level combinations, the open and close through switching realize the switching of the low and high level combination under different working modes；
The reset signal of the enable end connection processor of each driver.
2. the apparatus according to claim 1, which is characterized in that the value range of the resistance value of the resistance is 1000 ohm
To 1000000 ohm.
3. the apparatus of claim 2, which is characterized in that the resistance is with 4700 ohm or 10000 ohm
Resistance value.
4. the apparatus according to claim 1, which is characterized in that the switch is using jumper or toggle switch come real
It is existing.
5. the apparatus according to claim 1, which is characterized in that the NOT gate is using independent logical device or uses tool
There is signal to negate the circuit of function to realize.
6. the apparatus according to claim 1, which is characterized in that the corresponding data bit of the processor hardware configuration words is 16
Position, 8,32 or 64.
7. the apparatus according to claim 1, which is characterized in that the primary sources position passes through the drop-down inside processor
Resistance output.
8. a kind of method of loading processing device hardware configuration word, which is characterized in that this method is by any one of such as claim 1 to 7
The device realization, this method comprises:
It is the state of closing or opening according to required processor operating mode setting switch before processor reset；
When processor reset, reset signal exports low level, and driver enables as low level, and the output of driver at this time is enabled
To open, driver exports the data bit of corresponding hardware configuration word；
Processor reset when obtain hardware configuration word, complete reset after, reset signal export high level, driver enable be
Height, the output of driver at this time is enabled to close, and the output of driver becomes high-impedance state.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606715A (en) * | 1995-06-26 | 1997-02-25 | Motorola Inc. | Flexible reset configuration of a data processing system and method therefor |
| CN1725207A (en) * | 2005-04-27 | 2006-01-25 | 杭州华为三康技术有限公司 | Method and system for regulating processor allocation mode |
| CN101465754A (en) * | 2008-12-31 | 2009-06-24 | 上海华为技术有限公司 | Method, equipment and communication veneer for loading reset configuration words |
| CN101515240A (en) * | 2009-03-30 | 2009-08-26 | 华为技术有限公司 | Digital signal processor loading method, electronic device and electronic system |
| CN102854962A (en) * | 2012-08-23 | 2013-01-02 | 哈尔滨工业大学 | MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words |
-
2014
- 2014-11-03 CN CN201410608256.0A patent/CN105630120B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606715A (en) * | 1995-06-26 | 1997-02-25 | Motorola Inc. | Flexible reset configuration of a data processing system and method therefor |
| CN1725207A (en) * | 2005-04-27 | 2006-01-25 | 杭州华为三康技术有限公司 | Method and system for regulating processor allocation mode |
| CN101465754A (en) * | 2008-12-31 | 2009-06-24 | 上海华为技术有限公司 | Method, equipment and communication veneer for loading reset configuration words |
| CN101515240A (en) * | 2009-03-30 | 2009-08-26 | 华为技术有限公司 | Digital signal processor loading method, electronic device and electronic system |
| CN102854962A (en) * | 2012-08-23 | 2013-01-02 | 哈尔滨工业大学 | MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words |
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