CN105590834A - Semiconductor device and manufacturing method thereof, and electronic apparatus - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method comprises the following steps: providing a semiconductor substrate, and forming a groove in the semiconductor substrate; precipitating a material layer on the semiconductor layer and at the side wall and the bottom of the groove; implementing chemical-mechanical grinding processing to enable the surface roughness of the material layer disposed at the edge of a wafer to be increased; and implementing high-density plasma chemical vapor deposition, and filling the groove with another material layer. According to the invention, the adhesive power between the material layer formed through the high-density plasma chemical vapor deposition and the material layer below the aforementioned material layer can be improved, and a delamination phenomenon is avoided.

Description

A kind of semiconductor devices and manufacture method thereof, electronic installation

Technical field

The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices andManufacture method, electronic installation.

Background technology

In semiconductor fabrication process, depositing operation is each through being commonly used in Semiconductor substrate to formPlant material layer, wherein, high density plasma CVD technique is for having profundityIn the groove/hole of wide ratio, form material layer, for example, make when fleet plough groove isolation structure halfIn the groove forming in conductive substrate, fill for forming the material of isolation structure.

Prior art forms fleet plough groove isolation structure by following processing step: first, and as figureShown in 1A, provide Semiconductor substrate 100, in Semiconductor substrate 100, be formed for fillingThe groove 101 of isolated material, the step that forms groove 101 comprises: first in Semiconductor substrateUpper formation pad oxide layer 102 then forms hard mask layer in pad oxide layer 102103 (its constituent material is generally silicon nitride), pad oxide layer 102 can as cushionDischarge the stress between hard mask layer 103 and Semiconductor substrate 100, to hard mask layer 103After annealing, utilize hard mask layer 103 to carry out isolated area photoetching as mask, etchFor filling the groove 101 of isolated material; Then, as shown in Figure 1B, at hard mask layer 103Backing layer 104 is formed on the sidewall of upper and groove 101 and bottom, and (its constituent material is generally nitrogenSilica or silica); Then, as shown in Figure 1 C, deposition isolated material 105 is in halfIn conductive substrate 100, with complete filling groove 101, and carry out cmp until revealGo out backing layer 104; Finally, as shown in Fig. 1 D, remove hard mask layer 103 Hes by etchingPad oxide layer 102.

In above-mentioned technical process, adopt high density plasma CVD process depositsWhen isolated material 105, between the isolated material 105 of crystal round fringes and backing layer 104Adhesive force is less than the gravity of isolated material 105 self, and the leafing fragment of generation can cause deviceInefficacy.

Therefore, a kind of method need to be proposed, to address the above problem.

Summary of the invention

For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor devices,Comprise: Semiconductor substrate is provided, in described Semiconductor substrate, forms groove; Partly lead describedOn body substrate and the sidewall of described groove and bottom deposited material layer; Implement cmpProcess, increase so that be positioned at the surface roughness of the described material layer of crystal round fringes; Implement highly denseAnother material layer is filled in degree plasma activated chemical vapour deposition in described groove.

In one example, implement, after described cmp processing, also to comprise and implement to wipeThe step of cleaning treatment, to remove the granule foreign that residues in described material surface.

In one example, described groove for for fill isolated material with form shallow trench isolation fromThe groove of structure.

In one example, before forming described groove, be also included in described Semiconductor substrateThe step of deposit liner layer and hard mask layer successively.

In one example, fill another material layer in described groove after, also comprise: realExecute another cmp, until expose described material layer; Remove and describedly firmly cover by etchingRete and described laying.

In one example, described material layer is the lining being made up of silicon oxynitride or silicaNexine; Described another material layer is described spacer material layer.

In one embodiment, the present invention also provides a kind of semiconductor that adopts said method to manufactureDevice.

In one embodiment, the present invention also provides a kind of electronic installation, described electronic installation bagDraw together described semiconductor devices.

According to the present invention, can promote and to form by high density plasma CVDAdhesive force between the material layer of material layer and this material layer below, the phenomenon of avoiding that delamination occurs.

Brief description of the drawings

Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention. AttachedThere is shown embodiments of the invention and description thereof, be used for explaining principle of the present invention.

In accompanying drawing:

Figure 1A-Fig. 1 D forms fleet plough groove isolation structure and implements successively according to prior artThe schematic cross sectional view of the device that step obtains respectively;

Fig. 2 A-Fig. 2 D is the step that one method is implemented successively according to an exemplary embodiment of the presentThe schematic cross sectional view of the rapid device obtaining respectively;

Fig. 3 is the stream of the step that one method is implemented successively according to an exemplary embodiment of the presentCheng Tu.

Detailed description of the invention

In the following description, a large amount of concrete details have been provided to provide to the present invention moreUnderstand thoroughly. But, it is obvious to the skilled person that the present inventionCan be implemented without one or more these details. In other example, in order to keep awayExempt to obscure with the present invention, be not described for technical characterictics more well known in the art.

In order thoroughly to understand the present invention, will detailed step be proposed in following description, so thatThe semiconductor devices that explaination the present invention proposes and manufacture method thereof, electronic installation. Obviously, thisBright execution is not limited to the specific details that the technical staff of semiconductor applications has the knack of. ThisBright preferred embodiment is described in detail as follows, but except these are described in detail, the present invention alsoCan there are other embodiments.

Should be understood that, when using in this manual term " to comprise " and/or " comprising "Time, it indicates and has described feature, entirety, step, operation, element and/or assembly, butDo not get rid of exist or additional one or more other features, entirety, step, operation, element,Assembly and/or their combination.

[exemplary embodiment one]

With reference to Fig. 2 A-Fig. 2 D, wherein show one side according to an exemplary embodiment of the presentThe schematic cross sectional view of the device that the step that method is implemented successively obtains respectively.

First, as shown in Figure 2 A, provide Semiconductor substrate 200, Semiconductor substrate 200Constituent material can adopt unadulterated monocrystalline silicon, doped with on the monocrystalline silicon of impurity, insulatorSilicon (SOI) etc. As example, in the present embodiment, the formation material of Semiconductor substrate 200Material is selected monocrystalline silicon.

Next, deposit liner layer 202 and hard mask layer successively in Semiconductor substrate 200203. Described low-pressure chemical vapor deposition (LPCVD), the plasma enhanced chemical of being deposited asVapour deposition (PECVD), high vacuum chemical vapour deposition (UHVCVD), Rapid ThermalChemical vapour deposition (CVD) (RTCVD), physical vapour deposition (PVD) (PVD), ald (ALD)And one in molecular beam epitaxy (MBE). As example, the formation material of laying 202Material is oxide, for example silica, and the constituent material of hard mask layer 203 is silicon nitride. LiningBed course 202 can discharge between hard mask layer 203 and Semiconductor substrate 200 as cushionStress.

Then, as shown in Figure 2 B, in Semiconductor substrate 200, be formed for filling isolation materialThe groove 201 of material. After hard mask layer 203 is annealed, utilize hard mask layer 203Carry out isolated area photoetching as mask, etch the groove 201 for filling isolated material.

Then, as shown in Figure 2 C, on hard mask layer 203 and the sidewall of groove 201 andBottom deposition backing layer 204. The described low-pressure chemical vapor deposition, plasma of being deposited as strengthensChemical vapour deposition (CVD), high vacuum chemical vapour deposition, rapid heat chemical vapour deposition, physicsOne in vapour deposition, ald and molecular beam epitaxy. As example, backing layer204 constituent material is silicon oxynitride or silica.

Next, implement cmp processing, so that be positioned at the lining of crystal round fringes 206The surface roughness of layer 204 increases. Then, implement to wipe cleaning treatment, residue in to removeThe granule foreign on backing layer 204 surfaces.

Then, as shown in Figure 2 D, implement high density plasma CVD in grooveIn 201, fill isolated material 205. Owing to being positioned at the table of backing layer 204 of crystal round fringes 206Surface roughness increases, the isolated material forming by high density plasma CVD205 and backing layer 204 between frictional force become large, described frictional force is greater than isolated material 205The gravity of self, thus can delamination occurs phenomenon. Isolated material 205 is generally oxide,For example HARP.

So far, completed the technique step that one method is implemented according to an exemplary embodiment of the presentSuddenly. What above-described embodiment was described is the process that forms isolated material 205, those skilled in the artCan know, in semiconductor fabrication process, also exist by high-density plasmaLearn the manufacturing process that vapour deposition forms other material layer, for example interlayer dielectric layer and etch stopLayer, according to the present invention, before implementing high density plasma CVD, all canWafer is implemented to above-mentioned cmp and process and wipe cleaning treatment, and then promote by highThe material layer of the material layer that density plasma chemical vapour deposition (CVD) forms and this material layer belowBetween adhesive force, the phenomenon of avoiding that delamination occurs.

With reference to Fig. 3, wherein show one method reality successively according to an exemplary embodiment of the presentThe flow chart of the step of executing, for schematically illustrating the flow process of manufacturing process.

In step 301, Semiconductor substrate is provided, in Semiconductor substrate, form groove;

In step 302, in Semiconductor substrate and the sidewall of groove and bottom deposition materialsLayer;

In step 303, implement cmp processing, so that be positioned at the material of crystal round fringesThe surface roughness of the bed of material increases;

In step 304, implement high density plasma CVD and fill in grooveAnother material layer.

[exemplary embodiment two]

Next, can complete by subsequent technique the making of whole semiconductor devices, comprise:Implement another cmp, until expose backing layer 204; Remove hard mask by etchingLayer 203 and laying 202, complete the making of fleet plough groove isolation structure; In Semiconductor substrate 200Upper formation has the photoresist layer of well region pattern, covers fleet plough groove isolation structure completely; With describedPhotoresist layer is mask, implements well region and injects to form well region in Semiconductor substrate 200; AdoptRemove described photoresist layer with cineration technics; Above the middle body of well region, form drain junctionsStructure, as example, grid structure comprises the gate dielectric, the grid that stack gradually from bottom to topMaterial layer and grid hard masking layer; Form skew clearance wall in the both sides of grid structure, and partiallyMove in the Semiconductor substrate 200 in clearance wall outside and form LDD; Form adjacent skew clearance wallSide wall, and form source/drain region in the Semiconductor substrate 200 in side wall outside; Implement stressMemory technique, the carrier mobility of lifting channel region; At top and the grid of source/drain regionSelf-aligned silicide is formed on the top of structure; In Semiconductor substrate 200, form interlayer dielectricLayer, and in interlayer dielectric layer, form contact hole, expose the top of self-aligned silicide; FillMetal (being generally tungsten) in contact hole, form connect follow-up formation interconnecting metal layer with from rightThe contact plug of eka-silicon compound; Form multiple interconnecting metal layers, conventionally adopt dual damascene processComplete; Form metal pad, the Bonding during for subsequent implementation device package.

[exemplary embodiment three]

The present invention also provides a kind of electronic installation, and it comprises according to an exemplary embodiment of the present twoMethod manufacture semiconductor devices. Described electronic installation can be mobile phone, panel computer, penRemember this computer, net book, game machine, television set, VCD, DVD, navigator, photographAny electronic product or the equipment such as machine, video camera, recording pen, MP3, MP4, PSP, alsoCan be any intermediate products that comprise described semiconductor devices. Described electronic installation, owing to makingWith described semiconductor devices, thereby there is better performance.

The present invention is illustrated by above-described embodiment, but should be understood that, above-mentionedEmbodiment is just for for example and the object of explanation, but not be intended to by the present invention be limited to describeScope of embodiments in. In addition it will be appreciated by persons skilled in the art that not office of the present inventionBe limited to above-described embodiment, can also make more kinds of modification and repair according to instruction of the present inventionChange, these variants and modifications all drop in the present invention's scope required for protection. Of the present inventionProtection domain is defined by the appended claims and equivalent scope thereof.

Claims (8)

1. a manufacture method for semiconductor devices, comprising:

Semiconductor substrate is provided, in described Semiconductor substrate, forms groove;

In described Semiconductor substrate and the sidewall of described groove and bottom deposited material layer;

Implement cmp processing, so that be positioned at the surface of the described material layer of crystal round fringesRoughness increases;

Implement high density plasma CVD and in described groove, fill another materialLayer.

2. method according to claim 1, is characterized in that, implements described chemical machineAfter tool milled processed, also comprise and implement to wipe the step of cleaning treatment, described in removing and residuing inThe granule foreign of material surface.

3. method according to claim 1, is characterized in that, described groove be forFill isolated material to form the groove of fleet plough groove isolation structure.

4. method according to claim 3, is characterized in that, form described groove itBefore, be also included in described Semiconductor substrate the step of deposit liner layer and hard mask layer successively.

5. method according to claim 4, is characterized in that, in described groove, fills outAfter filling another material layer, also comprise: implement another cmp, until described in exposingMaterial layer; Remove described hard mask layer and described laying by etching.

6. method according to claim 5, is characterized in that, described material layer is served as reasonsThe backing layer that silicon oxynitride or silica form; Described another material layer is described isolation materialThe bed of material.

7. a semiconductor devices that adopts the described method of one of claim 1-6 to manufacture.

8. an electronic installation, described electronic installation comprises semiconductor claimed in claim 7Device.