CN105577183B - A kind of double loop charge pump bandwidth self-adaption phaselocked loop - Google Patents
A kind of double loop charge pump bandwidth self-adaption phaselocked loop Download PDFInfo
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- CN105577183B CN105577183B CN201510925064.7A CN201510925064A CN105577183B CN 105577183 B CN105577183 B CN 105577183B CN 201510925064 A CN201510925064 A CN 201510925064A CN 105577183 B CN105577183 B CN 105577183B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention provides a kind of double loop charge pump bandwidth self-adaption phaselocked loop, the phaselocked loop uses even level annular voltage controlled oscillator, double loop charge pump and voltage-current converter circuit, the phaselocked loop that can realize the advantages that quick lock in, loop bandwidth and concussion frequency of phaselocked loop adaptively adjust.
Description
Technical field
The invention belongs to field of radio frequency circuit design, are related to a kind of double loop charge pump bandwidth self-adaption phaselocked loop.
Background technology
Double loop charge pump bandwidth self-adaption phaselocked loop is widely used in SerDes circuits, and clock letter is provided for SerDes
Number, to receive and transmitting provides reference clock, therefore referred to as master clock.In the SerDes systems of multi-protocols unified shader,
When asking with different input reference frequencies, and requiring the frequency of phaselocked loop and bandwidth that can adaptively adjust and minimize strong
Influence of the clock signal to other circuit modules reduces electromagnetic interference therefore, it is necessary to use spread spectrum clock module.Using double loop
Charge pump bandwidth self-adaption phaselocked loop can meet requirement of the multi-protocols unified shader SerDes systems to phaselocked loop.
Invention content
The present invention provides a kind of double loop charge pump bandwidth self-adaption phaselocked loop, and the phaselocked loop is voltage-controlled using even level annular
Oscillator, double loop charge pump and voltage-current converter circuit, the phaselocked loop can realize the quick lock in of phaselocked loop, loop bandwidth
The advantages that adaptively being adjusted with concussion frequency.
The specific technical solution of the present invention is as follows：
A kind of double loop charge pump bandwidth self-adaption phaselocked loop, is characterized in that：
Including reference clock frequency dividing/frequency multiplier M1, phase frequency detector M2, path of integration charge pump M3, proportional path charge
Pump M4, I/V converter M5, comparator M10, V/I converter M11, low-pass filter M12, VCO buffer M13, VCO M14, phase
Position selection M15 and programmable frequency divider M16；
The path of integration charge pump M3 includes sequentially connected first UP circuits M6 and the first DN circuits M7；
The proportional path charge pump M4 includes sequentially connected 2nd UP circuits M8 and the 2nd DN circuits M9；
One end of reference clock frequency dividing/frequency multiplier M1 connects input signal reference clock, and the other end connects phase frequency detector
An input terminal A of M2.
One end of the other end input terminal B connection programmable frequency dividers M16 of phase frequency detector M2；
One end of the other end connection Selecting phasing M15 of programmable frequency divider M16；
The output end C of the other end connection VCO M14 of Selecting phasing M15；
There are four output end, respectively output end UP, output end UPB, output end DN and output ends by phase frequency detector M2
DNB；One end of the first UP circuits M6 in output end UPB connection path of integration charge pumps M3, output end DN connection path of integration
One end of the first DN circuits M7 in charge pump M3, the 2nd UP circuits M8's in output end UP connection proportional path charge pumps M4
One end, one end of the 2nd DN circuits M9 in output end DNB connection proportional path charge pumps M4, the first UP circuits M6's is another
The output end VB2 connections at end, the other end of the 2nd UP circuits M8 and I/V converters M5, the other end of the first DN circuits M7, the
The output end VB1 connections of the other end and I/V converters M5 of two DN circuits M9；
The tie point of first UP circuits M6 and the first DN circuits M7 are connected to ground and output voltage VINT by capacitance C1；
The tie point of an output end of I/V converters M5, the 2nd UP circuits M8 and the 2nd DN circuits M9 passes through capacitance C2
It is connected to ground and output voltage VCTRL；
The voltage VREF and voltage VCTRL of I/V converters M5 outputs are separately input into two input terminals of comparator M10；
Voltage VCTRL is input to the ends E of VCO M14；
Another output end of comparator M10 is connected to the input terminal of V/I converters M11；
An output end of V/I converters M11 is connected to one end of low-pass filter M12 and the ends D of VCO；
The other end ICP of V/I converters M11 is connected to the input terminal H of I/V converters M5.
The other end of low-pass filter M12 is connected to the ends L of VCO buffers M13；
The ends K and the ends J of VCO buffers M13 are connected to the ends F of VCO M14, and the ends K are connected with the ends J；
The ends I of VCO buffers M13 are connected to the ends G of VCO M14.Advantages of the present invention is as follows：
A kind of double loop charge pump bandwidth self-adaption phaselocked loop provided by the invention, the phaselocked loop can realize the fast of phaselocked loop
The advantages that speed locking, loop bandwidth and concussion frequency adaptively adjust, realizes spread spectrum function by phase difference value, can reduce
Electromagnetic interference.
Description of the drawings
Fig. 1 is the circuit realization figure of the method for the present invention；
Specific implementation mode
In the following with reference to the drawings and specific embodiments, technical scheme of the present invention is clearly and completely stated.Obviously,
The embodiment stated is only a part of the embodiment of the present invention, instead of all the embodiments, based on the embodiments of the present invention,
Those skilled in the art belong to the guarantor of the present invention in the every other embodiment do not made creative work premise and obtained
Protect range.
A kind of double loop charge pump bandwidth self-adaption phaselocked loop includes reference clock frequency dividing/frequency multiplier M1, phase frequency detector
M2, path of integration charge pump M3, proportional path charge pump M4, I/V converter M5, comparator M10, V/I converter M11, low pass
The modular circuits such as filter M12, VCO buffer M13, VCO M14, Selecting phasing M15, programmable frequency divider M16.Path of integration
Charge pump M3 includes the first UP circuits M6 of charge pump and the first DN circuits M7 of charge pump.Proportional path charge pump M3 includes electricity
The 2nd DN circuits M9 of the 2nd UP circuits M8 and charge pump of lotus pump.One end connection input of reference clock frequency dividing/frequency multiplier M1
Signal reference clock, the other end connect the ends A of phase frequency detector M2.The ends the B connection programmable frequency divider M16 of phase frequency detector M2
One end.One end of the other end connection Selecting phasing M15 of programmable frequency divider M16.The other end of Selecting phasing M15 connects
The C-terminal of VCO.Phase frequency detector M2 is by four output ends, respectively UP, UPB, DN and DNB；UPB connection path of integration charge pumps
One end of first UP circuits M6 in M3, one end of the first DN circuits M7 in DN connection path of integration charge pumps M3.UP connections
One end of the 2nd UP circuits M8 in proportional path charge pump M4, the 2nd DN circuits in DNB connection proportional path charge pumps M4
One end of M9.The other end of the output end VB1 connection M7 and M9 of I/V converters M5.The output end VB2 connections of I/V converters M5
The other end of M6 and M8.The tie point of M6 and M7 exports for VINT, and VINT is connected to ground by capacitance C1.The tie point of M8 and M9
It is exported for VCTRL, VCTRL is connected to ground by capacitance C2.The ends output end VREF and M of I/V converters M5 are connected to comparator
Two input terminals of M10.The ends output VCTRL of proportional path charge pump M4 are connected with the ends M, and are connected to the ends E of VCO M14.
The output end of comparator M10 is connected to the input terminal of V/I converters M11.The other end IVCO of V/I converters M11
It is connected to one end of low-pass filter M12 and the ends D of VCO.The other end ICP of V/I converters M11 is connected to I/V converters M5
The ends H.The other end of low-pass filter M12 is connected to the ends L of VCO buffers M13.The ends K of VCO buffers M13 are connected with the ends J
To the ends F of VCO M14, the ends K are connected with the ends J.The ends I of VCO buffers M13 are connected to the ends G of VCO M14
The present invention provides a kind of double loop charge pump bandwidth self-adaption phaselocked loop, it includes phase difference value module, pass through
Spread spectrum function may be implemented in phase difference value.
The present invention provides a kind of double loop charge pump bandwidth self-adaption phaselocked loop, it includes voltage controlled oscillator, have compared with
Wide frequency coverage so that voltage controlled oscillator can be realized certainly according to the electric current of voltage controlled oscillator and the variation of reference frequency
Dynamic locking.
The present invention provides a kind of double loop charge pump bandwidth self-adaption phaselocked loop, it includes path of integration charge pump and ratio
Example path charge pump, may be implemented the quick lock in of phaselocked loop and the automatic adjustment of bandwidth, and reduce the reference spur of phaselocked loop.
Operation principle：Phase frequency detector generates a Pulse Width Control product according to the difference of reference signal and output feedback signal
Sub-path charge pump and proportional path charge pump generate control voltage a VINT and VCTRL, the production of path of integration charge pump respectively
Raw control voltage VINT adjusts the control voltage VCTRL that proportional path charge pump generates, by adjusting proportional path charge pump
With the gain of path of integration charge pump, the dynamic decay factor and loop bandwidth for adjusting phaselocked loop accelerates the locking of phaselocked loop
Speed.The concussion frequency for the control voltage VCTRL control voltage controlled oscillators that proportional path charge pump generates, proportional path charge pump
Control voltage VCTRL and I/V conversion output control the voltage VREF of generation compare, and generate a constant voltage and are converted to electricity
Stream, current loop realize the adaptive adjustment of voltage controlled oscillator concussion frequency.The output frequency of VCO passes through Selecting phasing and can
Programming frequency division device generates frequency similar in one and reference frequency.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, it will be understood by those of ordinary skill in the art that：It still can be to aforementioned each implementation
Technical solution recorded in example is modified or equivalent replacement of some of the technical features；And these modification or
It replaces, it does not separate the essence of the corresponding technical solution
The spirit and scope of various embodiments of the present invention technical solution.
Claims (1)
1. a kind of double loop charge pump bandwidth self-adaption phaselocked loop, it is characterised in that：
Including reference clock frequency dividing/frequency multiplier M1, phase frequency detector M2, path of integration charge pump M3, proportional path charge pump M4,
I/V converters M5, comparator M10, V/I converter M11, low-pass filter M12, VCO buffer M13, VCO M14, phase choosing
Select M15 and programmable frequency divider M16；
The path of integration charge pump M3 includes sequentially connected first UP circuits M6 and the first DN circuits M7；
The proportional path charge pump M4 includes sequentially connected 2nd UP circuits M8 and the 2nd DN circuits M9；
One end of reference clock frequency dividing/frequency multiplier M1 connects input signal reference clock, and the other end connects phase frequency detector M2's
One input terminal A；
One end of the other end input terminal B connection programmable frequency dividers M16 of phase frequency detector M2；
One end of the other end connection Selecting phasing M15 of programmable frequency divider M16；
The output end C of the other end connection VCO M14 of Selecting phasing M15；
There are four output end, respectively output end UP, output end UPB, output end DN and output end DNB by phase frequency detector M2；It is defeated
One end of the first UP circuits M6 in outlet UPB connection path of integration charge pumps M3, output end DN connection path of integration charge pumps
One end of the first DN circuits M7 in M3, one end of the 2nd UP circuits M8 in output end UP connection proportional path charge pumps M4,
One end of the 2nd DN circuits M9 in output end DNB connection proportional path charge pumps M4, the other end of the first UP circuits M6, second
The output end VB2 connections of the other end and I/V converters M5 of UP circuits M8, the other end, the 2nd DN electricity of the first DN circuits M7
The output end VB1 connections of the other end and I/V converters M5 of road M9；
The tie point of first UP circuits M6 and the first DN circuits M7 are connected to ground and output voltage VINT by capacitance C1；
The tie point of an output end of I/V converters M5, the 2nd UP circuits M8 and the 2nd DN circuits M9 is connected by capacitance C2
To ground and output voltage VCTRL；
The voltage VREF and voltage VCTRL of I/V converters M5 outputs are separately input into two input terminals of comparator M10；Voltage
VCTRL is input to the ends E of VCO M14；
Another output end of comparator M10 is connected to the input terminal of V/I converters M11；
An output end of V/I converters M11 is connected to one end of low-pass filter M12 and the ends D of VCO；
The other end ICP of V/I converters M11 is connected to the input terminal H of I/V converters M5；
The other end of low-pass filter M12 is connected to the ends L of VCO buffers M13；
The ends K and the ends J of VCO buffers M13 are connected to the ends F of VCO M14, and the ends K are connected with the ends J；
The ends I of VCO buffers M13 are connected to the ends G of VCO M14.
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| CN201510925064.7A CN105577183B (en) | 2015-12-11 | 2015-12-11 | A kind of double loop charge pump bandwidth self-adaption phaselocked loop |
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| CN201510925064.7A CN105577183B (en) | 2015-12-11 | 2015-12-11 | A kind of double loop charge pump bandwidth self-adaption phaselocked loop |
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| CN105577183A CN105577183A (en) | 2016-05-11 |
| CN105577183B true CN105577183B (en) | 2018-08-21 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106844253B (en) * | 2016-12-15 | 2019-07-23 | 北京时代民芯科技有限公司 | A kind of serial communication clock data recovery system of low sampling rate |
| US10141941B2 (en) * | 2016-12-30 | 2018-11-27 | Huawei Technologies Co., Ltd. | Differential PLL with charge pump chopping |
| CN109639272B (en) * | 2018-12-14 | 2023-06-09 | 北京时代民芯科技有限公司 | Self-adaptive broadband phase-locked loop circuit |
| CN112953527A (en) * | 2021-03-12 | 2021-06-11 | 中国科学院微电子研究所 | Phase-locked loop structure and electronic equipment capable of being locked quickly |
| CN114301451A (en) * | 2021-12-31 | 2022-04-08 | 合肥市芯海电子科技有限公司 | Phase-locked loop circuit, control method, charge pump and chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101366192A (en) * | 2005-09-12 | 2009-02-11 | 高通股份有限公司 | Multi-band radio frequency modulator |
| CN101414824A (en) * | 2007-10-16 | 2009-04-22 | 联发科技股份有限公司 | All-digital phase-locked loop |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7482883B2 (en) * | 2005-10-19 | 2009-01-27 | Texas Instruments Incorporated | Gain normalization of a digitally controlled oscillator in an all digital phase locked loop based transmitter |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101366192A (en) * | 2005-09-12 | 2009-02-11 | 高通股份有限公司 | Multi-band radio frequency modulator |
| CN101414824A (en) * | 2007-10-16 | 2009-04-22 | 联发科技股份有限公司 | All-digital phase-locked loop |
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Effective date of registration: 20221018 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No. 15, Jinye Second Road, Xi'an, Shaanxi 710065 Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |