CN105574053B - The compression method and device of FPGA configuration file - Google Patents
The compression method and device of FPGA configuration file Download PDFInfo
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- CN105574053B CN105574053B CN201410635537.5A CN201410635537A CN105574053B CN 105574053 B CN105574053 B CN 105574053B CN 201410635537 A CN201410635537 A CN 201410635537A CN 105574053 B CN105574053 B CN 105574053B
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Abstract
The present invention relates to a kind of compression method of FPGA configuration file and devices, which comprises receives the compression instruction that processor is sent；First configuration file of fpga chip when carrying out RTL coding, synthesis, placement-and-routing is split, multiple subfiles are generated；When there are when identical subfile, obtaining the identical value of the identical subfile and the length of the identical value in the multiple subfile, and identifier is added, the identical value, length and identifier constitute look-up table；The identical subfile in first configuration file is deleted, the look-up table and independent subfile are constituted into the independent subfile of the second configuration file.
Description
Technical field
The present invention relates to the communications field more particularly to a kind of field programmable gate array (Field
Programmable Gate Array, FPGA) configuration file compression method and device.
Background technique
When in the prior art loading FPGA configuration file, when the capacity of configuration file is larger, generally require to spend
Take the transmission that longer time carries out configuration file, the rate for causing configuration file to load is slower, to affect fpga chip
Configuration speed.
Summary of the invention
Present invention aim to address in the prior art when carrying out FPGA configuration file load, when needing to spend longer
Between carry out configuration file transmission, configuration file load rate it is slower, the slow problem of the configuration speed of fpga chip.
In a first aspect, the embodiment of the invention provides a kind of compression methods of FPGA configuration file, which comprises
Receive the compression instruction that processor is sent；
Field programmable gate array fpga chip when to progress Method at Register Transfer Level RTL coding, synthesis, placement-and-routing
The first configuration file be split, generate multiple subfiles；
When the identical value that there are when identical subfile, obtains the identical subfile in the multiple subfile and described
The length of identical value, and identifier is added, the identical value, length and identifier constitute look-up table；
The identical subfile in first configuration file is deleted, the look-up table and independent subfile are constituted second and matched
Set the independent subfile of file.
Optionally, traverse the subfile, the combining characters not occurred using in the multiple subfile as mark
Symbol.
Optionally, the first configuration file of fpga chip divides when described pair of progress RTL coding, synthesis, placement-and-routing
It cuts, generates multiple subfiles and specifically include:
First configuration file is split according to the capacity of first configuration file.
Optionally, the method also includes:
Second configuration file is loaded into fpga chip, to configure the fpga chip.
Optionally, after the method further include: decoded to second configuration file for being loaded into fpga chip, with life
At the first configuration file.
Second aspect, the embodiment of the invention provides a kind of compression set of FPGA configuration file, described device includes: to connect
Unit, cutting unit are received, acquiring unit deletes unit；
The receiving unit, for receiving the compression instruction of processor transmission；
The cutting unit is carried out for the first configuration file to FPGA when carrying out RTL coding, synthesis, placement-and-routing
Segmentation, generates multiple subfiles；
The acquiring unit, for when there are when identical subfile, obtaining the identical Ziwen in the multiple subfile
The length of the identical value of part and the identical value, and identifier is added, the identical value, length and identifier, which are constituted, to be searched
Table；
The deletion unit, for deleting the identical subfile in first configuration file, by the look-up table and list
Only son's file constitutes the second configuration file.
Optionally, the acquiring unit is specifically used for, and traverses the subfile, not occur in the multiple subfile
The combining characters crossed are as identifier.
Optionally, the cutting unit is specifically used for, and matches according to by the capacity of first configuration file to described first
File is set to be split.
The present invention is by, in load, receiving the compression instruction that processor is sent to FPGA configuration file；To progress RTL volume
The first configuration file of fpga chip is split when code, synthesis, placement-and-routing, generates multiple subfiles；When the multiple son
There are when identical subfile in file, the identical value of the identical subfile and the length of the identical value are obtained, and add
Identifier, the identical value, length and identifier constitute look-up table；The identical subfile in first configuration file is deleted,
The look-up table and independent subfile are constituted the independent subfile of the second configuration file to compress, reduce the biography of configuration file
The defeated time, so that the rate for further solving configuration file load is slower, the slow problem of the configuration speed of fpga chip.
Detailed description of the invention
Fig. 1 is the compression method flow chart for the FPGA configuration file that the embodiment of the present invention one provides；
Fig. 2 is the architecture diagram for the FPGA configuration file load that the embodiment of the present invention one provides；
Fig. 3 is the compression set schematic diagram of FPGA configuration file provided by Embodiment 2 of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In order to facilitate understanding of embodiments of the present invention, it is further explained below in conjunction with attached drawing with specific embodiment
Bright, embodiment does not constitute the restriction to the embodiment of the present invention.
The present invention is applied to scene when FPGA configuration file to be loaded into fpga chip, by FPGA configuration file into
Row compression, accelerates the loading velocity of configuration file.
Fig. 1 is the loading method flow chart for the FPGA configuration file that the embodiment of the present invention one provides.As shown in Figure 1, this reality
Apply example the following steps are included:
S110 receives the compression instruction that processor is sent.
S120 is split the first configuration file of fpga chip when carrying out RTL coding, synthesis, placement-and-routing, generates
Multiple subfiles.
Specifically, as shown in Fig. 2, Fig. 2 is the architecture diagram that FPGA configuration file of the invention loads.After compression in Fig. 2
Bit stream be the second configuration file, bit stream decoding device can also be referred to as decoder, and configuration memory can be used as
The carrier of dictionary in fpga chip.
Using electric design automation (Electronic Design Automation, EDA) tool, passing through register
Transmitting stage (register-transfer level, RTL) coding, it is comprehensive, after placement-and-routing, the first configuration file is generated, when this
When first configuration file is larger, loading speed when being loaded into fpga chip is not high, in order to reduce the size of configuration file, improves
The configuration speed of fpga chip can be handled by pressing " compression " key of eda software to processor transmission compression instruction
After device receives compression instruction, the first configuration file is compressed.
Wherein, which is our company independent research, and having on the interface of the eda tool can be triggered as described above
The key that processor is compressed.
When being compressed to the first configuration file, when can be first split to the first configuration file, to the first configuration text
When part is split, first configuration file can be split according to the capacity of the first configuration file, by the first configuration
File division is multiple subfiles.Example and it is non-limiting, the first configuration file can be divided according to mono- subfile of 8bit
It cuts, in another embodiment, the first configuration file can also be split with mono- subfile of 16bit.
S130, when there are when identical subfile, obtained in the multiple subfile the identical value of the identical subfile with
And the length of the identical value, and identifier is added, the identical value, length and identifier constitute look-up table.
Any when at least two subfiles in multiple subfiles are identical, in available at least two subfile
The identical value of subfile, and the length of the identical value is obtained, and add identifier to the length of the identical value and identical value, it should
Identical value, the length of identical value and identifier constitute look-up table.Wherein, when adding identifier, whole subfiles can be traversed,
The combining characters not occurred using in the multiple subfile are as identifier.
After identical subfile is done above-mentioned processing, for remaining independent subfile, it can be not processed.
S140 deletes the identical subfile in first configuration file, and the look-up table and independent subfile are constituted
Second configuration file.
The processing that S120-130 is carried out to the identical subfile in all subfiles, for the individual Ziwen in subfile
Part, and look-up table is together, constitutes the second configuration file.Wherein, the independent subfile is not deposit in the multiple subfile
In the subfile of identical subfile.
Optionally, after the first configuration file to fpga chip compresses, the second configuration file of generation is loaded
To fpga chip, to configure the fpga chip.
Specifically, the user equipment (User Equipment, UE) where the second configuration file is connected with fpga chip
It connects, the second configuration file is downloaded in fpga chip by downloading wire, is provided with decoder circuit inside fpga chip in advance
Or decoder circuit is connected on the expansion interface of fpga chip, decoder is decoded the second configuration file, has decoded
Cheng Hou gets the first configuration file, and according to the first configuration file, fpga chip can complete relevant configuration, for example, completing
The downloading Booting sequence of fpga chip.
Specifically, in decoding, the look-up table in the second configuration file can be first got, it is extensive by reading look-up table
Identical subfile after recovery and the independent subfile not processed are combined by identical subfile of appearing again, and generate the
One configuration file.
It should be noted that also can use the mutation of Run- Length Coding algorithm or Run- Length Coding algorithm to the first configuration file
It is compressed, generates the second configuration file.
Also mutation algorithm, the base of LZ77, LZ78, LZSS, lzw algorithm, described LZ77, LZ78, LZSS, LZW be can use
Any one in the algorithm of dictionary and sliding window compresses the first configuration file, generates the second configuration file.
Also the compression algorithm that can use statistical probability, as Shanno-Fano algorithm, huffman coding, arithmetic coding and
Similar algorithm based on the Shanno-Fano algorithm, huffman coding, arithmetic coding compresses the first configuration file,
Generate the second configuration file.
Can also algorithm and above-mentioned three classes algorithm based on the application, with the algorithm of combined in any order Cheng Xin.
By the loading method of application FPGA configuration file provided in an embodiment of the present invention, the compression that processor is sent is received
Instruction；Field programmable gate array fpga chip when to progress Method at Register Transfer Level RTL coding, synthesis, placement-and-routing
First configuration file is split, and generates multiple subfiles；When there are when identical subfile, obtaining institute in the multiple subfile
The identical value of identical subfile and the length of the identical value are stated, and adds identifier, the identical value, length and identifier
Constitute look-up table；The identical subfile in first configuration file is deleted, the look-up table and independent subfile are constituted the
Two configuration files, so that the size of configuration file significantly reduces, to reduce when configuration file is loaded into fpga chip
Load time, to increase the allocative efficiency of fpga chip.
It should be noted that also can use LZ77, LZ78, LZSS, lzw algorithm, described LZ77, LZ78, LZSS, LZW
Mutation algorithm, any one in the algorithm based on dictionary and sliding window the first configuration file is compressed, generate the
Two configuration files.
Fig. 3 is the compression set schematic diagram of FPGA configuration file provided by Embodiment 2 of the present invention.As shown in figure 3, the pressure
Compression apparatus includes: receiving unit 310, cutting unit 320, acquiring unit 330, deletion unit 340.
The receiving unit 310, for receiving the compression instruction of processor transmission；
The cutting unit 320, for carry out RTL coding, synthesis, placement-and-routing when FPGA the first configuration file into
Row segmentation, generates multiple subfiles；
The acquiring unit 330, for when there are when identical subfile, obtaining the identical son in the multiple subfile
The length of the identical value of file and the identical value, and identifier is added, the identical value, length and identifier, which are constituted, to be searched
Table；
The deletion unit 340, for deleting the identical subfile in first configuration file, by the look-up table and
Independent subfile constitutes the second configuration file.
Optionally, the acquiring unit 330 is specifically used for, and traverses the subfile, not have in the multiple subfile
The combining characters occurred are as identifier.
Optionally, the cutting unit 320 is specifically used for, according to by the capacity of first configuration file to described first
Configuration file is split.
Professional should further appreciate that, described in conjunction with the examples disclosed in the embodiments of the present disclosure
Unit and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, hard in order to clearly demonstrate
The interchangeability of part and software generally describes each exemplary composition and step according to function in the above description.
These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.
Professional technician can use different methods to achieve the described function each specific application, but this realization
It should not be considered as beyond the scope of the present invention.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can be executed with hardware, processor
The combination of software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only memory
(ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of storage medium well known to interior.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (2)
1. a kind of compression method of FPGA configuration file, which is characterized in that the described method includes:
Receive the compression instruction that processor is sent；
To the of field programmable gate array fpga chip when carrying out Method at Register Transfer Level RTL coding, synthesis, placement-and-routing
One configuration file is split according to the capacity of first configuration file, generates multiple subfiles；
When the identical value that there are when identical subfile, obtains the identical subfile in the multiple subfile and described identical
The length of value, and add identifier, the identifier be after traversing multiple subfiles, without the combining characters occurred,
The identical value, length and identifier constitute look-up table；
The identical subfile in first configuration file is deleted, the look-up table and independent subfile are constituted into the second configuration text
The independent subfile of part；
Second configuration file is loaded into fpga chip, to configure the fpga chip, and to being loaded into fpga chip
Second configuration file is decoded, and first obtains the look-up table in the second configuration file, recovers identical Ziwen by searching for table
Part, by after recovery identical subfile and the independent subfile be combined to generate the first configuration file；
The decoder is pre-configured in fpga chip, or connects the fpga chip by expansion interface.
2. a kind of compression set of FPGA configuration file is applied to the method as described in claim 1, which is characterized in that described
Device includes: receiving unit, cutting unit, acquiring unit, deletion unit；
The receiving unit, for receiving the compression instruction of processor transmission；
The cutting unit, the first configuration file of FPGA is according to when for progress RTL coding, synthesis, placement-and-routing
The capacity of first configuration file is split, and generates multiple subfiles；
The acquiring unit, for when there are when identical subfile, obtaining the identical subfile in the multiple subfile
The length of identical value and the identical value, and identifier is added, after the identifier is traverses multiple subfiles, without
The combining characters occurred, the identical value, length and identifier constitute look-up table；
The deletion unit, it is by the look-up table and individually sub for deleting the identical subfile in first configuration file
File constitutes the second configuration file；
The decoder is pre-configured in fpga chip, or connects the fpga chip by expansion interface.
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| CN108037695B (en) * | 2017-11-29 | 2020-10-27 | 深圳市紫光同创电子有限公司 | Field programmable gate array and automatic configuration method thereof |
| CN110413580B (en) * | 2019-07-31 | 2021-10-29 | 中国科学院自动化研究所 | Compression method, system and device for FPGA configuration code stream |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002099454A (en) * | 2000-09-21 | 2002-04-05 | Nec Corp | File control system and method |
| CN101149765A (en) * | 2007-11-09 | 2008-03-26 | 北京航空航天大学 | High reliability digital integrated circuit design method |
| CN101834757A (en) * | 2010-04-01 | 2010-09-15 | 深圳英飞拓科技股份有限公司 | Methods for automatically detecting topology of optical transmission monitoring networks and implementation device |
| CN102129872A (en) * | 2010-01-14 | 2011-07-20 | 珠海扬智电子有限公司 | Data compression and decompression method and device thereof |
Family Cites Families (2)
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| CN102262547A (en) * | 2010-05-31 | 2011-11-30 | 中兴通讯股份有限公司 | Method and device for loading field programmable gate array (FPGA) |
| CN103685420B (en) * | 2012-09-24 | 2017-06-27 | 华为技术有限公司 | A kind of method of media file duplication removal, server and system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002099454A (en) * | 2000-09-21 | 2002-04-05 | Nec Corp | File control system and method |
| CN101149765A (en) * | 2007-11-09 | 2008-03-26 | 北京航空航天大学 | High reliability digital integrated circuit design method |
| CN102129872A (en) * | 2010-01-14 | 2011-07-20 | 珠海扬智电子有限公司 | Data compression and decompression method and device thereof |
| CN101834757A (en) * | 2010-04-01 | 2010-09-15 | 深圳英飞拓科技股份有限公司 | Methods for automatically detecting topology of optical transmission monitoring networks and implementation device |
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