CN105553850A - URL blocking method based on FPGA and TCAM - Google Patents

Abstract

The invention discloses a URL blocking method based on an FPGA and a TCAM, and relates to an information blocking method. The method employs a Hash algorithm to compress an URL keyword with combining with TCAM matching, and can meet the requirements for the URL blocking at a large-flow line speed.

Description

A kind of URL method for blocking based on FPGA and TCAM

Technical field

The present invention relates to a kind of information method for blocking, particularly relate to a kind of URL method for blocking based on FPGA and TCAM.

Background technology

Namely URL (UniformResourceLocator, URL(uniform resource locator)) shutoff limits the access of some specific URL.URL storehouse is set up in traditional URL shutoff, directly compares coupling to specific url field, for subsequent treatment such as the message that the match is successful abandon, is mainly used in the Software Development Platforms such as CPU/GPU/ network processing unit.Prior art mates shutoff to URL can only reach the handling property of tens k to hundreds of kPPS on single CPU/GPU/ network processing unit, and backbone network 10G port just needs the handling property reaching 14.4Mpps, the URL that prior art cannot meet under large discharge linear speed mates shutoff requirement.

Summary of the invention

Because the above-mentioned defect of prior art, technical problem to be solved by this invention is to provide a kind of URL method for blocking met under large discharge linear speed.

For achieving the above object, the invention provides a kind of URL method for blocking based on FPGA and TCAM, carry out according to the following steps:

S1, while FPGA internal clocking process buffer memory message, the critical field of URL extracting message is compressed in parallel through hash algorithm;

S2, to compress according to same hash algorithm preparing the url field of shutoff in TCAM, and write in TCAM as shutoff strategy;

S3, the packed field obtained by step S1 do content matching at TCAM; The dropping packets when content matching; Otherwise normally forward.

The invention has the beneficial effects as follows: the present invention can abandon the message needing shutoff immediately when message does surface speed forwarding by buffer memory to subordinate's processing module, can meet 10G even 100G port to the requirement of Message processing speed, reach the line-speed processing to message at individual equipment/platform.

Accompanying drawing explanation

Fig. 1 is the schematic flow sheet of the present invention one specific embodiment.

Embodiment

Below in conjunction with drawings and Examples, the invention will be further described:

As shown in Figure 1, a kind of based on FPGA (Field-ProgrammableGateArray, field programmable gate array) and TCAM (ternarycontentaddressablememory, TCAM) URL method for blocking, it is characterized in that carrying out according to the following steps:

S1, while FPGA internal clocking process buffer memory message, extract that the url field of message is parallel carries out Hash compression algorithm to calculate PktUrlCalResult;

S2, in TCAM, calculate to preparing the url field of shutoff the URLResult needing shutoff according to same hash algorithm, and write in TCAM as shutoff strategy;

S3, PktUrlCalResult is done content matching at TCAM, judge that whether it is identical; The dropping packets when content matching; Otherwise normally forward.

More than describe preferred embodiment of the present invention in detail.Should be appreciated that those of ordinary skill in the art just design according to the present invention can make many modifications and variations without the need to creative work.Therefore, all technical staff in the art, all should by the determined protection range of claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.

Claims (1)

1. based on a URL method for blocking of FPGA and TCAM, it is characterized in that, carry out according to the following steps:

S1, while FPGA internal clocking process buffer memory message, the critical field of URL extracting message is compressed in parallel through hash algorithm;

S2, to compress according to same hash algorithm preparing the url field of shutoff in TCAM, and write in TCAM as shutoff strategy;

S3, the packed field obtained by step S1 do content matching at TCAM; The dropping packets when content matching; Otherwise normally forward.