CN105553804A - Variable-rate 1553B protocol processor circuit and method - Google Patents

Abstract

The invention relates to a variable-rate 1553B protocol processor circuit and a method. the circuit comprises a clock frequency multiplication circuit, a 1553B protocol processing circuit and a configuration module, wherein the configuration module configures and outputs a clock frequency amplification factor N to the clock frequency multiplication circuit; the clock frequency multiplication circuit receives a clock signal CLK_IN with a fixed frequency, a multiplication clock signal with a frequency of N*CLK is generated, and the signal is sent to the 1553B protocol processing circuit; and the CLK is an input clock needed by the 1553B protocol processing circuit at a 1MHz bus baud rate. Through configuring a clock input mode for the 1553B protocol processor, a 1553 bus communication rate at a different rate is realized, and the purposes of enhancing the communication efficiency and reducing the average communication delay can be achieved.

Description

A kind of variable bit rate 1553B protocol processor circuit and method

Technical field

The invention belongs to computer communication technology field, relate to a kind of variable bit rate 1553B protocol processor circuit and method.

Background technology

MIL-STD-1553, full name is " interior of aircraft time-devision system instruction/response type multiplex data bus " is the STD bus that USAF electronic system is networked.It proposes for adapting to industrial and military needs, has very high reliability and flexibility.MIL-STD-1553 agreement is jointly released by US military and government for 1973, forms most initial version A, and start to be applied to the F-16 fighter plane of US military and novel attack helicopter AH-64A in 1975.Within 1978, this agreement develops into B version, and this agreement is fixed on B version by U.S. government simultaneously, and namely MIL-STD-1553B, uses till today always.China has issued national military standard GJB289A-97 (digital time-devision system instruction/response type multiplex data bus) on November 5th, 1997, and through Commission of Science, Technology and Industry for National Defence's approval, on May 1st, 1998 plays enforcement.This standard has been successfully applied in domestic various aircraft development project.Current MIL-STD-1553B has been widely used in military affairs, industry and sciemtifec and technical sphere, it is had to apply from LPX, space depot, various fighter plane, bomber, helicopter, it is even for guided missile system, and is used as the basic communication agreement between aircraft and guided missile.

At present, according to the regulation of MIL-STD-1553B/GJB289A-97 standard, the baud rate of 1553B bus is fixed as 1Mbps.And along with the development of technology, the function of avionics system is day by day complicated, and performance is become stronger day by day, and the baud rate of 1553B bus 1Mbps can not meet the requirement of system to bus communication bandwidth.

In current avionics system, there is multiple demand to the baud rate of 1553B bus system, such as: traditional 1Mbps and 2Mbps, 4Mbps etc. at a high speed.And the 1553B bus protocol processor IP of current maturation is commonly and meets 1Mbps baud rate and design.

For these existing issues, for meeting avionics system flexibly to the multiple rate requirement of 1553B bus, the current ripe 1553B bus protocol processor IP of concurrent multiplexing, proposes a kind of variable bit rate 1553B protocol processor circuit methods.

Summary of the invention

The invention provides a kind of variable bit rate 1553B protocol processor circuit methods, this circuit meets avionics system flexibly to the multiple rate requirement of 1553B bus, the current ripe 1553B bus protocol processor IP of concurrent multiplexing, make the 1553 bus communication speed realizing different rates, reach increase communication efficiency, reduce the object that average communication postpones.

Technical scheme of the present invention:

A kind of variable bit rate 1553B protocol treatment circuit, comprises clock multiplier circuit, 1553B protocol treatment circuit and configuration module,

Described configuration module is to clock multiplier circuit configuration output clock frequency multiplication factor N;

Clock signal clk _ IN that clock multiplier circuit receive frequency is fixing, producing frequency is the frequency multiplied clock signal of N*CLK, sends to 1553B protocol treatment circuit; Wherein CLK is under 1MHz bus baud rate, the input clock that 1553B protocol treatment circuit needs.

Clock multiplier circuit produces reset signal after configuration module has configured.

A kind of variable bit rate 1553B protocol processes method, step is as follows:

The multiplication factor N of step 1, configuration module setting output clock frequency, wherein N=1,2,3

Step 2, clock multiplier circuit produce frequency multiplied clock signal, and the frequency of frequency multiplied clock signal is N*CLK, and wherein CLK is under 1MHz bus baud rate, the input clock that 1553B protocol processor needs;

Step 3) under 1553B protocol treatment circuit is operated in the baud rate of NMHz.

Step 1) and step 2) between also have reset process:

Clock multiplier circuit produces reset signal, makes 1553B protocol treatment circuit be in reset mode.

Step 2) and step 4) cancel reset process in addition:

After frequency multiplied clock signal is stable, clock multiplier circuit sends the invalid instruction of reset signal, makes 1553B protocol treatment circuit be in normal operating conditions.

The advantageous effect that the present invention has:

The invention provides a kind of variable bit rate 1553B protocol treatment circuit and method, make to meet avionics system flexibly to the multiple rate requirement of 1553B bus, be easy to multiplexing current ripe 1553B bus protocol processor IP simultaneously, increase 1553B bandwidth, reduce communication delay.

Accompanying drawing explanation

Fig. 1 is electrical block diagram of the present invention;

Fig. 2 is flow chart of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is stated clearly and completely.Obviously; the embodiment stated is only the present invention's part embodiment, instead of whole embodiments, based on the embodiment in the present invention; the every other embodiment that those skilled in the art are not making creative work prerequisite and obtain, all belongs to protection scope of the present invention.

As shown in Figure 1, a kind of variable bit rate 1553B protocol treatment circuit, comprises clock multiplier circuit, 1553B protocol treatment circuit and configuration module, and configuration module is to clock multiplier circuit configuration output clock frequency multiplication factor N; Clock signal clk _ IN that clock multiplier circuit receive frequency is fixing, producing frequency is the frequency multiplied clock signal of N*CLK, sends to 1553B protocol treatment circuit; Wherein CLK is under 1MHz bus baud rate, the input clock that 1553B protocol treatment circuit needs.Clock multiplier circuit produces reset signal after configuration module has configured.

With reference to Fig. 2, the invention provides a kind of variable bit rate 1553B protocol processor circuit methods, step is as follows:

Step 1, variable bit rate 1553B protocol processor circuit are made up of clock multiplier circuit and 1553B protocol treatment circuit two parts.

Step 2, " clock multiplier circuit " can pass through software set output clock frequency, make clock multiplier circuit output clock frequency be that N takes advantage of and CLK, wherein N=1,2,3 CLK is under 1MHz bus baud rate, the clock that 1553B protocol processor needs.

Step 3, cancel the effective status of " clock multiplier circuit " reset signal.

Step 4, wait for that the output clock of " clock multiplier circuit " is stable after, the reset of " 1553B protocol treatment circuit " just cancels effective status.

Under step 5, " 1553B protocol treatment circuit " are operated in and expect baud rate.

Finally it should be noted that above embodiment only in order to technical scheme of the present invention to be described, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that; It still can be modified to the technical scheme that foregoing embodiments is recorded, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.

Claims (5)

1. a variable bit rate 1553B protocol treatment circuit, comprises clock multiplier circuit, 1553B protocol treatment circuit and configuration module,

Described configuration module is to clock multiplier circuit configuration output clock frequency multiplication factor N;

Clock signal clk _ IN that clock multiplier circuit receive frequency is fixing, producing frequency is the frequency multiplied clock signal of N*CLK, sends to 1553B protocol treatment circuit; Wherein CLK is under 1MHz bus baud rate, the input clock that 1553B protocol treatment circuit needs.

2. variable bit rate 1553B protocol treatment circuit according to claim 1, is characterized in that: clock multiplier circuit produces reset signal after configuration module has configured.

3. a variable bit rate 1553B protocol processes method, step is as follows:

Step 1) the multiplication factor N of configuration module setting output clock frequency, wherein N=1,2,3

Step 2) clock multiplier circuit generation frequency multiplied clock signal, the frequency of frequency multiplied clock signal is N*CLK, and wherein CLK is under 1MHz bus baud rate, the input clock that 1553B protocol processor needs;

Step 3) under 1553B protocol treatment circuit is operated in the baud rate of NMHz.

4. variable bit rate 1553B protocol processes method according to claim 3, is characterized in that: step 1) and step 2) between also have reset process:

Clock multiplier circuit produces reset signal, makes 1553B protocol treatment circuit be in reset mode.

5. variable bit rate 1553B protocol processes method according to claim 4, is characterized in that: step 2) and step 4) cancel reset process in addition:

After frequency multiplied clock signal is stable, clock multiplier circuit sends the invalid instruction of reset signal, makes 1553B protocol treatment circuit be in normal operating conditions.