CN105550445B - A kind of virtual verification method based on codec chip - Google Patents

A kind of virtual verification method based on codec chip Download PDF

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Publication number
CN105550445B
CN105550445B CN201510931048.9A CN201510931048A CN105550445B CN 105550445 B CN105550445 B CN 105550445B CN 201510931048 A CN201510931048 A CN 201510931048A CN 105550445 B CN105550445 B CN 105550445B
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models
chip
video
verification
audio
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CN105550445A (en
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马超
许宏杰
安博锋
陈威宇
卢俊
王婷
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Xian Aeronautics Computing Technique Research Institute of AVIC
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Xian Aeronautics Computing Technique Research Institute of AVIC
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

The present invention relates to a kind of virtual verification methods based on codec chip, hardware logic functional development means are used first, complete each functions of modules model development for meeting protocol requirement, functional requirement and performance requirement, again using the means of classification verification, the verification that each module meets each module of protocol requirement, functional requirement and performance requirement is completed.The present invention can in time, accurately have found the mistake and defect of chip design process, it is provided comprehensively, fast and accurately verify for change in design, the optimization of codec chip, the correctness of guarantee chip functions, performance, the risk for reducing chip flow failure, solves the problems, such as that audio/video decoding chip checking coverage rate is low.

Description

A kind of virtual verification method based on codec chip
Technical field
The invention belongs to IC design technologies, are related to a kind of virtual verification method based on codec chip.
Background technology
Audio/video information has the characteristics that intuitive, efficient, is widely used to the network media, DTV, satellite at present The fields such as transmission, but audio/video information data volume is huge, is often compressed before being transmitted using special algorithm, is then connecing Receiving end is decoded data.
H.264/AVC decoding chip of the present invention be it is a be integrated with embeded processor, host pci interface, H.264/AVC video decoding core, MPEG-2/4AAC audio decoders core, DDR2 memory interfaces, dma controller, Ethernet are whole The system on chip of the resources such as end, IDE record interfaces, be a intelligence, generalization, miniaturization meet real-time high-definition decoding work( The video and audio processing chip of energy.Chip functions module is numerous, in large scale, application scenarios are complicated, is brought very to verification work Big challenge.
Invention content
It is an object of the present invention to provide one kind may be implemented to each functions of modules of chip, interface sequence, system function and performance The virtual verification system design based on codec chip of verification, to find and solve the mistake occurred in codec chip design Accidentally and defect, verified respectively from subjective aspect and objective aspects, have accurate positioning, debugging flexibly, intuitive display and Verify the full feature of covering surface.
The technical scheme is that:
A kind of virtual verification method based on codec chip, includes the following steps:
Step 1:Develop validation test model
1.1) it uses simulation validation tool to build system verification platform, develops chip functions model;The simulating, verifying work Tool includes NCsim and/or QuestaSim, and the chip functions model includes GPIO models, UART models, VIC models, ETH moulds Type, ASRAM models, SSRAM models, IDE models, I2C models, DDR2 models, PCI models, VOC models, I2S models and STREAM models;
1.2) C language model of the exploitation with chip video codec functions;
Step 2:Each functions of modules verification
2.1) the actual working environment of codec chip is simulated, to the GPIO models, UART models, VIC models, ETH Model, ASRAM models, SSRAM models, IDE models, I2C models, DDR2 models, PCI models, VOC models, I2S models and STREAM models are verified;
2.2) circuit state of all subelements of C language model, judges when observing, monitor and preserve codec chip work Whether each subelement function of codec chip correct, if function is incorrect, to C language model modify circuit, add or repair It copies functional verification item, repeats this step and be transferred to step 3 if functional verification result is correct;
Step 3:Audio/video flow input verification
3.1) audio and video are inputted in coding/decoding system and verify source, export and preserve;
3.2) audio and video are inputted in C language model and verify source, export and preserve;
3.3) coding/decoding system is compared with the output of C language model, when as a result inconsistent, provides actual value respectively And desired value, return to step 1;
Audio and video verification source include a variety of typical cases meet H.264/AVC standard, MainProfile compression video Source, meet MPEG-2/4 all compression algorithms compression audio-source;
Step 4:Format conversion Correctness checking is carried out to the video data after chip encoding and decoding, format conversion is incorrect When, return to step 1;Format conversion is correct, terminates verification;The format conversion correctness refers to the video data symbol of chip output Close industry general computer standard or television system format.
Above-mentioned steps 4 may also include:The decoded video data of eye-observation chip is regarded from the angle subjective judgement of vision Frequently decoded correctness.
Beneficial effects of the present invention:
1, the present invention can in time, accurately have found the mistake and defect of chip design process, for setting for codec chip Meter change, optimization provide comprehensively, verify fast and accurately, ensure chip functions, performance correctness, reduce chip flow lose The risk lost.
2, the present invention uses hardware logic functional development means, completion to meet protocol requirement, functional requirement and performance requirement Each functions of modules model development.
3, the present invention is completed each module and is met protocol requirement, functional requirement and performance requirement using the means of classification verification Each module verification, solve the problems, such as that audio/video decoding chip checking coverage rate is low.
4, the present invention using comply with standard, the input that a plurality of types of audio-video sources are verified as system, and pass through result It compares, completes whether encoding and decoding audio and video data correctly judges;If it is necessary, being listened to audio and video using eye-observation, human ear As a result carry out subjective judgement, the technical problem of location of mistake difficulty, for decoding chip change in design, optimization provide it is comprehensive, fast Speed and accurately verification.
Description of the drawings
Fig. 1 is system schematic used in the virtual verification method based on codec chip;
Fig. 2 is the virtual verification method flow chart the present invention is based on codec chip.
Specific implementation mode
The present invention (realizes defined in H.264/AVC standard for the system function virtual verification method of codec chip The HD video encoding and decoding for meeting MainProfile, MPEG-2/4AAC audio coding decodings), include the following steps:
Step 1:Conclude exploitation validation test model and use-case
System verification platform, exploitation chip functions model (packet are built using simulation validation tool (NCsim, QuestaSim) Include GPIO models, UART models, VIC models, ETH models, ASRAM models, SSRAM models, IDE models, I2C models, DDR2 Model, PCI models, VOC models, I2S models and STREAM models);
Develop the pressure that a variety of typical cases meet the H.264/AVC compressed video source of standard MainProfile, meet MPEG-2/4 Contracting audio-source is used as verification to encourage, and verification excitation covers all compressions of H.264/AVC standard MainProfile and MPEG-2/4 Algorithm;
Develop the C language model of chip video codec functions.
Step 2:Each functions of modules verification
The actual working environment of codec chip is simulated, to the expansion of above-mentioned use-case for the verification work of each function module Make;It specifically includes:
The circuit state for observing, monitoring and preserve all subelements when codec chip work, judges that codec chip is each Whether subelement function is correct, if function is incorrect, according to functional verification results modification circuit, and addition or repairerment functional verification item And return to step 1 is transferred to step 3 if functional verification result is correct;
Step 3:Audio/video flow input verification
Audio and video to be developed in codec chip input step 1 verify excitation, export and preserve;Then in C language The audio and video verification source developed in input step 1 in model, exports and preserves;If the verification result of C language model is incorrect, Then return to step 1 adjusts the C language model of chip video codec functions;
Finally the output of codec chip and C language model is compared, when as a result inconsistent, provides actual value respectively And desired value, return to step 1;As a result consistent, then carry out step 4;
Step 4:Format conversion Correctness checking is carried out to the video data after chip encoding and decoding, it is ensured that chip output regards The general computer standard of frequency data fit industry or television system format, if format conversion is incorrect, return to step 1.
When necessary, the decoded video data of eye-observation chip also can be used in step 4, from the angle subjective judgement of vision The decoded correctness of video.

Claims (2)

1. a kind of virtual verification method based on codec chip, it is characterised in that:Include the following steps:
Step 1:Develop validation test model
1.1) it uses simulation validation tool to build system verification platform, develops chip functions model;The simulation validation tool packet Include NCsim and/or QuestaSim, the chip functions model include GPIO models, UART models, VIC models, ETH models, ASRAM models, SSRAM models, IDE models, I2C models, DDR2 models, PCI models, VOC models, I2S models and STREAM Model;
1.2) C language model of the exploitation with chip video codec functions;
Step 2:Each functions of modules verification
2.1) simulate the actual working environment of codec chip, to the GPIO models, UART models, VIC models, ETH models, ASRAM models, SSRAM models, IDE models, I2C models, DDR2 models, PCI models, VOC models, I2S models and STREAM Model is verified;
2.2) circuit state of all subelements of C language model when observing, monitor and preserve codec chip work, judges to compile solution Code each subelement function of chip it is whether correct, if function is incorrect, to C language model modify circuit, addition or repair work( It is able to verify that item, repeats this step and be transferred to step 3 if functional verification result is correct;
Step 3:Audio/video flow input verification
3.1) audio and video are inputted in coding/decoding system and verify source, export and preserve;
3.2) audio and video are inputted in C language model and verify source, export and preserve;
3.3) coding/decoding system is compared with the output of C language model, when as a result inconsistent, provides actual value and phase respectively Prestige value, return to step 1;
Audio and video verification source includes that a variety of typical cases meet H.264/AVC standard, the compressed video source of MainProfile, symbol Close the compression audio-source of all compression algorithms of MPEG-2/4;
Step 4:Format conversion Correctness checking is carried out to the video data after chip encoding and decoding, the format conversion correctness is The video data for referring to chip output meets the general computer standard of industry or television system format.
2. the virtual verification method based on codec chip according to claim 1, it is characterised in that:Step 4 further includes:People The eye observation decoded video data of chip, from the decoded correctness of angle subjective judgement video of vision.
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CN113766216A (en) * 2021-09-08 2021-12-07 北京爱芯科技有限公司 Verification method and verification system for video module

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101064629A (en) * 2006-04-26 2007-10-31 英业达股份有限公司 System for realizing virtual remote equipment and its method
CN101499937A (en) * 2009-03-16 2009-08-05 盛科网络(苏州)有限公司 Software and hardware collaborative simulation verification system and method based on FPGA
CN103530166A (en) * 2013-09-26 2014-01-22 中国航天科工集团第三研究院第八三五七研究所 Verification platform and verification method for multi-channel chip based on virtual RAM
CN103763214A (en) * 2014-01-10 2014-04-30 迈普通信技术股份有限公司 Chip array compression verification method
CN104717052A (en) * 2014-12-09 2015-06-17 中国航空工业集团公司第六三一研究所 Virtual verification system and method based on AFDX network switch chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1392913B1 (en) * 2008-12-30 2012-04-02 St Microelectronics Srl METHOD FOR IMPLEMENTING VARIATIONS OF THE FUNCTIONALITY OF A PROJECT LAYOUT OF AN INTEGRATED DEVICE, IN PARTICULAR A SINGLE CHIP OR SYSTEM-ON-CHIP SYSTEM USING FILLING CELLS PROGRAMMABLE THROUGH THE MASK

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101064629A (en) * 2006-04-26 2007-10-31 英业达股份有限公司 System for realizing virtual remote equipment and its method
CN101499937A (en) * 2009-03-16 2009-08-05 盛科网络(苏州)有限公司 Software and hardware collaborative simulation verification system and method based on FPGA
CN103530166A (en) * 2013-09-26 2014-01-22 中国航天科工集团第三研究院第八三五七研究所 Verification platform and verification method for multi-channel chip based on virtual RAM
CN103763214A (en) * 2014-01-10 2014-04-30 迈普通信技术股份有限公司 Chip array compression verification method
CN104717052A (en) * 2014-12-09 2015-06-17 中国航空工业集团公司第六三一研究所 Virtual verification system and method based on AFDX network switch chip

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