CN105529360B - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN105529360B CN105529360B CN201410522582.XA CN201410522582A CN105529360B CN 105529360 B CN105529360 B CN 105529360B CN 201410522582 A CN201410522582 A CN 201410522582A CN 105529360 B CN105529360 B CN 105529360B
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Abstract
A kind of semiconductor devices and forming method thereof.Wherein the forming method of the semiconductor devices includes: offer silicon-on-insulator, and the silicon-on-insulator successively includes substrate, insulating layer and top silicon layer；Gate structure is formed on the top silicon layer；Side wall is formed in the gate structure two sides；Semiconductor layer is formed on the top silicon layer of the side wall two sides；Ion is injected to the top silicon layer below the semiconductor layer and the semiconductor layer, until forming heavily doped region；After ion implantation, the side wall is removed with the top silicon layer below the exposure side wall；The semiconductor layer of top silicon layer and at least partly thickness to the exposure carries out that ion implantation technology is lightly doped；It is described ion implantation technology is lightly doped after, carry out annealing process.The performance of semiconductor device that the forming method is formed improves.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
With the development of semiconductor technology, the integrated level of integrated circuit is higher and higher, and the characteristic size (CD) of device is more next
It is smaller.When the feature size downsizing of device is to deep-submicron (0.25 micron hereinafter referred to as deep-submicron), the leakage current of device increases
Add, drain-induced barrier reduces (Drain induction barrier lower, DIBL) effect and short-channel effect
(SCE) etc. it is more and more obvious, becomes the main problem that the needs of device dimensions shrink overcome.
FDSOI (Fully Depleted Silicon On Insulator, fully- depleted insulation with the channel that undopes
Silicon on body) semiconductor devices (hereinafter referred to as FD device) of structure can overcome the problems, such as that device dimensions shrink bring is various,
Specific advantage are as follows: 1) since with ultra-shallow junctions, FD device can inhibit leakage current, control SCE effect；2) not due to channel
The random fluctuation of doping is adulterated and eliminates, therefore the mutability of FD device is very low；3) since FD device is to use buried oxide layer
It is completely isolated with body substrate, therefore the error rate of FD device is very low；4) since the source/drain of FD device is usually to dock heavy insulation
Body (such as buried oxide layer in FDSOI), therefore the junction capacity of FD device is very low.
A variety of FD device architectures have been developed in the prior art, such as FinFET (Fin Field-effect
Transistor, fin field-effect transistor), 3 grid structures, nano wire and ETSOI (Extremely Thin Silicon On
Insulator, silicon on ultrathin insulating body).
Although every kind of device architecture has the special advantage and challenge of its own, ETSOI especially draws because of its planar structure
People is note that it keeps ETSOI and mainstream plane CMOS manufacturing process completely compatible.It is quantized with fin number with device widths
FinFET is different, and ETSOI can have the width of any requirement.In addition, ETSOI is completely depleted, without floater effect.Knot
Fruit, ETSOI circuit can actually be similar to conventional body silicon circuit and design like that, therefore be able to achieve from bulk silicon technology to ETSOI
Seamless design migration.Finally, when ultra-thin buried oxide layer (UTBOX) is used together with ETSOI, additional device adjustment and
Power management is available to add reverse bias at dopant and/or substrate to realize.
However, the performance of semiconductor device formed on silicon on existing ultrathin insulating body is bad.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, to improve the property of semiconductor devices
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising:
Silicon-on-insulator is provided, the silicon-on-insulator successively includes substrate, insulating layer and top silicon layer；
Gate structure is formed on the top silicon layer；
Side wall is formed in the gate structure two sides；
Semiconductor layer is formed on the top silicon layer of the side wall two sides；
Ion is injected to the top silicon layer below the semiconductor layer and the semiconductor layer, until forming heavily doped region；
After ion implantation, the side wall is removed with the top silicon layer below the exposure side wall；
The semiconductor layer of top silicon layer and at least partly thickness to the exposure carries out that ion implantation technology is lightly doped；
It is described ion implantation technology is lightly doped after, carry out annealing process.
Optionally, the annealing region of the annealing process be 400 DEG C~800 DEG C, annealing time range be 10min~
180min。
Optionally, it is described be lightly doped ion that ion implantation technology is injected be phosphonium ion and arsenic ion at least within it
One, the doping concentration range of the ion is 1E14atom/cm2~1E16atom/cm2, the Implantation Energy range of the ion is
100eV~5KeV.
Optionally, it is described be lightly doped ion that ion implantation technology is injected be boron ion and indium ion at least within it
One, the doping concentration range of the ion is 1E14atom/cm2~1E16atom/cm2, the Implantation Energy range of the ion is
100eV~5KeV.
Optionally, the semiconductor layer is formed on the top silicon layer using epitaxial growth method.
Optionally, after removing the side wall, to the semiconductor layer of exposed top silicon layer and at least partly thickness into
Row metalization processing, until forming metal silicide layer.
Optionally, the metal silicide layer thickness being formed in the semiconductor layer is described more than or equal to being formed in
Push up silicon layer in the metal silicide thickness, be formed in it is described top silicon layer in the metal silicide layer thickness be greater than or
Equal to the top silicon layer thickness.
Optionally, the thickness range of the semiconductor layer is
Optionally, the thickness range of the top silicon layer is
Optionally, the thickness range of the side wall is
Optionally, after forming gate structure on the top silicon layer, and the side wall is formed in the gate structure two sides
Before, further include the steps that forming biasing side wall in the gate structure two sides；The ion implantation technology that is lightly doped is with described
It biases side wall and the gate structure is mask；The annealing process makes to remove to be formed partially in the top silicon layer exposed after side wall
Analyse lightly doped district.
To solve the above problems, the present invention also provides a kind of semiconductor devices, comprising:
Silicon-on-insulator, the silicon-on-insulator successively include substrate, insulating layer and top silicon layer；
Gate structure on the top silicon layer；
Further include:
Semiconductor layer on the silicon layer of gate structure two sides top, between the semiconductor layer and the gate structure
With gap；
The heavily doped region in the top silicon layer below the semiconductor layer is neutralized positioned at the semiconductor layer；
Top silicon layer below the gap neutralizes the lightly doped district in at least partly described semiconductor layer.
Optionally, the thickness range of the semiconductor layer is
Optionally, the thickness range of the top silicon layer is
Optionally, the width range in the gap is
It optionally, further include the metal pushed up in at least partly described semiconductor layer of silicon layer neutralization being located at below the gap
Silicide layer.
Optionally, the gate structure two sides also have biasing side wall, also have in the top silicon layer below the gap inclined
Analyse lightly doped district.
Compared with prior art, technical solution of the present invention has the advantage that
In technical solution of the present invention, first form gate structure on the top silicon layer of silicon on insulator, then and without
Ion implantation technology is lightly doped, but forms side wall in the gate structure two sides, and on the top silicon layer of the side wall two sides
Form semiconductor layer, the backward semiconductor layer and the semiconductor layer below top silicon layer inject ion, until being formed heavy
Doped region removes the side wall with the top silicon layer below the exposure side wall, at this point, again to the exposure after ion implantation
Top silicon layer and the semiconductor layer of at least partly thickness carry out that ion implantation technology is lightly doped, and carry out annealing process, from
And form semiconductor devices.The forming method is by the formation process of heavily doped region and ion implantation technology is lightly doped relatively is adjusted to
It is formed after semiconductor layer, accordingly it is possible to prevent the top silicon layer of crystal structure is amorphous before forming semiconductor layer, thus
Guarantee that semiconductor layer is smoothly formed, to improve the performance for the semiconductor devices being ultimately formed.
Further, the thickness range of side wall isTop silicon layer immediately below side wall, which is subsequently used for being formed, gently to be mixed
Miscellaneous area, and the top silicon layer of side wall two sides is subsequently used for forming heavily doped region, therefore, the thickness effect of side wall is subsequently formed heavily doped
Miscellaneous area while influencing the width range of lightly doped district to the distance of channel region.As it can be seen that the thickness of side wall is an important size
Factor.If the thickness range of side wall is greater thanThen the distance of heavily doped region to channel region is too big, to semiconductor devices
Performance has an adverse effect.If the thickness range of side wall is less thanThen the width of lightly doped district is too small, equally half-and-half leads
The performance of body device has an adverse effect.
Detailed description of the invention
Fig. 1 to Fig. 3 is the corresponding structural schematic diagram of each step of forming method of existing semiconductor devices；
Fig. 4 to Figure 13 is that the corresponding structure of each step of forming method of semiconductor devices provided by the embodiment of the present invention is shown
It is intended to.
Specific embodiment
As described in background, the performance of semiconductor device formed on silicon on existing ultrathin insulating body is bad.Ultra-thin
The existing method that semiconductor devices is formed on silicon-on-insulator is as shown in Figure 1 to Figure 3.
Referring to FIG. 1, provide including substrate (not shown), insulating layer (not shown) and the silicon-on-insulator for pushing up silicon layer 100,
And gate structure (not marking) is formed on the silicon layer 100 of top, the gate structure generally includes gate dielectric layer (not marking) and grid
Pole (does not mark).There can also be mask layer (not marking) at the top of the gate structure.The side of the gate structure and described
The side of mask layer is covered by biasing side wall 120.And it is located in the top silicon layer 100 of the gate structure two sides, it will usually in shape
It after biasing side wall 120, carries out that ion implantation technology (LDD, that is, lightly doped drain injection technology) is lightly doped, to be formed light
Doped region 110.
Referring to FIG. 2, forming semiconductor layer 130 on the top silicon layer 100 of biasing 120 two sides of side wall, and semiconductor layer
130 are formed in 110 top of lightly doped district.
Referring to FIG. 3, forming side wall 140 in the side of the gate structure and the side of the mask layer, side wall 140 covers
Lid biasing side wall 120, and semiconductor substrate 130 shown in covering part Fig. 2, are then mask with side wall 140, to not by side wall
The semiconductor substrate 130 of 140 coverings carries out ion implanting, forms heavily doped region 130a.
However, when forming semiconductor layer 130 in Fig. 2, encountering difficulty in above-mentioned existing method.Originally, it usually partly led
Body layer 130 needs to be formed using epitaxial growth method, however, before the formation of semiconductor substrate 130, first carried out being lightly doped from
Sub- injection technology forms lightly doped district 110, and ion implantation technology, which is lightly doped, can make the silicon crystal in doped region 110 by amorphous
Change (amorphized), and amorphous silicon surfaces substantially can not epitaxially grown silicon single crystalline layer (i.e. semiconductor layer 130).
For this purpose, the present invention provides a kind of forming method of new semiconductor devices, forming method silicon on insulator
Top silicon layer on form gate structure, and without ion implantation technology is lightly doped, but formed in the gate structure two sides
Side wall, and form semiconductor layer on the top silicon layer of the side wall two sides, the backward semiconductor layer and the semiconductor layer
The top silicon layer of lower section injects ion, until forming heavily doped region removes the side wall after ion implantation with the exposure side wall
The top silicon layer of lower section, at this point, the semiconductor layer of the top silicon layer of the exposure and at least partly thickness is lightly doped again
Ion implantation technology, and annealing process is carried out, to form semiconductor devices.The forming method is by the formation work of heavily doped region
It skill and ion implantation technology is lightly doped relatively is adjusted to be formed after semiconductor layer, accordingly it is possible to prevent the top silicon layer of crystal structure
It is amorphous before forming semiconductor layer, to guarantee that semiconductor layer is smoothly formed, to improve partly leading of being ultimately formed
The performance of body device.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
The embodiment of the present invention provides a kind of forming method of semiconductor devices, incorporated by reference to reference Fig. 4 to Figure 13.
Referring to FIG. 4, provide silicon-on-insulator (SOI is not marked), the silicon-on-insulator successively include substrate 201, absolutely
Edge layer 202 and top silicon layer 203.
In the present embodiment, substrate 201 can be the semiconductor substrate of any materials, such as polysilicon or polycrystalline germanium semiconductor
Substrate.The material of insulating layer 202 can be silica.The material for pushing up silicon layer 203 can be monocrystalline silicon.
In the present embodiment, pushing up in silicon layer 203 to include isolation structure, such as (STI does not show fleet plough groove isolation structure
Out).
In the present embodiment, the thickness range of top silicon layer 203 can beSince top silicon layer 203 is after being located at
Unique semiconductor material layer below the continuous gate structure formed, if the thickness of top silicon layer 203 is less thanIt is then subsequent corresponding
Channel region thickness it is too small, and if top silicon layer 203 thickness be greater thanSilicon knot on ultrathin insulating body can not then be formed
Structure.
To make the thickness range control for pushing up silicon layer 203 existThe present embodiment can first provide common insulation
Body silicon-on, this silicon on insulated substrate have the biggish top layer silicon of thickness, such as the thickness range of top layer silicon can be
30nm~80nm (is specifically as follows 30nm, 50nm or 80nm).Then top layer silicon can be thinned to obtain top silicon layer 203, thus
Silicon on insulated substrate shown in Fig. 4 (including substrate 201, insulating layer 202 and top silicon layer 203) is set to become silicon on ultrathin insulating body
Structure.
With continued reference to FIG. 4, forming gate structure on the silicon layer 203 of top, the gate structure includes 211 He of gate dielectric layer
Grid 212.
In the present embodiment, the material of gate dielectric layer 211 can be silica, and the material of grid 212 can be polysilicon.
It should be noted that in other embodiments of the invention, polysilicon material can be removed in subsequent process steps
The grid of material, and form metal gates.At this point, the material of gate dielectric layer can be high-K dielectric layer, it can be to form high K to be situated between
Matter layer-metal gate (HKMG) gate structure.
Referring to FIG. 5, forming first medium layer 221 in the top surface of gate structure and two sides, and first medium layer 221 is same
When covering top 203 upper surface of silicon layer.Then second dielectric layer 222 is formed in 221 side of first medium layer of gate structure two sides.
In the present embodiment, the material of first medium layer 221 can be silica, and the thickness of first medium layer 221 can beThe material of second dielectric layer 222 can be silicon nitride, and the thickness of second dielectric layer 222 can be
Referring to FIG. 6, forming third dielectric layer 223 covers second dielectric layer 222 and first medium layer 221.
In the present embodiment, the material of third dielectric layer 223 can be silica, and the thickness of third dielectric layer 223 can be
Referring to FIG. 7, being etched back to the first medium layer 221 and third dielectric layer that are located on the silicon layer 203 of top shown in removal Fig. 6
223, to form side wall 223a and biasing side wall (not marking) in gate structure two sides, wherein biasing side wall includes second dielectric layer
222 and it is etched back to rear remaining first medium layer 221a, side wall 223a is to be etched back to rear remaining third dielectric layer 223.
In the present embodiment, the thickness range of side wall 223a can beTop silicon layer immediately below side wall 223a
203 are subsequently used for being formed lightly doped district (please referring to Figure 12), and the top silicon layer 203 of the two sides side wall 223a be subsequently used for being formed it is heavily doped
Miscellaneous area's (please referring to Fig. 9), therefore, the distance of the heavily doped region that the thickness effect of side wall 223a is subsequently formed to channel region, simultaneously
Influence the width range of lightly doped district.As it can be seen that the thickness of side wall is an important size factor in the present embodiment.If side
The thickness range of wall is greater thanThen the distance of heavily doped region to channel region is too big, generates not to the performance of semiconductor devices
Benefit influences.If the thickness range of side wall is less thanThen the width of lightly doped district is too small, equally to the performance of semiconductor devices
Have an adverse effect.
Referring to FIG. 8, forming (raised) semiconductor layer 230 raised on the top silicon layer 203 of the two sides side wall 223a.
In the present embodiment, forming semiconductor layer 230 is the shape in order to meet subsequent metal silicide layer (please referring to Figure 11)
It is since top 203 thickness of silicon layer is too small, then subsequent to form metal silicide layer if only top silicon layer 203 at requiring.For
This, in the present embodiment, the thickness range of semiconductor layer 230 isIf the thickness of semiconductor layer 230 is less thanThen it is unfavorable for the formation of subsequent metal silicide layer (please referring to Figure 11).If the thickness of semiconductor layer 230 is greater thanThe waste of material and process time are not only caused, but also will lead to the heavily doped region (please referring to Fig. 9) being subsequently formed
With it is too big at a distance from channel region, reduce the performance of semiconductor devices.
In the present embodiment, semiconductor layer 230 can be formed on the silicon layer 203 of top using epitaxial growth method.Epitaxial growth
Method can grow the identical single-crystal semiconductor layer of crystal orientation on the silicon layer 203 of top, to improve the performance of semiconductor devices.It can be with
Semiconductor layer 230 is formed using vapor phase epitaxy method, detailed process is well known to those skilled in the art, no longer superfluous herein
It states.
Referring to FIG. 9, injecting ion (that is, ion to the top silicon layer 203 of semiconductor layer 230 and the lower section of semiconductor layer 230
Injection, ion implantation), until forming heavily doped region 240, the top silicon layer 203 of not formed heavily doped region is located at described
Below gate structure, the biasing side wall and side wall 223a.
In the present embodiment, being formed by semiconductor devices can be PMOS transistor, at this point, carrying out (source and drain) ion implanting
The foreign ion that technique is injected can be boron ion or indium ion.
In other embodiments of the invention, being formed by semiconductor devices may be NMOS transistor, carry out institute
When stating ion implantation technology, the foreign ion injected can be phosphonium ion or arsenic ion.
Referring to FIG. 10, removing side wall 223a shown in Fig. 9 after the ion implanting to expose the top below side wall 223a
Silicon layer 203.
In the present embodiment, dry etch process can be used, detailed process is well known to those skilled in the art, herein not
It repeats again.
Figure 11 is please referred to, is metallized to the semiconductor layer 230 of exposed top silicon layer 203 and at least partly thickness
Processing, until forming NiSi phase nickel silicide layer 250 (i.e. metal silicide).
In the present embodiment, NiSi phase nickel silicide layer 250 is located at the top silicon layer 203 and heavily doped of exposure after removal side wall 223a
Miscellaneous 240 top of area.The metalized can the top to grid 212 carry out simultaneously, i.e. NiSi phase nickel silicide layer 250 is same
When be formed in the top of grid 212.
In the present embodiment, the metalized is specifically as follows: in semiconductor layer 230, grid 212 and removal side wall
Metal layer (not shown) is formed after 223a on the top silicon layer 203 of exposure, the material of the metal layer can be nickel；Then spike moves back
(spike anneal is to form NiSi phase nickel silicide layer 250 for fire.
In the present embodiment, 250 thickness of NiSi phase nickel silicide layer being formed in semiconductor layer 230 can be greater than or equal to
It is formed in the thickness of the NiSi phase nickel silicide layer 250 in the silicon layer 203 of top, the NiSi phase being formed in the silicon layer 203 of top is nickel suicide
The thickness of nitride layer 250 can be greater than or equal to top 203 thickness of silicon layer.Also, the metal silicide layer being formed in the silicon layer 203 of top
250 generally equal to push up 203 thickness of silicon layer.
Figure 12 is please referred to, the top silicon layer 203 and at least partly thickness of exposure after the removal of side wall 223a shown in Fig. 9 are partly led
Body layer 230 carries out that ion implantation technology is lightly doped, and forms lightly doped district 260.In the present embodiment, lightly doped district 260 shown in Figure 12
Region is essentially coincided with 250 region of the nickel silicide layer of NiSi phase shown in Figure 11.
In the present embodiment, after the side wall 223a shown in removal Fig. 9, the side for biasing second dielectric layer 222 in side wall is sudden and violent
Dew, the ion implantation technology that is lightly doped are carried out using the biasing side wall and the gate structure as mask.When with described inclined
When to set side wall and the gate structure be mask, it on the one hand can prevent lightly doped district 260 after the subsequent anneal to be formed from excessively prolonging
Channel region center is extended to, to prevent short-channel effect, lightly doped district 260 extends to channel after on the other hand guaranteeing subsequent anneal
Area edge distance close enough, to reduce dead resistance.
In the present embodiment, being formed by semiconductor devices can be PMOS transistor, at this point, ion implantation technology is lightly doped
The ion injected is at least one of boron ion and indium ion, and the doping concentration range of ion can be 1E14atom/
cm2~1E16atom/cm2, the Implantation Energy of ion may range from 100eV~5KeV.Pass through control doping concentration and ion
Implantation Energy guarantees in lightly doped district 260 that dead resistance is reduced to ideal level, and makes lightly doped district subsequent
In annealing process, doping segregation (doping segregation) occurs, so that lightly doped district 260 be made to extend to channel region both ends
Edge, it may be assumed that the foreign ion for injecting lightly doped drain injection technology is located at the position for being close to channel area edge, to be source-drain area
Impurity concentration gradient is provided, the electric field in knot and channel section is reduced, the maximum electricity the maximum field position in knot and in channel
Flow path separation, and then can prevent hot carrier.
It should be noted that in other embodiments of the invention, being formed by semiconductor devices may be NMOS crystalline substance
Body pipe, the ion that ion implantation technology injection is lightly doped described at this time can be at least one of phosphonium ion and arsenic ion,
The doping concentration range of ion can be 1E14atom/cm2~1E16atom/cm2, the Implantation Energy of ion may range from
100eV~5KeV.
Figure 13 is please referred to, after ion implantation technology is lightly doped, carrying out annealing process, (annealing, which can also be treated as, to be lightly doped
One of step of ion implantation technology).
In the present embodiment, as shown in figure 13, in annealing process, the ion injected in ion implantation technology is lightly doped and carries out
Doping segregation, so as to form segregation lightly doped district 261, (segregation lightly doped district 261 belongs to one of lightly doped district 260 after annealing
Part), and the present embodiment can control the width W range of segregation lightly doped district 261 according to the selected of above-mentioned each process conditions
ForTo make lightly doped district 260 be close to channel area edge, (channel region is formed under gate structure described in Figure 13
In the top silicon layer 203 of side).
Spike annealing or millisecond laser annealing can be used in the present embodiment, can be used a step annealing, can also be used
Multiple step anneal.The temperature range of the annealing can be 400 DEG C~800 DEG C, such as: 400 DEG C, 500 DEG C, 600 DEG C, 700 DEG C
Or 800 DEG C.If annealing temperature is lower than 400 DEG C, in annealing process, the ion injected in ion implantation technology is lightly doped cannot
Enough doping segregations are enough carried out, if annealing temperature is higher than 800 DEG C, it is unfavorable to cause to the other structures of semiconductor devices
It influences.
In the present embodiment, annealing time range is 10min~180min.The selection of annealing time and above-mentioned annealing temperature
Selection has similar reason.If annealing time is too short, the ion injected in ion implantation technology, which is lightly doped, can not carry out foot
Enough doping segregations, and if annealing time is too long, the ion for adulterating segregation is too many, and cause ion to diffuse to channel region center,
Cause short-channel effect.
In the present embodiment, by carrying out annealing process after ion implantation technology is lightly doped, make NiSi phase nickel silicide
Layer 250 forms extension type NiSi2Phase nickel silicide (does not mark), extension type NiSi2Phase nickel silicide (extension type NiSi2Phase nisiloy
Compound region and 260 region of lightly doped district are almost the same).
As can be seen from the above description, extension type NiSi2Phase nickel silicide is the finally formed metal silicide of the present embodiment.Outside
Prolong type NiSi2Phase nickel silicide and silicon single crystal have essentially identical (111) crystal face, therefore, extension type NiSi2Phase nickel silicide
It can be formed along (111) crystal face, therefore show extension type NiSi in Figure 122Phase nickel silicide region is in an inclined surface, this
Inclined surface is (111) crystal face.And since nickel silicon suicide is in extension type, when carrying out annealing process, Nickel Silicon suicide
Nickel metal diffusion weakens in object, therefore in annealing process, the ion being only injected into is segregated, and in nickel silicon suicide
Metal is not spread substantially.
In existing method, usual nickel silicide is NiSi phase, although the self-resistance of NiSi phase nickel silicide is lower.But
It is, when the thickness for pushing up silicon layer reduces (such as being decreased to about 30nm or 10nm), extension type NiSi2Phase nickel silicide and source/
Drain region and channel region have minimum contact resistance, and extension type NiSi2Phase nickel silicide can also prevent diffusion.This
Embodiment forms extension type NiSi by above-mentioned annealing process2, to improve the performance of finally formed semiconductor devices.
The present embodiment after removing side wall, first to the semiconductor layer 230 of exposed top silicon layer 203 and at least partly thickness into
Then row metalization processing until forming NiSi phase nickel silicide layer 250 carries out that ion implantation technology is lightly doped again, most laggard
Row annealing, makes NiSi phase nickel silicide layer 250 form extension type NiSi2Phase nickel silicide.It should be noted that of the invention
In other embodiments, can also the semiconductor layer first to exposed top silicon layer and at least partly thickness carry out that ion implanting is lightly doped
Technique, then metalized is carried out to the semiconductor layer of exposed top silicon layer and at least partly thickness, the present invention does not limit this
It is fixed.
In the forming method of semiconductor devices provided by this implementation, after forming gate structure on the silicon layer 203 of top, with
Existing method is different, forms biasing side wall and side wall 223a in the gate structure two sides, and first in the two sides side wall 223a
It pushes up and forms semiconductor layer 230 on silicon layer 203, then the top silicon layer 203 to semiconductor layer 230 and below carries out (source and drain) ion
Injection technology forms heavily doped region 240, removes the top silicon layer 203 that side wall 223a is covered with exposure by side wall 223a later, finally
Just the top silicon layer 203 of exposure after semiconductor layer 230 and side wall 223a removal is carried out that ion implantation technology is lightly doped, formation is gently mixed
Miscellaneous area 260.The forming method is not carrying out ion implantation technology (including source and drain ion implantation technology and light to top silicon layer 203
Doped ions injection technology) before, just semiconductor layer 230 first is formed on the silicon layer 203 of top.When forming semiconductor layer 230, silicon is pushed up
Layer 203 does not carry out ion implantation technology also, i.e. top 203 internal crystal structure of silicon layer is not amorphous, therefore can use extension
Growing method successfully forms required semiconductor layer 230, and then improves the performance of finally formed semiconductor devices.
The embodiment of the invention also provides a kind of semiconductor devices, the semiconductor devices can use previous embodiment institute
The forming method of offer is formed, therefore the structure of the semiconductor devices and property are in combination with accordingly interior with reference to previous embodiment
Hold.
Specifically, please referring to Figure 13, the semiconductor devices includes the silicon-on-insulator (not marking), the insulator
Upper silicon successively includes substrate 201, insulating layer 202 and top silicon layer 203.The semiconductor devices further includes being located on the silicon layer 203 of top
Gate structure, the gate structure includes gate dielectric layer 211 and grid 212, and the gate structure two sides also have biasing side
Wall, the biasing side wall includes first medium layer 211a and second dielectric layer 222.The semiconductor devices further includes positioned at described
Push up the semiconductor layer 230 (please referring to Fig. 8) on silicon layer 203, the semiconductor layer 230 and the gate structure in gate structure two sides
Between have gap (gap does not mark, the gap as shown in Figure 9 side wall 223a removal after generate), be located at semiconductor layer
Heavily doped region 240 in 230 and in the top silicon layer of 230 lower section of semiconductor layer, the top silicon layer 203 below the gap neutralize
Lightly doped district 260 at least partly in semiconductor layer 230, lightly doped district 260 include segregation lightly doped district 261.The semiconductor
Device further includes the metal silicide layer in the top neutralization of the silicon layer 203 at least partly semiconductor layer 230 below the gap
250 (please referring to Figure 11), 250 region of metal silicide layer and be lightly doped in miscellaneous area 260 not comprising segregation lightly doped district 261
Region essentially coincides.
In the present embodiment, the thickness range of top silicon layer 203 can beThe thickness range of semiconductor layer 230
Can beThe width range (i.e. the thickness range of side wall 223a shown in Fig. 9) in the gap can beSegregation lightly doped district 261 width W range beThe selection reason of specific each structure size can
With reference to previous embodiment corresponding contents.
In semiconductor devices provided by the present embodiment, lightly doped district 260 is located at heavily doped region 240 and channel region (channel
Area is located in the top silicon layer below gate structure) between, and there is lightly doped district 260 segregation for being close to channel area edge gently to mix
Miscellaneous area 261, therefore, the dead resistance of entire semiconductor devices is small, and performance improves.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of semiconductor devices characterized by comprising
Silicon-on-insulator is provided, the silicon-on-insulator successively includes substrate, insulating layer and top silicon layer；
Gate structure is formed on the top silicon layer；
Side wall is formed in the gate structure two sides；
Semiconductor layer is formed on the top silicon layer of the side wall two sides；
Ion is injected to the top silicon layer below the semiconductor layer and the semiconductor layer, until forming heavily doped region；
After ion implantation, the side wall is removed with the top silicon layer below the exposure side wall；
The semiconductor layer of top silicon layer and at least partly thickness to the exposure carries out that ion implantation technology is lightly doped；
It is described ion implantation technology is lightly doped after, carry out annealing process；
After forming gate structure on the top silicon layer, and before the gate structure two sides form the side wall, further include
In the step of gate structure two sides form biasing side wall；The ion implantation technology that is lightly doped is with the biasing side wall and institute
Stating gate structure is mask；The annealing process, which makes to remove, forms segregation lightly doped district in the top silicon layer exposed after side wall.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the annealing temperature of the annealing process
Range is 400 DEG C~800 DEG C, and annealing time range is 10min~180min.
3. the forming method of semiconductor devices as described in claim 1, which is characterized in that described that ion implantation technology is lightly doped
The ion injected is at least one of phosphonium ion and arsenic ion, and the doping concentration range of the ion is 1E14atom/
cm2~1E16atom/cm2, the Implantation Energy range of the ion is 100eV~5KeV.
4. the forming method of semiconductor devices as described in claim 1, which is characterized in that described that ion implantation technology is lightly doped
The ion injected is at least one of boron ion and indium ion, and the doping concentration range of the ion is 1E14atom/
cm2~1E16atom/cm2, the Implantation Energy range of the ion is 100eV~5KeV.
5. the forming method of semiconductor devices as described in claim 1, which is characterized in that using epitaxial growth method described
The semiconductor layer is formed on the silicon layer of top.
6. the forming method of semiconductor devices as described in claim 1, which is characterized in that after removing the side wall, to sudden and violent
The top silicon layer of dew and the semiconductor layer of at least partly thickness carry out metalized, until forming metal silicide layer.
7. the forming method of semiconductor devices as claimed in claim 6, which is characterized in that be formed in the semiconductor layer
The metal silicide layer thickness is greater than or equal to the metal silicide thickness being formed in the top silicon layer, is formed in institute
The thickness for stating the metal silicide layer in the silicon layer of top is greater than or equal to the top silicon layer thickness.
8. the forming method of semiconductor devices as described in claim 1, which is characterized in that the thickness range of the semiconductor layer
For
9. the forming method of semiconductor devices as described in claim 1, which is characterized in that it is described top silicon layer thickness range be
10. the forming method of semiconductor devices as described in claim 1, which is characterized in that the thickness range of the side wall is
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