CN105512560A - Disposable programmable storage chip and control method thereof - Google Patents
Disposable programmable storage chip and control method thereof Download PDFInfo
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- CN105512560A CN105512560A CN201510840214.4A CN201510840214A CN105512560A CN 105512560 A CN105512560 A CN 105512560A CN 201510840214 A CN201510840214 A CN 201510840214A CN 105512560 A CN105512560 A CN 105512560A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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Abstract
The invention provides a disposable programmable storage chip. The storage chip comprises a controller and a first random access memory. The controller is used for acquiring disposable editable clear data of one data block and outputting a first invoking signal, a second invoking signal and a third invoking signal. The first random access memory is connected with the controller, an encrypt/decrypt engine, a data integrity detector and a data corrector and used for storing ciphertext data with encrypted disposable editable cleartext data in each data block, and supplementing cyclic redundancy check codes and error-correcting codes. The controller is connected with the first random access memory and used for writing all data as preprogrammed data stored into the first random access memory.The first random access memory helps to improve utilization rate of the chip and ensure reliability of OTP data.
Description
Technical field
The present invention relates to security system chip field, particularly relate to a kind of One Time Programmable
storerthe control method of chip and disposable programmable memory chip.
Background technology
Along with the development of technology today, people notice the importance of information security at one's side.Various safety technique is used on the product of ours at one's side such as finance, mobile phone, internet.Safe SOC(SystemonChip; SOC (system on a chip)) the important role of chip performer in safety product; be applied in the fields such as digital signature, ecommerce, mobile-phone payment; so the particular importance that the storage content of protection safety chip is just aobvious, especially the protection of the memory module of some preservation private information, keys etc. is just more important.
Because these private information, keys etc. are generally stored in OTP(OneTimeProgram, one-off programming) in storer, and otp memory itself has and can only write 1 by 0, there is irreversible characteristic, therefore in physics realization, can by covering tamperproof circuit prevention on otp memory.In logical design; one is use storage protection unit (MemoryProtectUnit; MPU) access rights of restricting host protect OTP; prevent main frame unauthorized access; two is consider from the design of OTP controller; the access of hardware constraints storer; prevent main frame unauthorized access; important information is caused to be revealed; such as central processor unit (CentralProcessorUnit; CPU) only at privileged mode, OTP is programmed, and to OTP carry out programming need input password, just can programme when the password is appropriate.
But above-mentioned two kinds of modes of taking precautions against OTP and being tampered, cannot prevent directtissima otp memory, OTP content is stolen, and OTP power down value is easily modified, and after there is OTP misprogrammed, misdata cannot be repaired and use.
Summary of the invention
Object of the present invention is intended at least solve one of above-mentioned technological deficiency, provides the control method of a kind of disposable programmable memory chip and disposable programmable memory chip.
The invention provides a kind of disposable programmable memory chip, described memory chip comprises:
Disposable programmable memory;
Controller, disposablely edits clear data for receiving or exporting, and exports the first call signal, the second call signal and the 3rd call signal;
Enciphering/deciphering engine, be connected with described controller, for according to described first call signal, read and describedly disposablely edit clear data, and described clear data is encrypted obtains encrypt data, and described encrypt data is write the first random access memory;
Data integrity detecting device, be connected with described controller, for according to described second call signal, from the first random access memory, read described encrypt data, and cyclic redundancy check (CRC) code is calculated to encrypt data and writes the first random access memory;
Correcting data error device, be connected with described controller, for according to described 3rd call signal, from the first random access memory, read described encrypt data and cyclic redundancy check (CRC) code, and error correcting code is calculated to described encrypt data and cyclic redundancy check (CRC) code and writes the first random access memory;
First random access memory, respectively with described controller, enciphering/deciphering engine, data integrity detecting device is connected with correcting data error device, for storing the disposable encrypt data edited after clear data encryption in each data block, replenishment cycles redundancy check code and error correcting code;
Controller, is connected with the first random access memory, also for the total data stored in the first random access memory is write described disposable programmable memory as programming data.
As can be seen from the scheme of said chip, by correcting data error device, error correction is carried out to OTP data, under the error correcting capability allowed, even if wrong, correcting data error device also can error correction, and the data that chip is used remain correct data, improve the utilization factor of chip.Integrity detector can ensure that whether the order that data store and numerical value are modified, and ensure that the reliability of OTP data in addition.
The present invention also provides the control method of disposable programmable memory chip, and described control method comprises the following steps:
Controller edits clear data for obtaining the disposable of a data block, and exports the first call signal, and wherein each data block comprises encrypt data, cyclic redundancy check (CRC) code and error correcting code;
Enciphering/deciphering engine, according to described first call signal, reads and describedly disposablely edits clear data, and is encrypted described clear data and obtains encrypt data, and encrypt data is write the first random access memory;
Controller exports the second call signal;
Data integrity detecting device, according to described second call signal, reads described encrypt data from the first random access memory, and calculates cyclic redundancy check (CRC) code to encrypt data and write the first random access memory;
Controller exports the 3rd call signal;
Correcting data error device is according to described 3rd call signal, from the first random access memory, read described encrypt data and cyclic redundancy check (CRC) code, and error correcting code is calculated to described encrypt data and cyclic redundancy check (CRC) code and writes the first random access memory;
The total data stored in first random access memory is write described disposable programmable memory as the programming data of each data block by controller.
As can be seen from the scheme of said method, by correcting data error device, error correction is carried out to OTP data, under the error correcting capability allowed, even if wrong, correcting data error device also can error correction, and the data that chip is used remain correct data, improve the utilization factor of chip.Integrity detector can ensure that whether the order that data store and numerical value are modified, and ensure that the reliability of OTP data in addition.
Accompanying drawing explanation
Fig. 1 is the result schematic diagram of a kind of embodiment of disposable programmable memory chip of the present invention;
Fig. 2 is data store organisation schematic diagram of the present invention;
Fig. 3 is the process flow diagram of a kind of embodiment of control method of disposable programmable memory chip of the present invention;
Fig. 4 is the process flow diagram of the another kind of embodiment of control method of disposable programmable memory chip of the present invention.
Embodiment
In order to make technical matters solved by the invention, technical scheme and beneficial effect clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The invention provides a kind of disposable programmable memory chip of embodiment, as shown in Figure 1, described memory chip comprises:
Disposable programmable memory and otp memory 108;
Controller 101, disposablely edits clear data for receiving or exporting, and exports the first call signal, the second call signal and the 3rd call signal;
Enciphering/deciphering engine 102, be connected with described controller 101, for according to described first call signal, read and describedly disposablely edit clear data, and described clear data is encrypted obtains encrypt data, and described encrypt data is write the first random access memory 106;
Data integrity detecting device 104, be connected with described controller 101, for according to described second call signal, from the first random access memory 106, read described encrypt data, and cyclic redundancy check (CRC) code is calculated to encrypt data and writes the first random access memory 106;
Correcting data error device 103, be connected with described controller 101, for according to described 3rd call signal, from the first random access memory 106, read described encrypt data and cyclic redundancy check (CRC) code, and error correcting code is calculated to described encrypt data and cyclic redundancy check (CRC) code and writes the first random access memory 106;
First random access memory (RAM1) 106, respectively with described controller 101, enciphering/deciphering engine 102, data integrity detecting device 104 is connected with correcting data error device 103, for storing the disposable encrypt data edited after clear data encryption in each data block, cyclic redundancy check (CRC) code and error correcting code;
Controller 101, is connected with the first random access memory 106, also for the total data stored in the first random access memory is write described disposable programmable memory 108 as programming data.
In concrete enforcement, disposable programmable memory chip mainly completes the communication with external bus interface, in programming operation, read operation and self-test operations process, call enciphering/deciphering engine 102, correcting data error device 103 and data integrity detecting device 104 to ensure the security of communication data.Wherein, enciphering/deciphering engine 102 completes OTP(OneTimeProgram when OTP programming operation, one-off programming) encryption of clear data, when reading otp memory 108, OTP encrypt data is decrypted.Correcting data error unit adopts the abbreviation of BCH(Bose, Ray-Chaudhuri and Hocquenghem) algorithm, when OTP programming operation, BCH value is calculated to encrypt data, crc value, and in OTP process of self-test, error correction is carried out to each data block, error correction result is covered the data of original mistake, if can not error correction, then reset deadlock system.Data integrity detects it and adopts CRC(CyclicRedundancyCheck, cyclic redundancy check (CRC)) algorithm, when OTP programming operation, crc value is calculated to OTP encrypt data, and in OTP process of self-test, integrity detection is carried out to the encrypt data of each data block, crc value, if integrity detection failure, then reset deadlock system.In addition,
As can be seen from the scheme of above-mentioned disposable programmable memory chip, by correcting data error device, error correction is carried out to OTP data, under the error correcting capability allowed, even if wrong, correcting data error device also can error correction, the data that chip is used remain correct data, improve the utilization factor of chip.Integrity detector can ensure that whether the order that data store and numerical value are modified, and ensure that the reliability of OTP data in addition.
In concrete enforcement, controller 101 receives or exports the disposable of a data block and edits clear data, be specially: the disposable clear data of editing that controller obtains from main frame divides according to the size of data block, carry out One Time Programmable operation all in units of data block, then controller exports in the first random access memory 106 after being encrypted this data block at every turn.Data store organisation schematic diagram as shown in Figure 2.Encrypt data 201, replenishment cycles redundancy check and CRC code 202 and error correcting code and BCH code 203 form a data block, the size of each data block, are the maximum amount of datas that BCH algorithm can process.Encrypt data 101 be by OTP plain text encryption after data, crc value 102 is values that data integrity detecting device 104 calculates, and BCH value 103 is values that correcting data error device 103 calculates.And RAM1106 size equals the size of a data block, data store according to form shown in Fig. 2.Otp memory 108 is otp memories of One Time Programmable, is used for storing private information and key etc.
In concrete enforcement, described memory chip also comprises first selector 105(MUX1), respectively with described first random access memory 106, controller 101, enciphering/deciphering engine 102, data integrity detecting device 104 and correcting data error device 103, for the encrypt data in the first random access memory 106, cyclic redundancy check (CRC) code and error correcting code export.First selector 105 be MUX MUX1 when OTP programming operation, according to the call signal of controller 101, the OTP encrypt data in RAM1106, crc value and BCH value are carried out selection export.
In concrete enforcement, described memory chip also comprises the second random access memory (RAM2) 111 be connected with disposable programmable memory 108.
In concrete enforcement, the programming data in disposable programmable memory 108, also for when getting the reset signal of chip, is written in the second random access memory 111 by controller 101, exports the 4th call signal to described correcting data error device 103;
Described correcting data error device 103, also for according to the 4th call signal, encrypt data and the cyclic redundancy check (CRC) code of described programming data is read from the second random access memory, and error correction is carried out to encrypt data and cyclic redundancy check (CRC) code, and the data after error correction are covered data in the second random access memory and will be covered into function signal export described controller 101;
Controller 101 also for get be covered into function signal time, export the 5th call signal to data integrity detecting device;
Data integrity detecting device 104 is also for according to the 5th call signal, encrypt data and the cyclic redundancy check (CRC) code of described programming data is read from the second random access memory 111, and integrity detection will be carried out to encrypt data and cyclic redundancy check (CRC) code, and function signal will be detected as export described controller 101;
Controller 101 is also detected as function signal for described in basis, allows the second random access memory 111 described in host access.
In concrete enforcement, controller 101 is also for when getting covering failure signal or detecting failure signal, and chip is locked.
That is, the content inside the second random access memory 111 and the content inside otp memory 108 completely the same.Because OTP chip is vulnerable to the shortcoming that voltage is attacked, by the data Replica of OTP in RAM2, main frame can only obtain OTP data from RAM2, if power down, the data of RAM2 are lost immediately, and assailant does not get data, thus add the security of OTP data.
After chip reset, first by the content replication of otp memory 108 in volatile memory RAM2, then the data in controller 101 calling data error-corrector 103 couples of RAM2 carry out error correction, and error correction result is write RAM2, by the data cover of original mistake, if error correction failure, reset deadlock system, otherwise in controller 101 calling data integrity detector 104 couples of RAM2, data carry out integrity detection, if detect unsuccessfully, reset deadlock system, otherwise OTP self-inspection completes.The data read after the self-inspection of OTP ensure that main frame are not tampered, and after only having self-inspection to complete, main frame could access disposable programmable memory chip.In addition, before OTP is not programmed, be blank, also can carry out OTP process of self-test, now self-inspection inspection be OTP whether be full 0 data.Then just OTP is programmed.
In concrete enforcement, described memory chip also comprises second selector 109, respectively with described second random access memory, enciphering/deciphering engine, data integrity detecting device and correcting data error device, for to the encrypt data in the second random access memory, cyclic redundancy check (CRC) code and error correcting code export.Second selector 109 is MUX MUX2, when reading OTP, OTP encrypt data being distributed to the deciphering of encryption and decryption engine, in OTP process of self-test, OTP encrypt data being distributed to correcting data error device 103 error correction respectively and data integrity detecting device 104 detects.
In concrete enforcement, described memory chip also comprises the first address disarrangement device 107 be connected with first selector 105 and otp memory 108, for the disturbing of data address in otp memory 108.
In concrete enforcement, described memory chip also comprises the second address disarrangement device 110 be connected with second selector 109 and the second random access memory 111 respectively, for the disturbing of data address in the second random access memory 111.
Due to the content be stored in otp memory be encryption after data, by the first address disarrangement device 107 and the second address disarrangement device 110, data address is made to be discontinuous, even if data leak, also be difficult to the meaning analyzing data, add the security of data.
In concrete enforcement, the present invention also provides a kind of control method of disposable programmable memory chip of embodiment, and described control method comprises the following steps:
Controller edits clear data for obtaining the disposable of a data block, and exports the first call signal, and wherein each data block comprises encrypt data, cyclic redundancy check (CRC) code and error correcting code;
Enciphering/deciphering engine, according to described first call signal, reads and describedly disposablely edits clear data, and is encrypted described clear data and obtains encrypt data, and encrypt data is write the first random access memory;
Controller exports the second call signal;
Data integrity detecting device, according to described second call signal, reads described encrypt data from the first random access memory, and calculates cyclic redundancy check (CRC) code to encrypt data and write the first random access memory;
Controller exports the 3rd call signal;
Correcting data error device is according to described 3rd call signal, from the first random access memory, read described encrypt data and cyclic redundancy check (CRC) code, and error correcting code is calculated to described encrypt data and cyclic redundancy check (CRC) code and writes the first random access memory;
The total data stored in first random access memory is write described disposable programmable memory as the programming data of each data block by controller.
In concrete enforcement, OTP process of self-test comprises the following steps:
When getting the reset signal of chip, the programming data in disposable programmable memory is written in the second random access memory by controller, exports the 4th call signal to described correcting data error device;
Described correcting data error device is according to the 4th call signal, encrypt data and the cyclic redundancy check (CRC) code of described programming data is read from the second random access memory, and error correction is carried out to encrypt data and cyclic redundancy check (CRC) code, and the data after error correction are covered data in the second random access memory and will be covered into function signal export described controller;
When controller gets and is covered into function signal, export the 5th call signal to data integrity detecting device;
Data integrity detecting device is according to the 5th call signal, encrypt data and the cyclic redundancy check (CRC) code of described programming data is read from the second random access memory, and integrity detection will be carried out to encrypt data and cyclic redundancy check (CRC) code, and function signal will be detected as export described controller;
Controller according to described in be detected as function signal, allow the second random access memory described in host access.
In concrete enforcement, as shown in Figure 3, described control method comprises the following steps:
Step S301, controller receives OTP clear data, calls enciphering/deciphering engine and is encrypted clear data, obtain encrypt data.
Step S302, controller is by described encrypt data write RAM1.
Step S303, controller reads encrypt data from RAM1 and sends into data integrity detecting device.
Step S304, data integrity detecting device calculates crc value to encrypt data.
Step S305, crc value is write RAM1 by controller.
Step S306, controller reads encrypt data and crc value from RAM1, data is sent in correcting data error device.
Step S307, correcting data error unit device calculates BCH value to described encrypt data and cyclic redundancy check (CRC) code.
Step S308, controller by BCH value write RAM1, complete data block in RAM1 all set.
Step S309, controller is programmed to otp memory, by the data of data block whole in RAM1 write otp memory.
Repeat step S301 to S309, the OTP data of multiple data block of can programming.
In concrete enforcement, as shown in Figure 4, after chip reset, need to carry out self-inspection to disposable programmable memory chip, described control method comprises the following steps:
Step S401, after chip reset, controller by the content replication of otp memory in volatile memory RAM2.
Step S402, the programming data feeding correcting data error device that controller reads a data block from RAM2 carries out error correction.
Step S403, correcting data error unit 203 carries out error correction to the programming data of a data block.
Step S404, controller judges that whether error correction is successful, if successful execution step S405, if unsuccessfully perform step S412.
Step S405, controller, by the data write RAM2 after error correction, covers original misdata.
Step S406, controller reads encrypt data from RAM2 and crc value feeding integrity detector detects.
Step S407, integrity detector carries out integrity detection.
Step S408, controller judges that whether integrity detection result is successful, if successful execution step S409, if unsuccessfully perform step S412.
Step S409, OTP block self-inspection terminates, and data are not tampered.
Step S410, controller judges that all data block self-inspections complete, if do not perform step S402.
Step S411, OTP self-inspection terminates.
Step S412, controller reset deadlock system.
In step s 404, controller judges whether error correction number exceedes preset value, if not, then and error correction achievement, if so, then error correction failure.
In step S408, controller judges whether integrity detection result is 0, if so, then detects successfully, if not, then detects failure.
If main frame carries out read operation to OTP, controller reads OTP encrypt data from RAM2, then calls encryption and decryption engine 102 pairs of decrypt data, then the OTP after deciphering is expressly returned to main frame.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a disposable programmable memory chip, is characterized in that: described memory chip comprises:
Disposable programmable memory;
Controller, edits clear data for receiving or export the disposable of a data block, and exports the first call signal, the second call signal and the 3rd call signal;
Enciphering/deciphering engine, be connected with described controller, for according to described first call signal, read and describedly disposablely edit clear data, and described clear data is encrypted obtains encrypt data, and described encrypt data is write the first random access memory;
Data integrity detecting device, be connected with described controller, for according to described second call signal, from the first random access memory, read described encrypt data, and cyclic redundancy check (CRC) code is calculated to encrypt data and writes the first random access memory;
Correcting data error device, be connected with described controller, for according to described 3rd call signal, from the first random access memory, read described encrypt data and cyclic redundancy check (CRC) code, and error correcting code is calculated to described encrypt data and cyclic redundancy check (CRC) code and writes the first random access memory;
First random access memory, respectively with described controller, enciphering/deciphering engine, data integrity detecting device is connected with correcting data error device, for storing the disposable encrypt data edited after clear data encryption in each data block, replenishment cycles redundancy check code and error correcting code;
Controller, is connected with the first random access memory, also for the total data stored in the first random access memory is write described disposable programmable memory as programming data.
2. memory chip as claimed in claim 1, it is characterized in that: described memory chip also comprises first selector, respectively with described first random access memory, enciphering/deciphering engine, data integrity detecting device and correcting data error device, for to the encrypt data in the first random access memory, cyclic redundancy check (CRC) code and error correcting code export.
3. memory chip as claimed in claim 2, is characterized in that: described memory chip also comprises the second random access memory be connected with disposable programmable memory.
4. memory chip as claimed in claim 3, it is characterized in that: controller is also for when getting the reset signal of chip, programming data in disposable programmable memory is written in the second random access memory, exports the 4th call signal to described correcting data error device;
Described correcting data error device, also for according to the 4th call signal, encrypt data and the cyclic redundancy check (CRC) code of described programming data is read from the second random access memory, and error correction is carried out to encrypt data and cyclic redundancy check (CRC) code, and the data after error correction are covered data in the second random access memory and will be covered into function signal export described controller;
Controller also for get be covered into function signal time, export the 5th call signal to data integrity detecting device;
Data integrity detecting device is also for according to the 5th call signal, encrypt data and the cyclic redundancy check (CRC) code of described programming data is read from the second random access memory, and integrity detection will be carried out to encrypt data and cyclic redundancy check (CRC) code, and function signal will be detected as export described controller;
Controller is also detected as function signal for described in basis, allows the second random access memory described in host access.
5. memory chip as claimed in claim 4, is characterized in that: controller is also for when getting covering failure signal or detecting failure signal, and chip is locked.
6. memory chip as claimed in claim 4, it is characterized in that: described memory chip also comprises second selector, respectively with described second random access memory, enciphering/deciphering engine, data integrity detecting device and correcting data error device, for to the encrypt data in the second random access memory, cyclic redundancy check (CRC) code and error correcting code export.
7. memory chip as claimed in claim 2, it is characterized in that: described memory chip also comprises the first address disarrangement device be connected with described first selector and disposable programmable memory respectively, for the disturbing of data address in disposable programmable memory.
8. memory chip as claimed in claim 4, it is characterized in that: described memory chip also comprises the second address disarrangement device be connected with second selector and the second random access memory respectively, for the disturbing of data address in the second random access memory.
9. a control method for disposable programmable memory chip, is characterized in that: described control method comprises the following steps:
Controller edits clear data for receiving or export the disposable of a data block, and exports the first call signal, and wherein each data block comprises encrypt data, cyclic redundancy check (CRC) code and error correcting code;
Enciphering/deciphering engine, according to described first call signal, reads and describedly disposablely edits clear data, and is encrypted described clear data and obtains encrypt data, and encrypt data is write the first random access memory;
Controller exports the second call signal;
Data integrity detecting device, according to described second call signal, reads described encrypt data from the first random access memory, and calculates cyclic redundancy check (CRC) code to encrypt data and write the first random access memory;
Controller exports the 3rd call signal;
Correcting data error device is according to described 3rd call signal, from the first random access memory, read described encrypt data and cyclic redundancy check (CRC) code, and error correcting code is calculated to described encrypt data and cyclic redundancy check (CRC) code and writes the first random access memory;
The total data stored in first random access memory is write described disposable programmable memory as the programming data of each data block by controller.
10. control method as claimed in claim 9, is characterized in that: edit clear data at controller for obtaining the disposable of a data block, and comprise the following steps before exporting the step of the first call signal:
When getting the reset signal of chip, the programming data in disposable programmable memory is written in the second random access memory by controller, exports the 4th call signal to described correcting data error device;
Described correcting data error device is according to the 4th call signal, described programming data and cyclic redundancy check (CRC) code is read from the second random access memory, and error correction is carried out to described programming data and cyclic redundancy check (CRC) code, and the data after error correction are covered data in the second random access memory and will be covered into function signal export described controller;
When controller gets and is covered into function signal, export the 5th call signal to data integrity detecting device;
Data integrity detecting device is according to the 5th call signal, encrypt data and the cyclic redundancy check (CRC) code of described programming data is read from the second random access memory, and integrity detection will be carried out to encrypt data and cyclic redundancy check (CRC) code, and function signal will be detected as export described controller;
Controller according to described in be detected as function signal, allow the second random access memory described in host access.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108073413A (en) * | 2016-11-15 | 2018-05-25 | 华为技术有限公司 | Chip and chip programming method |
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| CN109977049A (en) * | 2019-03-01 | 2019-07-05 | 京微齐力(深圳)科技有限公司 | A kind of controller and method, system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108073413A (en) * | 2016-11-15 | 2018-05-25 | 华为技术有限公司 | Chip and chip programming method |
| CN108073413B (en) * | 2016-11-15 | 2022-01-11 | 华为技术有限公司 | Chip and chip programming method |
| CN108921561A (en) * | 2018-08-27 | 2018-11-30 | 河南芯盾网安科技发展有限公司 | A kind of digital thermal wallet based on hardware encryption |
| CN108921561B (en) * | 2018-08-27 | 2023-11-21 | 河南芯盾网安科技发展有限公司 | Digital hot wallet based on hardware encryption |
| CN109977049A (en) * | 2019-03-01 | 2019-07-05 | 京微齐力(深圳)科技有限公司 | A kind of controller and method, system |
| CN109977049B (en) * | 2019-03-01 | 2020-06-23 | 京微齐力(深圳)科技有限公司 | Controller, method and system |
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|---|---|
| CN105512560B (en) | 2018-11-16 |
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