CN105468557A

CN105468557A - Isolation method for avoiding interference to SMBUSes (System Management Bus)

Info

Publication number: CN105468557A
Application number: CN201510804476.5A
Authority: CN
Inventors: 孔祥涛
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2015-11-20
Filing date: 2015-11-20
Publication date: 2016-04-06
Anticipated expiration: 2035-11-20
Also published as: CN105468557B

Abstract

The invention discloses an isolation method for avoiding interference to SMBUSBes (System Management Bus), and belongs to the field of server management. According to the isolation method, when a group of SMBUSes output by a server BMC (Baseboard Management Controller) are utilized to mount non-SMBUS interface equipment, an isolation chip is added for the non-SMBUS interface equipment to carry out isolation; GPIOs (General Purpose Input/Output) of the non-SMBUS interface equipment are output to an enabling pin of the isolation chip; when initialization of the non-SMBUS interface equipment is completed, different GPIOs output different levels according to program setting; and by an exclusive-OR gate, a high level is output to open the isolation chip, and the mounted SMBUSes can be normally managed and monitored by the BMC. The isolation method solves the problem that in a power-on stage of equipment without an SMBUS interface, due to long program initialization duration, a level state of an SMBUS interface can be very instable to possibly cause BUS BUSY so as to influence normal operation of the BMC; and influence on the SMBUSes under the condition is avoided.

Description

The partition method that a kind of SMBUS of avoiding is disturbed

Technical field

The present invention discloses the partition method that a kind of SMBUS of avoiding is disturbed, and belongs to server admin field.

Background technology

In server field, BMC is used to realize monitoring management to whole system.But in high-end server, need the number of devices of management often many.Due to the SMBUS restricted number of BMC module, many times to need on one group of SMBUS multiple equipment in parallel to reach the object made full use of.Some equipment, as PsoC, FPGA do not have special SMBUS interface, uses GPIO to carry out software definition SMBUS interface usually.At power up phase, these equipment, as PsoC, FPGA can continue the longer program initialization time usually.In this stage, SMBUS interface level state is very unstable, if now BMC is managing other equipment, then can cause BUSBUSY thus affect BMC normally working.The invention provides the partition method that a kind of SMBUS of avoiding is disturbed, under avoiding above-mentioned situation, SMBUS is affected.

BMC, BaseboardManagementController, baseboard management controller, Baseboard Management Controller, be a special service processor, communicated with system manager by independently connection line, BMC is comprised in the main circuit board of template or monitored equipment usually.The sensor of BMC is used for measuring internal physical variable, and notifies keeper, and keeper will utilize Long-distance Control to take correct measure.Like this, single keeper just can the simultaneously numerous server of Long-distance Control and other equipment, save the overall cost of network, and can guarantee reliability.Function: local and remote diagnosis, control desk support, configuration management, hardware management and failture evacuation.

SMBus, the abbreviation of SystemManagementBus, be translated into System Management Bus, SMBus is a kind of two-wire system universal serial bus, for system and the such task of power management provide a control bus, use the system of SMBus, to send between equipment and receipt message is all pass through SMBus, instead of use independent control line, the number of pins of equipment can be saved like this.

Summary of the invention

The present invention is directed in prior art the equipment not having SMBUS interface, at power up phase, owing to continuing the longer program initialization time, SMBUS interface level state can be very unstable, may BUSBUSY be caused thus affect the problem that BMC normally works, the partition method providing a kind of SMBUS of avoiding to be disturbed, under avoiding above-mentioned situation, SMBUS is affected.

The concrete scheme that the present invention proposes is:

The partition method that a kind of SMBUS of avoiding is disturbed, during the non-SMBUS interfacing equipment of one group of SMBUS carry that server B MC goes out, increase isolating chip to non-SMBUS interfacing equipment to isolate, the GPIO of non-SMBUS interfacing equipment outputs to the enable pin of isolating chip, after the initialization of non-SMBUS interfacing equipment completes, according to program setting, different GPIO exports different level, after XOR gate, export a high level isolating chip is opened, will be normally subject to the management and supervision of BMC by the SMBUS of carry.

Describedly SWITCH chip is increased to non-SMBUS interfacing equipment isolate, the GPIO of non-SMBUS interfacing equipment outputs to the enable pin of SWITCH chip, after the initialization of non-SMBUS interfacing equipment completes, according to program setting, different GPIO exports different level, after XOR gate, export a high level SWITCH chip is opened, will be normally subject to the management and supervision of BMC by the SMBUS of carry.

Describedly increase SWITCH chip to non-SMBUS interfacing equipment and isolate, the GPIO of non-SMBUS interfacing equipment outputs to the OEpin enable pin of SWITCH chip.

Described non-SMBUS interfacing equipment comprises PsoC, FPGA.

The buffer circuit that a kind of SMBUS of avoiding is disturbed, the GPIO of the non-SMBUS interfacing equipment of one group of SMBUS carry that server B MC goes out connects the OEpin enable pin of SWITCH chip through XOR gate, non-SMBUS interfacing equipment level of GPIO in initialization procedure remains on default conditions, and XOR gate exports a low level and closed by Switch chip; After initialization completes, according to program setting, different GPIO exports different level, exports a high level and opened by Switch chip after XOR gate.

Universal input/export referred to as GPIO, or bus extender.

Usefulness of the present invention is:

During the non-SMBUS interfacing equipment of one group of SMBUS carry that the present invention utilizes server B MC to go out, increase isolating chip to non-SMBUS interfacing equipment to isolate, the GPIO of non-SMBUS interfacing equipment outputs to the enable pin of isolating chip, after the initialization of non-SMBUS interfacing equipment completes, according to program setting, different GPIO exports different level, after XOR gate, export a high level isolating chip is opened, the management and supervision of BMC will be normally subject to by the SMBUS of carry, solve the equipment not having SMBUS interface, at power up phase, owing to continuing the longer program initialization time, SMBUS interface level state can be very unstable, may BUSBUSY be caused thus affect the problem that BMC normally works, under avoiding above-mentioned situation, SMBUS is affected.

Accompanying drawing explanation

Fig. 1 the inventive method application structure schematic diagram.

Embodiment

In addition, the present invention also provides a kind of SMBUS of avoiding buffer circuit be disturbed, the GPIO of the non-SMBUS interfacing equipment of one group of SMBUS carry that server B MC goes out connects the OEpin enable pin of SWITCH chip through XOR gate, non-SMBUS interfacing equipment level of GPIO in initialization procedure remains on default conditions, and XOR gate exports a low level and closed by Switch chip; After initialization completes, according to program setting, different GPIO exports different level, exports a high level and opened by Switch chip after XOR gate.

According to said method and summary of the invention, the present invention will be further described by reference to the accompanying drawings.

With reference to accompanying drawing, the multiple equipment of carry on one group of SMBUS that BMC goes out.Simple parallel way cannot avoid the equipment impacts such as PsoC/FPGA, thus produces BUSBUSY, affects BMC monitoring management.Therefore as follows increase SWITCH chip at PsoC/FPGA end and isolate, the OEpin enable pin of SWITCH chip is controlled by PsoC/FPGA.The GPIO of PsoC/FPGA outputs to the OEpin of Switch through an XOR gate (XOR).OEpin has effectively high.Under normal circumstances, the level of PsoC/FPGA GPIO in initialization procedure can remain on default conditions.Therefore XOR gate can export a low level and closed by Switch.Thus SMBUS is from the impact of PsoC/FPGA.After PsoC/FPGA initialization completes, according to program setting, two GPIO export two different level, export a high level and opened by Switch after XOR gate.Now, the SMBUS of PsoC/FPGA will normally be subject to the management and supervision of BMC.

The equipment not having SMBUS interface is solved by said method the present invention, at power up phase, owing to continuing the longer program initialization time, SMBUS interface level state can be very unstable, may cause BUSBUSY thus affect the problem that BMC normally works, under avoiding above-mentioned situation, SMBUS is affected.

Claims

1. the partition method avoiding SMBUS to be disturbed, when it is characterized in that the non-SMBUS interfacing equipment of one group of SMBUS carry that server B MC goes out, increase isolating chip to non-SMBUS interfacing equipment to isolate, the GPIO of non-SMBUS interfacing equipment outputs to the enable pin of isolating chip, after the initialization of non-SMBUS interfacing equipment completes, according to program setting, different GPIO exports different level, after XOR gate, export a high level isolating chip is opened, will be normally subject to the management and supervision of BMC by the SMBUS of carry.

2. the partition method that is disturbed of a kind of SMBUS of avoiding according to claim 1, it is characterized in that describedly increasing SWITCH chip to non-SMBUS interfacing equipment and isolating, the GPIO of non-SMBUS interfacing equipment outputs to the enable pin of SWITCH chip, after the initialization of non-SMBUS interfacing equipment completes, according to program setting, different GPIO exports different level, after XOR gate, export a high level SWITCH chip is opened, will be normally subject to the management and supervision of BMC by the SMBUS of carry.

3. the partition method that is disturbed of a kind of SMBUS of avoiding according to claim 1 and 2, it is characterized in that describedly increasing SWITCH chip to non-SMBUS interfacing equipment and isolating, the GPIO of non-SMBUS interfacing equipment outputs to the OEpin enable pin of SWITCH chip.

4. the partition method that is disturbed of a kind of SMBUS of avoiding according to claim 3, is characterized in that described non-SMBUS interfacing equipment comprises PsoC, FPGA.

5. the buffer circuit avoiding SMBUS to be disturbed, it is characterized in that the GPIO of the non-SMBUS interfacing equipment of one group of SMBUS carry that server B MC goes out connects the OEpin enable pin of SWITCH chip through XOR gate, non-SMBUS interfacing equipment level of GPIO in initialization procedure remains on default conditions, and XOR gate exports a low level and closed by Switch chip; After initialization completes, according to program setting, different GPIO exports different level, exports a high level and opened by Switch chip after XOR gate.