CN105450237B - A kind of digital intermediate frequency dynamic rage extension method - Google Patents
A kind of digital intermediate frequency dynamic rage extension method Download PDFInfo
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- CN105450237B CN105450237B CN201510793836.6A CN201510793836A CN105450237B CN 105450237 B CN105450237 B CN 105450237B CN 201510793836 A CN201510793836 A CN 201510793836A CN 105450237 B CN105450237 B CN 105450237B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
Abstract
The present invention proposes a kind of digital intermediate frequency dynamic rage extension method, further includes significance bit detection unit, data shift cells left and output data gain adjusting unit, realizes that steps are as follows：The RAM that the integer ADC sampled datas that one group of resolution ratio is n are sent into FPGA simultaneously, is synchronized and is carried out data valid bit detection, and one group of ADC sampled datas input obtains most significant digit number when finishing, and is denoted as M；The difference of n M is sent into the arithmetic pipelining of FPGA, each adc data is moved to left into n M successively in data shift cells left；Data after moving to left are sent into digital intermediate frequency signal processing unit and in addition to afterbody multiplying, are intercepted to the output data of all integer data multiplyings in this element；The data format of the output data of digital intermediate frequency signal processing unit is converted into floating type from integer；Gain tuning is carried out according to the digit n M that move to left in data shift cells left to floating type output data.
Description
Technical field
The present invention relates to radio art, more particularly to a kind of digital intermediate frequency dynamic rage extension method.
Background technology
Time-frequency conversion process based on principle of Software Radio, digital intermediate frequency pretreatment includes down coversion, filtering, adding window
Etc. processes, time-frequency conversion generally take FFT operations, implementation to be completed in DSP or FPGA.To ensure that data handling procedure is defeated
Go out data signal-to-noise ratio and input data it is consistent, need using the high data type of operational precision, i.e. real-coded GA.
Integer sampled data is converted into floating type and is sent into Floating-point DSP progress operation by prior art, or in FPGA
It is interior that operation is carried out with real-coded GA format, as shown in Figure 1, its data processing realizes that steps are as follows：
First, adc data format is subjected to data type conversion, floating type is converted into from integer；
Then, real-coded GA is sent into digital medium-frequency signal processing unit and carries out data calculating.
The shortcomings that prior art, is as follows：
(1) when being based on Floating-point DSP realization digital medium-frequency signal processing, since DSP is the serial operational mode of single command cycle,
When data transfer rate is higher, DSP cannot achieve the requirement of real-time processing speed；
(2) if all carrying out operation, same multiplying, real-coded GA institute with real-coded GA format in FPGA
Stock number is accounted for far more than integer data, under the pressure of limited logical resource, this technology is not suitable for digital medium-frequency signal processing.
Invention content
To solve the deficiencies in the prior art, the present invention provides a kind of new digital intermediate frequency dynamic rage extension method, not
Reduce deterioration of the data cutout to digital intermediate frequency signal-to-noise ratio under the premise of changing original FPGA integer datas operation and data cutout,
Extended dynamic range, while meeting the real-time of data processing.
The technical proposal of the invention is realized in this way：
A kind of digital intermediate frequency dynamic rage extension method further includes significance bit detection unit, data shift cells left and output
Data gain adjustment unit realizes that steps are as follows：
Step (1), the RAM that the integer ADC sampled datas that one group of resolution ratio is n are sent into FPGA simultaneously, are synchronized and are carried out
Data valid bit detects, and one group of ADC sampled datas input obtains most significant digit number when finishing, and is denoted as M；
The difference of n-M is sent into the arithmetic pipelining of FPGA, successively by each ADC in data shift cells left by step (2)
Data move to left n-M；
Step (3), the data after moving to left are sent into digital intermediate frequency signal processing unit, in this element, remove afterbody
Except multiplying, the output data of all integer data multiplyings is intercepted；
The data format of the output data of digital intermediate frequency signal processing unit is converted to floating type by step (4) from integer；
Step (5) carries out Gain tuning to floating type output data according to the digit n-M that moves to left in data shift cells left.
Optionally, if a sampled data is A (n)=a020+a121+a222+…+an-22n-2+an-12m-1, ai∈ { 0,1 }, 0
≤ i≤n-1, one is n shared, and most significant digit number is M, moves to left n-M and retains operation number of significant digit to greatest extent, after moving to left
Data are denoted as A ' (n)；
M are set as with the binary data that it is multiplied, is indicated as follows：
B (m)=b020+b121+b222+…+bm-22m-2+bm-12m-1, wherein bi∈ { 0,1 }, 0≤i≤m-1；
Then its mutually multiplied coefficient matrix of A (n) and B (n) is：
Since the most significant digit of A (n) and B (n) are M and m, a respectivelyM-1bm-1=1, A (n) B (m) >=2M+m-2；
As M ＞ m, the product representation of A (n) and B (n) is as follows：
A (n) B (m)=aM-1bm-1·2M+m-2+(aM-1bm-2+aM-2bm-1)·2M+m-3+…
+(aM-mbm-1+aM-m+1bm-2+…+aM-2b1+aM-1b0)·2M-1
≤2M-1·(2m-1+2·2m-2+3·2m-3+…+m·20)
=2M-1·(2m+1- m-2) ＜ 2M+m
Then have 2M+m-2≤ A (n) B (m) ＜ 2M+m；
As M ＜ m, the product representation of A (n) and B (n) is as follows：
A (n) B (m)=aM-1bm-1·2M+m-2+(aM-1bm-2+aM-2bm-1)·2M+m-2+…
+(a0bm-1+a1bm-2+…+aM-2bm-M+1aM-1bm-M)·2M-1
≤2m-1·(2M-1+2·2M-2+3·2M-3+…+M·20)
=2m-1·(2M+1- M-2) ＜ 2M+m
Then have 2M+m-2≤ A (n) B (m) ＜ 2M+m；
Therefore, the most significant bit of A (n) B (m) is 2M+m-2Or 2M+m-1；
When the most significant bit of A (n) B (m) is 2M+m-2When：
The result of A (n) B (m) is expressed as
With []TIndicate cut position processing, if cut out it is K low, then
If ETFor cut position error, then the cut position error of A (n) B (m) is
Work as XkWhen being 1, cut position error is maximum, at this time ET=-(2K- 1), 2K＞ ＞ 1, and enable q=2K, i.e.-q ＜ ET≤0；
After N number of n sampled data carries out multiplying and intercepted in FPGA, N number of E is generatedTInterception is constituted to miss
Difference sequence is set as e (j), j=0,1,2 ..., N-1；
Then, the probability density function of e (j) is
Its mean value isVariance is
If the power of A (n) B (m) isThen the logarithm of the signal-to-noise ratio of A (n) B (m) is expressed as：
It is A ' (n)=A (n) 2 that A (n) sequences, which move to left the sequence after n-M,n-M, the result of A ' (n) B (m) is expressed asK low, K ＞ n-M are cut out, thenA′
(n) the cut position error of B (m) is that its maximum value is set as q ', q '=- (2K-2n-M)；
Then the logarithm of the signal-to-noise ratio of A ' (n) B (m) is expressed as：
Optionally, Gain tuning, floating-point are carried out according to the digit n-M that moves to left of data shift cells left to floating type output data
Type output data divided by 2n-M。
Optionally, e (j) has following statistical nature：
(a) stationary random sequence；
(b) unrelated with the sequence of multiplying is participated in；
(c) uncorrelated between any two value of e (j)；
(d) it is uniformly distributed in error range.
The beneficial effects of the invention are as follows：
(1) while adc data is sent into FPGA, the synchronous identification for carrying out most significant digit number, execution efficiency height；
(2) deterioration of the data cutout to digital intermediate frequency signal-to-noise ratio is maximally reduced；
(3) data output is converted to floating type and significantly extends data representation range, and ensures the data processing of design
Gain is constant.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention without having to pay creative labor, may be used also for those of ordinary skill in the art
With obtain other attached drawings according to these attached drawings.
Fig. 1 is existing digital medium-frequency signal processing procedure principle schematic；
Fig. 2 is the digital intermediate frequency dynamic rage extension method principle schematic of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment shall fall within the protection scope of the present invention.
In FPGA, integer data multiplying output data bit wide is equal to the sum of two input data bit wides, realizes multistage
When multiplying, bit wide increase can cause the consumption of rear class logical resource to increase substantially；Since the logical resource of FPGA is limited,
Therefore it needs to intercept the output data of every grade of multiplying.The data precision that a large amount of multiplyings and data cutout are brought
Loss is so that the signal-to-noise ratio of output data is less than the signal-to-noise ratio of input data.
The present invention reduces deterioration of the data cutout to digital intermediate frequency signal-to-noise ratio, to expanding digital intermediate frequency dynamic range.
The principle of the digital intermediate frequency dynamic rage extension method of the present invention is as shown in Fig. 2, in addition to existing digital intermediate frequency is believed
Further include significance bit detection unit, data shift cells left and output data gain adjusting unit except number processing procedure.
Steps are as follows for the realization of the present invention：
Step (1), the RAM that the integer ADC sampled datas that one group of resolution ratio is n are sent into FPGA simultaneously, are synchronized and are carried out
Data valid bit detects, and one group of ADC sampled datas input can obtain most significant digit number when finishing, and be denoted as M；
The difference of n-M is sent into the arithmetic pipelining of FPGA, successively by each ADC in data shift cells left by step (2)
Data move to left n-M；
Step (3), the data after moving to left are sent into digital intermediate frequency signal processing unit, in this element, remove afterbody
Except multiplying, the output data of all integer data multiplyings is intercepted；
The data format of the output data of digital intermediate frequency signal processing unit is converted to floating type by step (4) from integer；
Step (5) carries out Gain tuning to floating type output data according to the digit n-M that moves to left in data shift cells left,
So that structure and the structure of Fig. 1 shown in Fig. 2 have same gain.
The present invention can reduce deterioration of the data cutout to digital intermediate frequency signal-to-noise ratio, extended dynamic range, and principle is as follows：
If a sampled data is A (n)=a020+a121+a222+…+an-22n-2+an-12n-1, ai∈ { 0,1 }, 0≤i≤n-
1, one is n shared, and most significant digit number is M, and operation number of significant digit, the number after moving to left can be retained to greatest extent by moving to left n-M
According to being denoted as A ' (n).M are set as with the binary data that it is multiplied, is indicated as follows：
B (m)=b020+b121+b222+…+bm-22m-2+bm-12m-1, wherein bi∈ { 0,1 }, 0≤i≤m-1.
Then its mutually multiplied coefficient matrix of A (n) and B (n) is：
Since the most significant digit of A (n) and B (n) are M and m, a respectivelyM-1bm-1=1, i.e. A (n) B (m) >=2M +m-2.As M ＞ m, the product of A (n) and B (n) can indicate as follows：
A (n) B (m)=aM-1bm-1·2M+m-2+(aM-1bm-2+aM-2bm-1)·2M+m-3+…
+(aM-mbm-1+aM-m+1bm-2+…+aM-2b1+aM-1b0·2M-1
≤2M-1·(2m-1+2·2m-2+3·2m-3+…+m·20)
=2M-1·(2m+1- m-2) ＜ 2M+m
Then have 2M+m-2≤ A (n) B (m) ＜ 2M+m。
As M ＜ m, the product of A (n) and B (n) can indicate as follows：
A (n) B (m)=aM-1bm-1·2M+m-2+(aM-1bm-2+aM-2bm-1)·2M+m-3+…
+(a0bm-1+a1bm-2+…+aM-2bm-M+1+aM-1bm-M)·2M-2
≤2m-1·(2M-1+2·2M-2+3·2M-3+…+M·20)
=2m-1·(2M+1- M-2) ＜ 2M+m
Then have 2M+m-2≤ A (n) B (m) ＜ 2M+m。
Therefore, the most significant bit of A (n) B (m) is 2M+m-2Or 2M+m-1。
Below with the most significant bit of A (n) B (m) for 2M+m-2To illustrate the purpose of the present invention.
The result of A (n)-B (m) was represented by with []TIt indicates
Cut position processing then sets E if cutting out K lowTFor cut position error, then A (n) B (m)
Cut position error beWork as XkWhen being 1, cut position error is maximum,
E at this timeT=-(2K- 1), general 2K＞ ＞ 1, and enable q=2K, i.e.-q ＜ ET≤0.N number of n sampled data is multiplied in FPGA
Method operation and after being intercepted, generates N number of ETInterception error sequence is constituted, e (j), j=0,1,2 ..., N-1 are set as.e(j)
Generally there is following statistical nature：
(a) stationary random sequence；
(b) unrelated with the sequence of multiplying is participated in；
(c) uncorrelated between any two value of e (j), i.e. e (j) is white noise sequence；
(d) it is uniformly distributed in error range.
Then, the probability density function of e (j) is
Its mean value isVariance is
If the power of A (n) B (m) isThen the logarithm of the signal-to-noise ratio of A (n) B (m) is expressed as：
It is A ' (n)=A (n) 2 that A (n) sequences, which move to left the sequence after n-M,n-M, the result of A ' (n) B (m) is represented byK low, K ＞ n-M are cut out, thenA′
(n) the cut position error of B (m) is that its maximum value is set as q ', q '=- (2K-2n-M).Then A '
(n) logarithm of the signal-to-noise ratio of B (m) is expressed as：
Comparison 1. 2. formula, must can move to left that digit n-M is bigger, and the signal-to-noise ratio of multiplication output data is influenced to get over by truncated error
It is small.
Gain tuning is carried out according to the digit n-M that moves to left of data shift cells left to floating type output data, i.e. floating type is defeated
Go out data divided by 2n-MSo that the system of Fig. 2 and the system of Fig. 1 have same gain.This is because：
A ' (n) B (m)=A (n) 2n-MB (m)=A (n) B (m) 2n-M, therefore
The digital intermediate frequency dynamic rage extension method of the present invention, while adc data is sent into FPGA, the synchronous maximum that carries out has
The identification of digit is imitated, execution efficiency is high；Maximally reduce deterioration of the data cutout to digital intermediate frequency signal-to-noise ratio；Data export
It is converted to floating type and significantly extends data representation range, and ensure that the data processing gain of design is constant.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
With within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention god.
Claims (4)
1. a kind of digital intermediate frequency dynamic rage extension method, which is characterized in that realize that steps are as follows：
Step (1), the RAM that the integer ADC sampled datas that one group of resolution ratio is n are sent into FPGA simultaneously, are synchronized by effective
Position detection unit carries out data valid bit detection, and one group of ADC sampled datas input obtains most significant digit number when finishing, is denoted as M；
The difference of n-M is sent into the arithmetic pipelining of FPGA, successively by each adc data in data shift cells left by step (2)
Move to left n-M；
Step (3), the data after moving to left are sent into digital intermediate frequency signal processing unit, in this element, remove afterbody multiplication
Except operation, the output data of all integer data multiplyings is intercepted；
The data format of the output data of digital intermediate frequency signal processing unit is converted to floating type by step (4) from integer；
Step (5) moves to left digit n-M in output data Gain tuning to floating type output data according in data shift cells left
Unit carries out Gain tuning.
2. digital intermediate frequency dynamic rage extension method as described in claim 1, which is characterized in that
If a sampled data is A (n)=α020+α121+α222+…+αn-22n-2+αn-12n-2, αi∈ { 0,1 }, 0≤i≤n-1, altogether
There are n, most significant digit number is M, moves to left n-M and retains operation number of significant digit to greatest extent, the data after moving to left are denoted as A '
(n)；
M are set as with the binary data that it is multiplied, is indicated as follows：
B (m)=b020+b121+b222+…+bm-22m-2+bm-12m-1, wherein bi∈ { 0,1 }, 0≤i≤m-1；
Then its mutually multiplied coefficient matrix of A (n) and B (m) is：
Since the most significant digit of A (n) and B (m) are M and m, a respectivelyM-1bm-1=1, A (n) B (m) >=2M+m-2；
As M ＞ m, the product representation of A (n) and B (m) is as follows：
Then have 2M+m-2≤ A (n) B (m) ＜ 2M+m；
As M ＜ m, the product representation of A (n) and B (m) is as follows：
Then have 2M+m-2≤ A (n) B (m) ＜ 2M+m, therefore, the most significant bit of A (n) B (m) is 2M+m-2Or 2M+m-1；
When the most significant bit of A (n) B (m) is 2M+m-2When：
The result of A (n) B (m) is expressed asXk∈ { 0,1 }；
With []TIndicate cut position processing, if cut out it is K low, then
If ETFor cut position error, then the cut position error of A (n) B (m) is
Work as XkWhen being 1, cut position error is maximum, at this time ET=-(2K- 1), 2K＞ ＞ 1, and enable q=2K, i.e.-q ＜ ET≤0；
After N number of n sampled data carries out multiplying and intercepted in FPGA, N number of E is generatedTConstitute interception error sequence
Row, are set as e (j), j=0,1,2 ..., N-1；
Then, the probability density function of e (j) is
Its mean value isVariance is
If the power of A (n) B (m) isThen the logarithm of the signal-to-noise ratio of A (n) B (m) is expressed as：
It is A ' (n)=A (n) 2 that A (n) sequences, which move to left the sequence after n-M,n-M, the result of A ' (n) B (m) is expressed asK low, K ＞ n-M are cut out, thenA′
(n) the cut position error of B (m) isIts maximum value is set as q ', q '=- (2K-2n-M)；
Then the logarithm of the signal-to-noise ratio of A ' (n) B (m) is expressed as：
3. digital intermediate frequency dynamic rage extension method as claimed in claim 2, which is characterized in that floating type output data root
Gain tuning, floating type output data divided by 2 are carried out according to the digit n-M that moves to left of data shift cells leftn-M。
4. digital intermediate frequency dynamic rage extension method as claimed in claim 2, which is characterized in that e (j) has following statistics special
Sign：
(a) stationary random sequence；
(b) unrelated with the sequence of multiplying is participated in；
(c) uncorrelated between any two value of e (j)；
(d) it is uniformly distributed in error range.
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