CN105426314B - A kind of process mapping method of FPGA memories - Google Patents
A kind of process mapping method of FPGA memories Download PDFInfo
- Publication number
- CN105426314B CN105426314B CN201410490278.1A CN201410490278A CN105426314B CN 105426314 B CN105426314 B CN 105426314B CN 201410490278 A CN201410490278 A CN 201410490278A CN 105426314 B CN105426314 B CN 105426314B
- Authority
- CN
- China
- Prior art keywords
- port set
- memory
- port
- macro
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention relates to a kind of process mapping method of FPGA memories, the method includes：Classification encapsulation is carried out according to the raw information of memory logic netlist, generates port set set；According to the quantity and port set parameter of the port set that the port set set includes, memory macro is constructed；Cutting is carried out to the data space and address space of the memory macro according to the resource extent in target process library, obtains memory assembly；The memory assembly includes functional parameter, and the functional parameter is specially：Construct the port set parameter of the port set of the memory macro；The memory assembly is generated into memory assembly expanded set by Bits Expanding and address extension；According to each memory assembly that the memory assembly expanded set includes, then carry out the accurate matching of memory component types；It according to the connection relation of the memory assembly after the accurate matching and the functional parameter, is mapped in device technology mapping library, generates the FPGA memories.
Description
Technical field
The present invention relates to the IC design technical fields in field of microelectronics, especially field programmable gate battle array
Arrange the process mapping method of (Field Programmable Gate Array, FPGA) memory.
Background technology
FPGA is a kind of logic device with abundant hardware resource, powerful parallel processing capability and flexible reconfigurable ability
Part.These features make FPGA obtain more and more extensive uses in many fields such as data processing, communication, network.
Memory is the basic unit of FPGA, and Technology Mapping (Technology Mapping) is that FPGA is related in flow,
Connect the important bridge of front end logic synthesis and rear end placement-and-routing.In this stage, the circuit meshwork list unrelated with technique is one
Under fixed hardware constraint, it is mapped to the dependency structure of technology library, process mapping method directly influences the performance of FPGA.
Invention content
The present invention provides a kind of process mapping methods of FPGA memories, can realize a kind of support more scales, mostly readings
The Technology Mapping of the FPGA memories of WriteMode and multiport.
An embodiment of the present invention provides a kind of process mapping methods of FPGA memories, including：
Classification encapsulation is carried out according to the raw information of memory logic netlist, generates port set set；
According to the quantity and port set parameter of the port set that the port set set includes, memory macro is constructed；
Cutting is carried out to the data space and address space of the memory macro according to the resource extent in target process library,
Obtain memory assembly；The memory assembly includes functional parameter, and the functional parameter is specially：Construct the memory macro
Port set port set parameter；
The memory assembly is generated into memory assembly expanded set by Bits Expanding and address extension；
According to each memory assembly that the memory assembly expanded set includes, then carry out memory component types
Accurate matching；
According to the connection relation of the memory assembly after the accurate matching and the functional parameter, in device technology
Mapping library is mapped, and the FPGA memories are generated.
Preferably, the quantity and port set parameter of the port set for including according to the port set set, construction storage
Device is macro to include：
Determine whether the quantity of the port set is 1 or 2；
It is macro according to the port set parametric configuration one-port memory if it is 1；
It is macro or pseudo-dual port memories are macro according to the full dual-ported memory of port set parametric configuration if it is 2；Its
In, when the port set parameter of two port sets is read-only or another read-only read-write, constructs full dual-port and deposit
Reservoir is macro；When the port set parameter of a port set is only to write, the port set parameter of another port set is read-only
When, construction pseudo-dual port memories are macro；
If the quantity of the port set is 3 or more, according to preset dual-port read-write mode pairing rules, to institute
The port set stated in port set set is matched, and according to the port set of successful matching construct full dual-ported memory it is macro or
Pseudo-dual port memories are macro, macro according to unpaired successful port set construction one-port memory.
It is further preferred that it is described according to preset dual-port read-write mode pairing rules, in the port set set
Port set matched specially：
By the port set parameter be read-only port set it is that the port set of read-write is matched with port set parameter successively,
Until the port set that the port set parameter is read-write is all paired or the port set parameter is that read-only port set is complete
Portion is paired；
When it is read-only port set also to deposit the unpaired port set parameter, by the unpaired port set
Parameter is that read-only port set is successively that the port set only write is matched with port set parameter, until the port set parameter is
The port set only write all is paired or the port set parameter is that read-only port set is all paired；
When being read-only port set there is also the unpaired port set parameter, by the unpaired port
Group parameter is that read-only port set is matched two-by-two.
Preferably, the resource extent in the library according to target process is empty to the data space of the memory macro and address
Between carry out cutting, obtaining memory assembly is specially：
The memory macro scale is calculated according to the data depth of the memory macro and address width；
In target process library, obtains and be more than and make closest to the component type of the resource extent of the memory macro scale
Component type for first cutting component type, or the acquisition resource extent equal with the memory macro scale is used as the first time
Cutting component type；
According to memory macro described in the first cutting component type cutting, memory assembly is constructed.
It is further preferred that when in the target process library, when whole resource extents are respectively less than the memory macro scale,
The method further includes：
The maximum component type of resource extent is as first cutting component type in acquisition target process library.
It is further preferred that the accurate matching includes：
Calculate the first cost that the memory assembly is constructed using the first cutting component type；
It obtains in target process library, is less than the other assemblies type of the resource extent of the first cutting component type；
The cost using memory assembly described in other assemblies type structure is calculated successively, wherein minimum cost is second
Cost；
When second cost is less than the first cost, using the corresponding component type of second cost as described in construction
The optimal component type of memory assembly；
Otherwise, using the first cutting component type as the optimal component type for constructing the memory assembly.
The process mapping method of FPGA memories provided in an embodiment of the present invention, by the original of memory logic netlist
Information carries out classification encapsulation, generates port set set；According to the quantity and port set of the port set that the port set set includes
Parameter constructs memory macro；It is empty to the data space of the memory macro and address according to the resource extent in target process library
Between carry out cutting, obtain memory assembly；Memory component types are carried out after accurately matching, further according to the institute after accurate matching
The connection relation of memory assembly and the functional parameter are stated, is mapped in device technology mapping library, the FPGA is generated and deposits
Reservoir, to realize a kind of process mapping method of FPGA memories that supporting more scales, more read-write modes and multiport.
Description of the drawings
Fig. 1 is the flow chart of the process mapping method of FPGA memories provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram of port set set pin provided in an embodiment of the present invention；
Fig. 3 is the method flow diagram of construction memory macro provided in an embodiment of the present invention；
Fig. 4 is the cutting method flow chart of memory assembly provided in an embodiment of the present invention；
Fig. 5 is the accurate matched method flow diagram of memory assembly provided in an embodiment of the present invention.
Specific implementation mode
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Fig. 1 is the flow chart of the process mapping method of FPGA memories provided in an embodiment of the present invention.As shown in Figure 1, institute
The method of stating includes the following steps：
Step 110, classification encapsulation is carried out according to the raw information of memory logic netlist, generates port set set；
Specifically, when carrying out FPGA Technology Mappings, it is necessary first to there is the raw information of logic netlist to input.For input
Logic netlist raw information, carry out classification encapsulation, generation is set by the one group of relevant pins and parameter of major key of address pins
Set set, the i.e. form of port set.The port set set refers to the set for the multiple port sets for accessing same block storage.End
Mouth group set can be with as shown in Fig. 2, PORT GROUP 0 be first port set in port set set, PORT GROUP in figure
I is the i+1 port set in port set set.
Port set template class having the same in port set set, their pin frameworks having the same.
Each port set has some port set parameters, in one example can be with shown in table 1 specific as follows.
| Port set parameter | Parameter attribute value |
| Synchronous mode | Output deposit, address deposit |
| Control signal | Piece is enabled, writes enabled, reads enabled, resetting is enabled |
| Read/write conflict pattern | It first reads, writes logical, holding, bypass |
| Data-out port reset values | >=0 |
Table 1
By taking port set set shown in Fig. 2 as an example, each port set includes clock signal pin CLK, chip selection signal pin
EN, write enable signal pin WE, reset signal pin RST, data input signal pin DIN (data width), address signal pipe
Foot ADDR (address depth) and data output signal pin DOUT.
It should be noted that the parameter attribute value of each port set can be different in port set set.
Step 120, the quantity and port set parameter for the port set for including according to the port set set construct memory
It is macro；
Specifically, memory macro is characterized by port mode, according to the difference for reading and writing enabled and address pins, by port
All of the port group in group set is divided, the logical layer encapsulation matched.Port mode can be specifically classified as:It is single-ended
Mouth, pseudo-double port, full dual-port and several classifications of multiport.
The specific method for constructing memory macro can be with as shown in figure 3, include the following steps：
Step 301, determine whether the quantity of the port set is 1；
If it is 1, step 302 is executed；It is no to then follow the steps 303；
Step 302, macro according to the port set parametric configuration one-port memory when port set quantity is 1.
Step 303, determine whether the quantity of the port set is 2；
If it is 2, step 304 is executed；It is no to then follow the steps 307；
Step 304, when port set quantity be 2 when, determine two port sets port set parameter whether be only
It reads or one read-only one is read and write；
Step 305, if the port set parameter of two port sets is read-only or a read-only read-write, according to
The full dual-ported memory of port set parametric configuration is macro；
Step 306, if the port set parameter of a port set is only to write, the port set of another port set
Parameter be it is read-only, it is macro according to the port set parametric configuration pseudo-dual port memories；
Step 307, when port set quantity is 3 or more, according to preset dual-port read-write mode pairing rules, to institute
The port set stated in port set set is matched, and according to the port set of successful matching construct full dual-ported memory it is macro or
Pseudo-dual port memories are macro, macro according to unpaired successful port set construction one-port memory.
Specifically, if in port set set when at least 3 port sets, need first to classify to port set, time
Go through whole port sets in port set set, according to the port set parameter of each port set, by whole port sets according to it is read-write,
Parameter attribute that is read-only, only writing is divided, and is classified as read-write port set subclass, read-only port set subclass and is only write end
Mouth group subclass.Then, the port set in all subclass is matched.
Pairing follows certain matching rule, as shown in table 2 below.
Table 2
Also, matched two port sets needs are two port sets for accessing same block storage.
In a specific example, matching process can be specially：
The a port group in read-only port set subclass is chosen successively, first by one in read-only port set subclass
Port set is matched with the port set in read-write port set subclass, if successful matching, by two ends of successful matching
Mouth group is removed from read-only port set subclass and read-write port set subclass respectively, also, according to two ports of pairing
The full dual-ported memory of group construction is macro, until the port set in the read-write port set subclass is all paired, Huo Zhesuo
The port set stated in read-only port set subclass is all paired.
It, will be only if also depositing unpaired port set in read-only port set subclass after the completion of above-mentioned pairing process
Port set of the unpaired port set successively with only write port group subclass is matched in read port group subclass, if matched
To success, two port sets of successful matching are removed from read-only port set subclass and write port group subclass respectively,
Also, it is macro to construct pseudo-dual port memories according to the two of pairing port sets.Until the end in the write port group subclass
Mouthful group all be paired or the read-only port set subclass in port set be all paired.
It, will not if also depositing unpaired port set in read-only port set subclass after the completion of above-mentioned pairing process
The port set parameter being paired is that read-only port set is matched two-by-two.Also, according to the two of pairing port set structures
It is macro to make full dual-ported memory.Until the port set that can not match.
It is macro according to remaining unpaired port set construction one-port memory after the completion of above-mentioned pairing process.
Step 130, according to the resource extent in target process library to the data space and address space of the memory macro
Cutting is carried out, memory assembly is obtained；
Specifically, memory assembly is to advise the data space of memory macro and address space according to target process base resource
Mould carries out the logical layer encapsulation for being matched to target process library that cutting obtains.The memory assembly includes functional parameter, institute
Stating functional parameter is specially：Construct the port set parameter of the port set of the memory macro.
Target process base resource may include multiple assembly, such as block storage, distributed memory etc., each component
It can be by sizes scale.For example block storage can be 5K, 9K, 18K etc., distributed memory can be 32 × 2S, 32
× 2D, 32 × 2T, 32 × 2Q etc..
For the memory macro that previous step constructs, there is a certain size macro scale, target process can be utilized
The size scale of the component of base resource carrys out given threshold, and the data space and address space of the memory macro are cut in determination
The first cutting component type divided carries out cutting according to first cutting component type, then carries out optimal component type matching again.
Specifically as shown in figure 4, including the following steps：
Step 401, the memory macro scale is calculated according to the data depth of the memory macro and address width；
Step 402, the component for being more than memory macro scale in target process library with the presence or absence of size scale is determined；
Step 403, it is equal to if it does, obtaining size scale, or more than simultaneously closest to the memory macro scale
Component type is as first cutting component type；
Step 404, it is cut for the first time if it does not exist, then obtaining the component type that size is largest in target process library and being used as
Subassembly type；
Step 405, according to memory macro described in the first cutting component type cutting, memory assembly is constructed.
Step 140, the memory assembly is generated into memory assembly expanded set by Bits Expanding and address extension；
Specifically, in port set set above-mentioned, it has been specified that address depth and data width, are determining storage
After device assembly, needs to carry out address extension and Bits Expanding according to address depth and data width, make memory assembly expanded set
Address depth and data width are consistent with the memory macro that port set set constructs.
For example, the address depth of port set set is 2K, the address depth for the memory assembly that preceding step determines is 1K, data
Width is 18bit, then in the depth of address, needs memory assembly being extended, be extended to two, gated by EN, when
EN high gates one of memory assembly into line access when effective, the progress of another memory assembly is gated when EN is low effective
Access.
According to the method described in the above specific example, memory assembly can be carried out according to the parameter of port set set
Extension, is configured to memory assembly expanded set corresponding with port set set.
Step 150, each memory assembly for including according to the memory assembly expanded set, then into line storage
The accurate matching of component type；
Specifically, for each memory assembly that expanded set includes, accurate of component type can be carried out again
Match.It is specific as follows to state step：
Step 501, the first cost using the first cutting component type construction memory assembly is calculated；
Step 502, it obtains in target process library, is less than the other assemblies of the resource extent of the first cutting component type
Type；
Step 503, the cost using the other assemblies type structure memory assembly is calculated successively, wherein minimum makes
Valence is the second cost；
Above-mentioned steps 501 can execute after step 502 or 503, can also be with step 502 or 503 parallel execution.
Step 504, judge whether first cost is higher than the second cost；
Step 505, when the first cost is higher than the second cost, using the corresponding component type of second cost as construction
The optimal component type of memory assembly；
Step 506, otherwise, using first cutting component type as the optimal component type of construction memory assembly.
The memory assembly that the optimal component type namely finally determines.
Each memory assembly for including for expanded set determines its optimal component type, to the group that is expanded
In finally determine each memory assembly.
Step 160, according in the memory assembly expanded set accurately match after memory assembly connection relation and
The functional parameter is mapped in device technology mapping library, generates the FPGA memories.
Specifically, by the mapping of memory assembly to memory entities, line can follow different configuration relation rule
Then carry out.When constructing FPGA memories according to memory assembly expanded set, different component selections is stored in constructor
The information of pattern carries out corresponding connection relation configuration according to the different mode of selection.And according to functional parameter, in device work
Skill mapping library is mapped, and required FPGA memories are constructed.
The method provided through the embodiment of the present invention can support the FPGA of more scales, more read-write modes and multiport to deposit
The Technology Mapping of reservoir.
Professional should further appreciate that, described in conjunction with the examples disclosed in the embodiments of the present disclosure
Unit and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, hard in order to clearly demonstrate
The interchangeability of part and software generally describes each exemplary composition and step according to function in the above description.
These functions are implemented in hardware or software actually, depend on the specific application and design constraint of technical solution.
Professional technician can use different methods to achieve the described function each specific application, but this realization
It should not be considered as beyond the scope of the present invention.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can use hardware, processor to execute
The combination of software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only memory
(ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of storage medium well known to interior.
Above-described specific implementation mode has carried out further the purpose of the present invention, technical solution and advantageous effect
It is described in detail, it should be understood that the foregoing is merely the specific implementation mode of the present invention, is not intended to limit the present invention
Protection domain, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (6)
1. a kind of process mapping method of on-site programmable gate array FPGA memory, which is characterized in that the method includes:
Classification encapsulation is carried out according to the raw information of memory logic netlist, generates port set set；
According to the quantity and port set parameter of the port set that the port set set includes, memory macro is constructed；
Cutting is carried out to the data space and address space of the memory macro according to the resource extent in target process library, is obtained
Memory assembly；The memory assembly includes functional parameter, and the functional parameter is specially：Construct the end of the memory macro
The port set parameter of mouth group；
The memory assembly is generated into memory assembly expanded set by Bits Expanding and address extension；
According to each memory assembly that the memory assembly expanded set includes, then carry out the essence of memory component types
Really matching；
According to the connection relation of the memory assembly after the accurate matching and the functional parameter, mapped in device technology
Library is mapped, and the FPGA memories are generated.
2. according to the method described in claim 1, it is characterized in that, the port set for including according to the port set set
Quantity and port set parameter, construction memory macro include：
Determine whether the quantity of the port set is 1 or 2；
It is macro according to the port set parametric configuration one-port memory if it is 1；
It is macro or pseudo-dual port memories are macro according to the full dual-ported memory of port set parametric configuration if it is 2；Wherein,
When the port set parameter of two port sets is read-only or another read-only read-write, full dual-port storage is constructed
Device is macro；When the port set parameter of a port set is only to write, when the port set parameter of another port set is read-only,
It is macro to construct pseudo-dual port memories；
If the quantity of the port set is 3 or more, according to preset dual-port read-write mode pairing rules, to the end
Port set in mouth group set is matched, and constructs macro or pseudo- pair of full dual-ported memory according to the port set of successful matching
Port store is macro, macro according to unpaired successful port set construction one-port memory.
3. according to the method described in claim 2, it is characterized in that, described matched according to preset dual-port read-write mode is advised
Then, the port set in the port set set is matched specially：
By the port set parameter it is that read-only port set is successively that the port set of read-write is matched with port set parameter, until
The port set parameter is that the port set of read-write is all paired or the port set parameter is read-only port set whole quilt
Pairing；
When being read-only port set there is also the unpaired port set parameter, the unpaired port set is joined
Number is that read-only port set is successively that the port set only write is matched with port set parameter, until the port set parameter is only
The port set write all is paired or the port set parameter is that read-only port set is all paired；
When being read-only port set there is also the unpaired port set parameter, the unpaired port set is joined
Number is that read-only port set is matched two-by-two.
4. according to the method described in claim 1, it is characterized in that, the resource extent in the library according to target process is to described
The data space and address space of memory macro carry out cutting, and obtaining memory assembly is specially：
The memory macro scale is calculated according to the data depth of the memory macro and address width；
In target process library, the resource extent component more than or equal to the memory macro scale is obtained, and will be wherein closest
The resource extent component type of the memory macro scale is as first cutting component type；
According to memory macro described in the first cutting component type cutting, memory assembly is constructed.
5. according to the method described in claim 4, it is characterized in that, when in the target process library, whole resource extents are small
When the memory macro scale, the method further includes：
The maximum component type of resource extent is as first cutting component type in acquisition target process library.
6. method according to claim 4 or 5, which is characterized in that it is described it is accurate matching include：
Calculate the first cost that the memory assembly is constructed using the first cutting component type；
It obtains in target process library, is less than the other assemblies type of the resource extent of the first cutting component type；
The cost using memory assembly described in other assemblies type structure is calculated successively, wherein minimum cost is made for second
Valence；
When second cost is less than the first cost, using the corresponding component type of second cost as the construction storage
The optimal component type of device assembly；
Otherwise, using the first cutting component type as the optimal component type for constructing the memory assembly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410490278.1A CN105426314B (en) | 2014-09-23 | 2014-09-23 | A kind of process mapping method of FPGA memories |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410490278.1A CN105426314B (en) | 2014-09-23 | 2014-09-23 | A kind of process mapping method of FPGA memories |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105426314A CN105426314A (en) | 2016-03-23 |
| CN105426314B true CN105426314B (en) | 2018-09-11 |
Family
ID=55504532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410490278.1A Active CN105426314B (en) | 2014-09-23 | 2014-09-23 | A kind of process mapping method of FPGA memories |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105426314B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106407535A (en) * | 2016-09-06 | 2017-02-15 | 北京深维科技有限公司 | Field-programmable gate array chip-based process mapping method |
| CN106383936B (en) * | 2016-09-07 | 2020-01-31 | 京微齐力(北京)科技有限公司 | FPGA memory splitting method |
| CN106383938B (en) * | 2016-09-07 | 2020-01-10 | 京微齐力(北京)科技有限公司 | FPGA memory inference method and device |
| CN110851345B (en) * | 2019-09-23 | 2023-04-14 | 上海辛格林纳新时达电机有限公司 | Calling method and calling device of system parameters |
| CN112948324A (en) * | 2021-04-16 | 2021-06-11 | 山东高云半导体科技有限公司 | Memory mapping processing method and device and FPGA chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003209558A (en) * | 2002-01-10 | 2003-07-25 | Toyo Commun Equip Co Ltd | Node device |
| CN101246511A (en) * | 2008-02-28 | 2008-08-20 | 复旦大学 | Programmable logic device fast logical block mapping method |
| CN101286181A (en) * | 2008-05-30 | 2008-10-15 | 山东大学 | On site programmable gate array on-chip programmable system based on DW8051 core |
-
2014
- 2014-09-23 CN CN201410490278.1A patent/CN105426314B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003209558A (en) * | 2002-01-10 | 2003-07-25 | Toyo Commun Equip Co Ltd | Node device |
| CN101246511A (en) * | 2008-02-28 | 2008-08-20 | 复旦大学 | Programmable logic device fast logical block mapping method |
| CN101286181A (en) * | 2008-05-30 | 2008-10-15 | 山东大学 | On site programmable gate array on-chip programmable system based on DW8051 core |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105426314A (en) | 2016-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105426314B (en) | A kind of process mapping method of FPGA memories | |
| US7711536B2 (en) | System and method for verification aware synthesis | |
| US9043518B2 (en) | Method and apparatus for calibrating a memory interface with a number of data patterns | |
| US20160320451A1 (en) | Simulation verification method for fpga function modules and system thereof | |
| US9390212B2 (en) | Methods and apparatus for synthesizing multi-port memory circuits | |
| US6813201B2 (en) | Automatic generation and validation of memory test models | |
| CN102967823A (en) | Single-particle multi-bit upsetting monitoring system | |
| US9300275B1 (en) | Multi-bit pulsed latch cell for use in an integrated circuit | |
| CN108962304A (en) | Storage device and its operating method | |
| CN108446412B (en) | Memory compiling method and device and generated memory | |
| US9026747B2 (en) | Memory device with a logical-to-physical bank mapping cache | |
| CN108206043A (en) | Data storage device and its operating method | |
| CN107357948A (en) | Method for establishing FPGA netlist | |
| Su et al. | Flash-DBSim: a simulation tool for evaluating flash-based database algorithms | |
| US11156664B2 (en) | Scan chain techniques and method of using scan chain structure | |
| JP2003256495A (en) | Power consumption calculation device and method | |
| CN106126815A (en) | A kind of circuit emulation method and device | |
| CN105260545B (en) | A kind of verification method of programmable circuit system | |
| US20230025288A1 (en) | System and method for generation of a report and debug of address transformations in electronic systems described with ip-xact standard | |
| CN117112452B (en) | Register simulation configuration method, device, computer equipment and storage medium | |
| US7509548B2 (en) | Method and apparatus for integrated circuit self-description | |
| US10007489B1 (en) | Automated method identifying physical memories within a core or macro integrated circuit design | |
| US8819612B1 (en) | Analyzing timing requirements of a hierarchical integrated circuit design | |
| CN1333356C (en) | Write serialization and resource duplication combined multi-port register file design method | |
| Sharma et al. | Designing of 8-bit synchronous FIFO memory using register file |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |