CN105405821A - Wafer level TSV encapsulation structure and encapsulation process - Google Patents
Wafer level TSV encapsulation structure and encapsulation process Download PDFInfo
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- CN105405821A CN105405821A CN201510946081.9A CN201510946081A CN105405821A CN 105405821 A CN105405821 A CN 105405821A CN 201510946081 A CN201510946081 A CN 201510946081A CN 105405821 A CN105405821 A CN 105405821A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a wafer level TSV encapsulation structure and an encapsulation process. One wafer level TSV encapsulation structure comprises a device wafer, the device wafer comprises a substrate, a first insulating layer arranged on the substrate and a plurality of bonding pads arranged on the first insulating layer; the device wafer comprises a groove penetrating the bonding pads and the first insulating layer, the groove is formed in the middle of the bonding pad, the metal material is arranged in the groove, the metal material is electrically connected with the bonding pad; the substrate is provided with a through TSV hole, the TSV hole is corresponding to the bonding pad, the diameter of the TSV hole is greater than the width of the groove, each of the side wall of the TSV hole and the surface of the substrate is provided with a second insulating layer, each of the bottom of the TSV hole and the second insulating layer is provided with at least one layer of re-wiring layer, the re-wiring layer is electrically connected with the metal material, the re-wiring layer is provided with salient points which are electrically connected with the re-wiring layer. The etching of a silicon oxide insulating layer at each of the side wall and corners of the TSV is avoided, and the reliability of the device is effectively improved.
Description
Technical field
The present invention relates to a kind of encapsulating structure of microelectronics technology and packaging technology, be specifically related to a kind of wafer scale TSV encapsulating structure and packaging technology.
Background technology
Along with the continuous progress of microelectric technique, the characteristic size of integrated circuit constantly reduces, and interconnection density improves constantly.The requirement of user to high-performance low power consumption simultaneously improves constantly.In this case, by reducing the live width of interconnection line further to propose the restriction that high performance mode is subject to physical characteristics of materials and apparatus and process, the resistance capacitance (RC) of two-dimentional interconnection line postpones the bottleneck becoming the raising of restriction semiconductor core piece performance gradually.Silicon perforation (ThroughSiliconVia, being called for short TSV) technique is by forming metal upright post in wafer, and be equipped with metal salient point, can to realize between wafer (chip) or direct three-dimensional interconnection between chip and substrate, the limitation of conventional semiconductor chip two dimension wiring can be made up like this.This interconnection mode and traditional Stack Technology as have compared with bonding techniques the stacking density of three-dimensional large, encapsulate the advantages such as overall dimension is afterwards little, thus greatly improve the speed of chip and reduce power consumption.Therefore, TSV technology has been widely regarded as the forth generation encapsulation technology after bonding, carrier band weldering and flip-chip, will become the mainstream technology in high-density packages field gradually.
For employing via-last technology to fingerprint recognition, CIS(CMOSimagesensor) etc. when encapsulating, adopt from chip back drilling, object interconnects with the metal pad of chip front side more.But to interconnect with metal pad, just must penetrate the dielectric layer covered above metal pad and (be generally SiO
2), for SiO
2etching, generally adopt dry etching technology, this layer of dielectric layer lithographic technique can etch away the sidewall in TSV hole and the insulating layer of silicon oxide of corner, this just there will be electricity integrity problem.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of wafer scale TSV encapsulating structure and packaging technology, the insulating layer of silicon oxide of the sidewall and corner that avoid TSV also can be etched, and effectively improves device reliability.
The technical solution used in the present invention is:
A kind of wafer scale TSV encapsulating structure, comprise device wafers, described device wafers comprises substrate, the some pads being arranged on the first insulating barrier on substrate and being arranged on the first insulating barrier, it is characterized in that: described device wafers comprises the groove running through described pad and described first insulating barrier, described groove is arranged on the middle part of pad, metal material is provided with in described groove, described metal material is electrically connected with pad, described substrate is provided with the TSV hole run through, described TSV hole is corresponding with pad to be arranged, the diameter in described TSV hole is greater than the width of described groove, the described sidewall in TSV hole and the surface of substrate are provided with the second insulating barrier, the bottom in described TSV hole and the second insulating barrier are provided with at least one deck wiring layer again, described wiring layer is again electrically connected with metal material, described wiring layer is again provided with salient point, described salient point is electrically connected with wiring layer again.
Corresponding with a kind of wafer scale TSV encapsulating structure, the present invention also provides a kind of wafer scale TSV packaging technology, comprises the steps,
Step one, provide a device wafers, some pads that described device wafers comprises substrate, is arranged on the first insulating barrier on substrate and is arranged on the first insulating barrier; The face at described first insulating barrier place is set to the front of substrate, the another side of the substrate of answering with vis-a-vis is set to the back side; Described device wafers comprises front and back, and the front of described device wafers and the front of substrate are in the same way;
Step 2, etch the first insulating barrier corresponding below pad and pad, described etch areas forms groove, and described groove runs through described pad and the first insulating barrier and is positioned at the middle part of pad;
Step 3, metal material is set in a groove, metal material is electrically connected with pad;
Step 4, carry out thinning to substrate back;
The position of step 5, the corresponding pad of substrate back after thinning makes TSV hole until expose metal material, and the aperture in described TSV hole is greater than the width of groove;
Step 6, in the hole in TSV hole and the back side of substrate make the second insulating barrier;
Second insulating barrier of the bottom in step 7, removal TSV hole, makes the metal material of the bottom in TSV hole out exposed;
Step 8, on the bottom and the second insulating barrier in TSV hole, make at least one deck wiring layer again, wiring layer is again electrically connected with metal material;
Step 9, on wiring layer again, utilize bump process to make salient point, described salient point is electrically connected with wiring layer again.
Further, described step 4 comprises the steps:
A, front bonding one slide glass wafer to device wafers, described bonding pattern is interim bonding or permanent bonding;
B, utilize the thinning machine of wafer to carry out thinning to substrate back, make substrate thinning to 20 ~ 200 microns.
Advantage of the present invention: the present invention is by etching the first insulating barrier corresponding below pad and pad, described etch areas forms groove, metal material is set in a groove, then at the back side of substrate, TSV hole is offered in the position of corresponding pad, and wiring layer is again set in TSV hole, this technique can avoid the sidewall of TSV and the insulating layer of silicon oxide of corner to be etched, and effectively improves device reliability.
Accompanying drawing explanation
Fig. 1 is the structural representation of device wafers of the present invention;
Fig. 2 is that the present invention etches the structural representation after forming groove;
Fig. 3 is the structural representation after arranging metal material in groove of the present invention;
Fig. 4 is the structural representation after substrate back of the present invention offers TSV hole;
Fig. 5 is that the present invention makes the second insulating barrier and the structural representation again after wiring layer;
Fig. 6 is the structural representation after the present invention makes salient point.
Sequence number in figure: 1, device wafers; 2, substrate; 3, the first insulating barrier; 4, pad; 5, groove; 6, metal material; 7, TSV hole; 8, the second insulating barrier; 9, wiring layer again; 10, salient point; 11, passivation layer.
Embodiment
Describe the present invention below with reference to embodiment shown in the drawings.But these execution modes do not limit the present invention, the structure that those of ordinary skill in the art makes according to these execution modes, method or conversion functionally are all included in protection scope of the present invention.
In addition, label or the sign of repetition may be used in various embodiments.These repeat only clearly to describe the present invention in order to simple, do not represent between discussed different embodiment and/or structure and have any relevance.
As shown in Fig. 1 ~ 6: a kind of wafer scale TSV encapsulating structure, comprise device wafers 1, described device wafers 1 comprises substrate 2, the some pads 4 the first insulating barrier 3 being on the substrate 2 set and being arranged on the first insulating barrier 3, described device wafers 1 comprises the groove 5 running through described pad 4 and described first insulating barrier 3, described groove 5 is arranged on the middle part of pad 4, metal material 6 is provided with in described groove 5, described metal material 6 is electrically connected with pad 4, described substrate 2 is provided with the TSV hole 7 run through, described TSV hole 7 is corresponding with pad 4 to be arranged, the diameter in described TSV hole 7 is greater than the width of described groove 5, the sidewall in described TSV hole 7 and the surface of substrate 2 are provided with the second insulating barrier 8, the bottom in described TSV hole 7 and the second insulating barrier 8 are provided with at least one deck wiring layer 9 again, described wiring layer again 9 is electrically connected with metal material 6, described wiring layer again 9 is provided with salient point 10, described salient point 10 is electrically connected with wiring layer 9 again.
Described wiring layer again 9 is also provided with passivation layer 11, and described passivation layer 11 is provided with opening, and described salient point 10 partial receipt is in described opening.
Introduce a kind of wafer scale TSV packaging technology below in detail, comprise the steps:
Step one, as shown in Figure 1, provide one 8 inch, thickness is 725um device wafers 1, is provided with device in described device wafers 1, some pads 4 that described device wafers 1 comprises substrate 2, arranges the first insulating barrier 3 on the substrate 2 and be arranged on the first insulating barrier 3; The face at described first insulating barrier 3 place is set to the front of substrate 2, the another side of the substrate 2 of answering with vis-a-vis is set to the back side; Described device wafers 1 comprises front and back, and the front of described device wafers 1 and the front of substrate 2 are in the same way;
Step 2, as shown in Figure 2, the first insulating barrier 3 corresponding below pad 4 and pad 4 is etched by wet-etching technology or dry etch process, described etch areas forms groove 5, described groove 5 runs through described pad 4 and the first insulating barrier 3, described groove 5 is positioned at the middle part of pad 4, and the width of described groove 5 is 2 ~ 100 microns;
Step 3, as shown in Figure 3, metal material 6 is set in groove 5, metal material 6 is electrically connected with pad 4;
Be specially: first on groove 5 and the first insulating barrier 3, deposit one deck Seed Layer (not shown) by physical vapor deposition (PVD) technique, thickness correspondence gets 0.1um/0.3um; Then photoetching process is carried out, utilize the region beyond photoresist covering groove 5, carry out electroplating technology, carry out metal material 6 to groove 5 to fill, described metal material 6 and pad 4 are electrically connected, remove photoresist, and the Ti/Cu Seed Layer beyond metal material 6 region is etched away, described metal material 6 is copper or other conducting metals;
Step 4, as shown in Figure 4, carry out thinning to substrate 2 back side;
A: to the front bonding one slide glass wafer of device wafers 1, described bonding pattern is interim bonding or permanent bonding;
B: utilize the thinning machine of wafer to carry out thinning to substrate 2 back side, make substrate 2 be thinned to 20 ~ 200 microns;
Step 5, as shown in Figure 5, the position of the corresponding pad 4 in substrate 2 back side after thinning makes TSV hole 7 until expose metal material 6, and the aperture in described TSV hole 7 is greater than the width of groove 5; Make TSV hole 7 to pad 4 position by dry etch process at substrate 2 back side, just, the aperture in aperture 5 ~ 100um, TSV hole 7 is greater than the width of groove 5, and metal material 6 is not contacted with substrate 2;
Step 6, as shown in Figure 5, in the hole in TSV hole 7 and the back side of substrate 2 make the second insulating barrier 8; The manufacture method of described second insulating barrier 8 has two kinds: 1, made by the mode of spin coating or spraying, and now, the material of the second insulating barrier 8 is BCB(p-bisbenzene), PI(claims polyimides) etc. polymeric material; 2, made by chemical vapor deposition (CVD) technique, now, the material of the second insulating barrier 8 is silicon dioxide;
Step 7, as shown in Figure 6, adopts dry etch process or wet-etching technology to remove the second insulating barrier 8 bottom hole, TSV hole 7, makes the metal material 6 of the bottom in TSV hole 7 out exposed;
Step 8, as shown in Figure 6, make at least one deck wiring layer 9 again bottom hole, TSV hole 7 and on the second insulating barrier 8, make again wiring layer 9 be electrically connected with metal material 6; Again wiring layer 9 be made as common process, be generally: bottom TSV hole 7 and the second insulating barrier 8 on depositing Ti/Cu Seed Layer, thickness gets 0.1um/0.3um; Carry out photoetching process, preferred thickness is the photoresist of 5 ~ 10 microns, defines the lines that connect up again; Electroplate, preferred material is copper, and typical electroplating thickness is 3 ~ 5 microns; Remove photoresist also the Ti/Cu Seed Layer of the exterior domain of the lines that connect up again to be eroded, complete the processing of one deck wiring layer 9 again, as multilayer wiring layer 9 again need be made, only need repeat the manufacture craft of above-mentioned wiring layer again 9;
Step 9, as shown in Figure 6, wiring layer 9 again utilizes salient point 10 technique to make salient point 10, and described salient point 10 is electrically connected with wiring layer 9 again;
Be specially: first, wiring layer 9 again makes passivation layer 11, the material of described passivation layer 11 is BCB(p-bisbenzene), PI(claims polyimides) etc. the light-sensitive material in polymeric material, TSV hole 7 is filled up by described passivation layer 11, and cover the wiring layer again 9 at substrate 2 back side, described passivation layer 11 utilize salient point 10 technique make salient point 10, salient point 10 technique is also common process, be generally: the position exposure imaging needing to make salient point 10 on passivation layer 11, expose again wiring layer 9, then depositing Ti/Cu Seed Layer, thickness gets 0.1 micron/0.3 micron, making the position of salient point 10 by photoresist exposure imaging, expose the Seed Layer of bottom, then metal is filled in exposure imaging position to electroplate to be formed, after removing photoresist, form metal salient point 10 with reflux technique or do not adopt reflux technique directly to form metal column salient point 10, the effect of these metal salient points 10 or metal column salient point 10 interconnects at follow-up realization and other substrate or chip.
In above-mentioned a kind of wafer scale TSV packaging technology embodiment, in step one, described device wafers 1 is not limited to 8 inches, also can be other dimensional standard wafers; In described step 8, TSV hole 7 can not be filled up by described passivation layer 11, is just covered in hole, TSV hole 7 and substrate 2 back side.
The present invention is by etching the first insulating barrier 3 corresponding below pad 4 and pad 4, described etch areas forms groove 5, metal material 6 is set in groove 5, then at the back side of substrate 2, TSV hole 7 is offered in the position of corresponding pad 4, and wiring layer 9 is set again in TSV hole 7, the method can avoid the sidewall of TSV and the insulating layer of silicon oxide of corner to be etched, and effectively improves device reliability.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
Claims (3)
1. a wafer scale TSV encapsulating structure, comprise device wafers, described device wafers comprises substrate, the some pads being arranged on the first insulating barrier on substrate and being arranged on the first insulating barrier, it is characterized in that: described device wafers comprises the groove running through described pad and described first insulating barrier, described groove is arranged on the middle part of pad, metal material has been provided with in described groove, described metal material is electrically connected with pad, described substrate is provided with the TSV hole run through, described TSV hole is corresponding with pad to be arranged, the diameter in described TSV hole is greater than the width of described groove, the described sidewall in TSV hole and the surface of substrate are provided with the second insulating barrier, the bottom in described TSV hole and the second insulating barrier are provided with at least one deck wiring layer again, described wiring layer is again electrically connected with metal material, described wiring layer is again provided with salient point, described salient point is electrically connected with wiring layer again.
2. a wafer scale TSV packaging technology, is characterized in that: comprise the steps,
Step one, provide a device wafers, some pads that described device wafers comprises substrate, is arranged on the first insulating barrier on substrate and is arranged on the first insulating barrier; The face at described first insulating barrier place is set to the front of substrate, the another side of the substrate of answering with vis-a-vis is set to the back side; Described device wafers comprises front and back, and the front of described device wafers and the front of substrate are in the same way;
Step 2, etch the first insulating barrier corresponding below pad and pad, described etch areas forms groove, and described groove runs through described pad and the first insulating barrier and is positioned at the middle part of pad;
Step 3, metal material is set in a groove, metal material is electrically connected with pad;
Step 4, carry out thinning to substrate back;
The position of step 5, the corresponding pad of substrate back after thinning makes TSV hole until expose metal material, and the aperture in described TSV hole is greater than the width of groove;
Step 6, in the hole in TSV hole and the back side of substrate make the second insulating barrier;
Second insulating barrier of the bottom in step 7, removal TSV hole, makes the metal material of the bottom in TSV hole out exposed;
Step 8, on the bottom and the second insulating barrier in TSV hole, make at least one deck wiring layer again, wiring layer is again electrically connected with metal material;
Step 9, on wiring layer again, utilize bump process to make salient point, described salient point is electrically connected with wiring layer again.
3. a kind of wafer scale TSV packaging technology according to claim 2, is characterized in that: described step 4 comprises the steps:
A, front bonding one slide glass wafer to device wafers, described bonding is interim bonding or permanent bonding;
B, utilize the thinning machine of wafer to carry out thinning to substrate back, make substrate thinning to 20 ~ 200 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510946081.9A CN105405821A (en) | 2015-12-16 | 2015-12-16 | Wafer level TSV encapsulation structure and encapsulation process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510946081.9A CN105405821A (en) | 2015-12-16 | 2015-12-16 | Wafer level TSV encapsulation structure and encapsulation process |
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| CN105405821A true CN105405821A (en) | 2016-03-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108011608A (en) * | 2017-12-13 | 2018-05-08 | 中国电子科技集团公司第二十六研究所 | Wafer-level packaging structure and packaging process applied to surface acoustic wave filter |
| CN108122791A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer-level packaging method and semiconductor devices |
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| US8102049B2 (en) * | 2006-08-25 | 2012-01-24 | Renesas Electronics Corporation | Semiconductor device including through electrode and method of manufacturing the same |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
| CN104617036A (en) * | 2015-01-14 | 2015-05-13 | 华天科技（昆山）电子有限公司 | Manufacturing method for interconnected through holes in wafer level chip size packaging |
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2015
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Patent Citations (4)
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| US8102049B2 (en) * | 2006-08-25 | 2012-01-24 | Renesas Electronics Corporation | Semiconductor device including through electrode and method of manufacturing the same |
| US20100155940A1 (en) * | 2008-12-19 | 2010-06-24 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108122791A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer-level packaging method and semiconductor devices |
| CN108011608A (en) * | 2017-12-13 | 2018-05-08 | 中国电子科技集团公司第二十六研究所 | Wafer-level packaging structure and packaging process applied to surface acoustic wave filter |
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