CN105336621B - The forming method of fin field effect pipe - Google Patents
The forming method of fin field effect pipe Download PDFInfo
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- CN105336621B CN105336621B CN201410369904.1A CN201410369904A CN105336621B CN 105336621 B CN105336621 B CN 105336621B CN 201410369904 A CN201410369904 A CN 201410369904A CN 105336621 B CN105336621 B CN 105336621B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
A kind of forming method of fin field effect pipe, comprising: provide substrate, substrate surface is formed with several discrete fins；Separation layer is formed in fin side wall and top surface, and etch rate of the etching technics to separation layer is different from the etch rate to fin；Impurity layer is formed in insulation surface, there is atom identical with fin material in impurity layer, and also there is N-type ion or P-type ion in impurity layer；Substrate is made annealing treatment, N-type ion or P-type ion in impurity layer is diffused into fin by separation layer, forms doped region in fin, and impurity layer is converted into intrinsic layer；Using separation layer as etching stop layer, etching removal intrinsic layer；Etching removal separation layer, until exposing fin top and sidewall surfaces.The present invention improves the even concentration for the doped region to be formed, and avoids the decrystallized problem of fin caused by ion implantation technology, and keep the integrality of fin size, optimizes the electric property of fin field effect pipe.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, in particular to a kind of forming method of fin field effect pipe.
Background technique
With the continuous development of semiconductor process technique, the development trend that semiconductor technology node follows Moore's Law is continuous
Reduce.In order to adapt to the reduction of process node, it has to constantly shorten the channel length of MOSFET field-effect tube.Channel length
Shortening has the tube core density for increasing chip, increases the benefits such as the switching speed of MOSFET field-effect tube.
However, with the shortening of device channel length, device source electrode between drain electrode at a distance from also shorten therewith, so
Grid is deteriorated to the control ability of channel, and the difficulty of grid voltage pinch off (pinch off) channel is also increasing, so that subthreshold
Value electric leakage (subthreshold leakage) phenomenon, i.e., so-called short-channel effect (SCE:short-channel
Effects it) is easier to occur.
Therefore, in order to preferably adapt to the scaled requirement of device size, semiconductor technology gradually starts from plane
Mosfet transistor to more high effect three-dimensional transistor transient, such as fin field effect pipe (FinFET).
In FinFET, grid can at least be controlled ultra-thin body (fin) from two sides, be had more much better than than planar MOSFET devices
Grid to the control ability of channel, can be good at inhibiting short-channel effect；And FinFET has more preferable relative to other devices
Existing production of integrated circuits technology compatibility.
However, the electric property for the fin field effect pipe that the prior art is formed is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of fin field effect pipe, equal in the concentration for improving doped region
While even property, fin and doped region is avoided to be damaged, improves the electric property and reliability of fin field effect pipe.
To solve the above problems, the present invention provides a kind of forming method of fin field effect pipe, comprising: provide substrate, institute
It states substrate surface and is formed with several discrete fins；Separation layer, and etching technics are formed in the fin side wall and top surface
Etch rate to separation layer is different from the etch rate to fin；Impurity layer, the impurity are formed in the insulation surface
There is atom identical with fin material in layer, and also there is N-type ion or P-type ion in the impurity layer；To the substrate
It is made annealing treatment, diffuses into N-type ion or P-type ion in impurity layer in fin by separation layer, the shape in fin
At doped region, and impurity layer is converted into intrinsic layer；Using the separation layer as etching stop layer, etching removes the intrinsic layer；It carves
Etching off removes the separation layer, until exposing fin top and sidewall surfaces.
Optionally, the material of the intrinsic layer is silicon, SiGe or silicon carbide.
Optionally, the material of the separation layer is silica.
Optionally, the separation layer with a thickness of 5 angstroms to 10 angstroms.
Optionally, the separation layer is formed using atomic layer deposition or oxidation technology.
Optionally, immersion treatment is carried out to the fin using deionized water ozoniferous, the fin portion surface is aoxidized
Form the separation layer.
Optionally, in the deionized water ozoniferous, ozone concentration is 20ppm to 100ppm.
Optionally, the technological parameter of the atom layer deposition process are as follows: reaction gas includes silicon source gas and oxygen source gas,
Reaction gas further includes current-carrying gas, wherein silicon source gas SiH4、SiH2Cl2、SiHCl3Or Si2Cl6, oxygen source gas O2
Or O3, current-carrying gas N2Or Ar, silicon source gas flow be 100sccm to 5000sccm, oxygen source gas flow be 100sccm extremely
2000sccm, current-carrying gas flow are 100sccm to 5000sccm, and reaction chamber temperature is 50 degree to 450 degree, reaction chamber chamber pressure
It is by force 1 support to 200 supports.
Optionally, the oxidation technology is that remote plasma aoxidizes or decoupled plasma aoxidizes.
Optionally, the impurity layer with a thickness of 50 angstroms to 300 angstroms.
Optionally, the N-type ion is P, As or Sb, and the P-type ion is B, Ga or In.
Optionally, the material of the impurity layer is the silicon for mixing P-type ion or the SiGe for mixing P-type ion.
Optionally, when the material of the impurity layer is the silicon of boron-doping, boron atom concentration is 1E21atom/cm in impurity layer3
To 5E25atom/cm3。
Optionally, the material of the impurity layer is the silicon of doped type N ion or the silicon carbide of doped type N ion.
Optionally, the impurity layer is formed using low-pressure chemical vapor deposition process.
Optionally, the deposition reaction chamber temp of the low-pressure chemical vapor deposition process is 400 degree to 800 degree, deposition
Reaction chamber pressure is 5 supports to 100 supports.
Optionally, the intrinsic layer is removed using tetramethylammonium hydroxide or ammonium hydroxide etching.
Optionally, during forming the impurity layer or after forming the impurity layer, the annealing is carried out.
Optionally, the technique of the annealing is in spike annealing, Millisecond annealing or solid phase epitaxial regrowth annealing
It is one or more of.
Optionally, the technological parameter of the solid phase epitaxial regrowth annealing are as follows: annealing temperature is 400 degree to 650 degree, annealing
Pressure is 1 support to 760 supports, and anneal duration is 1min to 120min, in N2Or it is carried out under atmosphere of inert gases.
Compared with prior art, technical solution of the present invention has the advantage that
In the embodiment of the present invention, separation layer is formed in fin side wall and top surface, and etching technics is to the quarter of separation layer
It is different from the etch rate to fin to lose rate；Impurity layer is formed in insulation surface, is had and fin material in the impurity layer
Expect identical atom, and also there is N-type ion or P-type ion in the impurity layer；Substrate is made annealing treatment, impurity layer is made
In N-type ion or P-type ion diffused into fin by separation layer, form doped region in fin, and impurity layer converts
For intrinsic layer, there is atom identical with fin material atom, and N-type ion or p-type in intrinsic layer in corresponding intrinsic layer
The content of ion is considerably less or even is not present, therefore the material properties of the intrinsic layer and fin material properties are very close, carves
Etch rate of the etching technique to intrinsic layer and the etch rate to fin are very close.And the present invention is between intrinsic layer and fin
It is formed with separation layer, and etch rate of the etching technics to separation layer is different from the etch rate to fin, therefore goes in etching
When except intrinsic layer, the separation layer plays the role of etching stop layer, prevents the etching technics of etching removal intrinsic layer to fin
It causes to etch, keeps the integrality of fin size, and avoid and the doped region formed in fin is caused to etch, maintain and mix
The integrality in miscellaneous area, to improve the electric property and reliability of fin field effect pipe.
Meanwhile the embodiment of the present invention using in impurity layer N-type ion or P-type ion fin diffused by separation layer
The method for forming doped region, since N-type ion or P-type ion after separation layer by can just diffuse into fin, with existing skill
Art is compared, and the doped region that the embodiment of the present invention is formed can be done more shallow.Also, the formation provided through the embodiment of the present invention is mixed
The method in miscellaneous area avoids the decrystallized problem of ion implantation technology bring, and compared with prior art, shape of the embodiment of the present invention
At doped region ion concentration distribution more evenly.
Further, the embodiment of the present invention forms impurity layer using low-pressure chemical vapor deposition process, anti-under environment under low pressure
Answer the mean free path of the gaseous molecular of gas bigger, so that the indoor reacting gas concentration of reaction chamber quickly reaches concentration point
Cloth uniform state, to improve the even concentration of the N-type ion or P-type ion in the impurity layer of formation, and then make to be formed
The concentration distribution of doped region more evenly, further increases the electric property of fin field effect pipe.
Further, separation layer of the embodiment of the present invention with a thickness of 5 angstroms to 10 angstroms, both guaranteed subsequent to play etching stop layer
Effect, and avoid as separation layer thickness it is blocked up caused by the excessively shallow problem of doped region.
Detailed description of the invention
Fig. 1 is the flow diagram for the fin field effect pipe forming method that an embodiment provides；
Fig. 2 to Figure 15 is the schematic diagram of the section structure of fin field effect pipe forming process provided in an embodiment of the present invention.
Specific embodiment
It can be seen from background technology that the electric property for the fin field effect pipe that the prior art is formed is to be improved.
It has been investigated that the prior art generallys use the side of ion implanting at source region and the drain region of fin field effect pipe
Method is doped the fin of fin field effect pipe；Since fin is stereochemical structure, when the angle difference of ion implanting, source region and
The concentration and injection depth of drain region ion implanting will be different, lead to non-conformal (un-conformal) doping problem occur,
The doping concentration in each region of fin is different, for example, doping concentration of the doping concentration of fin top area than fin sidewall areas
Greatly；The non-conformal doping problem is to lead to an important reason of fin field effect pipe electric property difference.
Also, ion implantation technology also will cause that fin portion surface is decrystallized (amorphization), and fin portion surface is decrystallized
It is poor to also result in fin field effect pipe electric property.
To solve the above problems, propose a kind of forming method of fin field effect pipe, referring to FIG. 1, the following steps are included:
Step S1, substrate is provided, the substrate surface is formed with several discrete fins；Step S2, in the fin top surface and
Sidewall surfaces form impurity layer, have N-type ion or P-type ion in the impurity layer；Step S3, it anneals to the substrate
Processing makes N-type ion or P-type ion in impurity layer diffuse into fin, forms doped region；Step S4, it is making annealing treatment
Cheng Hou, etching remove the impurity layer.
The above method avoids the decrystallized problem of ion implantation technology bring, also, fin top area and sidewall region
The doping concentration in domain reaches unanimity.
In order to improve formation impurity layer quality, reduce the hole in impurity layer so that N-type ion in impurity layer or
P-type ion is evenly distributed, and improves the uniform concentration distribution of the doped region of formation, using contain silicon, germanium, SiGe, GaAs
Or material of the material of silicon carbide as impurity layer, also there is in impurity layer N-type ion or P-type ion accordingly.
However, after undergoing annealing, N-type ion or P-type ion in impurity layer diffuse into fin, in impurity layer
Remaining material is silicon, germanium, SiGe, GaAs or silicon carbide, and the material properties and fin material properties are close, is caused
When etching removes the impurity layer, the etching technics also has biggish etch rate to fin, leads to fin and doped region
It is partially etched removal, causes the electric property and reliability decrease of fin field effect pipe.
For this purpose, the present invention provides a kind of forming method of fin field effect pipe, fin side wall and top surface formed every
Absciss layer；Impurity layer is formed in insulation surface, there is atom identical with fin material, and the impurity layer in the impurity layer
In have N-type ion or P-type ion；The substrate is made annealing treatment, N-type ion or P-type ion in impurity layer are expanded
It dissipates and enters in fin, form doped region in fin, and impurity layer is converted into intrinsic layer；Using the separation layer as etching stopping
Layer, etching remove the intrinsic layer；Etching removes the separation layer, until exposing fin top and sidewall surfaces.The present invention
Embodiment is by avoiding ion implantation technology band for the N-type ion or the P-type ion method that diffuses into fin in impurity layer
The decrystallized and non-conformal come adulterates problem, and prevents the technique of removal intrinsic layer from causing adverse effect to fin, makes fin
Portion has good pattern and complete characteristic size, improves the electric property and reliability of the fin field effect pipe of formation.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 15 is that the semiconductor structure that one embodiment of the invention provides forms process the schematic diagram of the section structure.
Referring to FIG. 2, providing substrate 100, the substrate 100 includes first area I and second area II, first area I
100 surface of substrate is formed with several the first discrete fins 101, and 100 surface of second area II substrate is formed with several discrete
Second fin 102.
The substrate 100 provides workbench to be subsequently formed fin field effect pipe.The material of the substrate 100 be silicon,
Silicon on germanium, SiGe, GaAs, silicon carbide or insulator.
In the present embodiment, the material of the substrate 100 is silicon.
The first area I is NMOS area or PMOS area, and the second area II is NMOS area or PMOS area；
The type of the first area I and second area II identical can may be reversed, therefore the fin field effect pipe formed can be with
For NMOS device, PMOS device or cmos device.The present embodiment is using the fin field effect pipe formed as cmos device, and the firstth area
Domain I is PMOS area, second area II be do for NMOS area it is exemplary illustrated.
First fin 101 and the second fin 102 are using dry etching method (RIE:Reactive Ion
Etching) one initial semiconductor substrate of etching is formed.
As one embodiment, the forming step of first fin 101 and the second fin 102 are as follows: offer is initially partly led
Body substrate, the initial semiconductor substrate includes first area and second area；It is formed in the initial semiconductor substrate surface
Patterned mask layer, the mask layer define the position for being subsequently formed the first fin 101 and the second fin 102；With figure
The mask layer of change is exposure mask, and using reactive ion etching process, the initial semiconductor substrate of etched portions thickness is to forming substrate
100, the substrate 100 includes first area I and second area II, and in first area, 100 surface of I substrate is formed several discrete
First fin 101 forms several the second discrete fins 102 on 100 surface of second area II substrate.
In other embodiments, the first fin and the second fin can also be formed using double-pattern exposure method, specifically
, formed fin processing step include: provide initial semiconductor substrate, the initial semiconductor substrate include first area and
Second area；Patterned sacrificial layer is formed in the initial semiconductor substrate surface；Formation is covered in the sacrificial layer surface
And the initial side wall film of initial semiconductor substrate surface；It is etched back to the initial side wall film, is formed initially in sacrificial layer side wall
Side wall layer；Remove the sacrificial layer；Using the initial side wall layer as exposure mask, the initial semiconductor substrate of etching removal segment thickness
Substrate is formed, the substrate includes first area and second area, and substrate surface forms several discrete first in first area
Fin forms several the second discrete fins in second area substrate surface.
Referring to FIG. 3,100 surface of substrate between the first fin 101 and the second fin 102 forms isolation structure 103,
And 103 top surface of isolation structure is lower than 102 top surface of the first fin 101 and the second fin.
The isolation structure 103 prevents adjacent for the first adjacent fin 101, the second adjacent fin 102 to be isolated
It is electrically connected between one fin 101 and adjacent second fin 102.
The material of the isolation structure 103 be silica, silicon nitride or silicon oxynitride,
As one embodiment, the processing step for forming the isolation structure 103 includes: on 100 surface of substrate,
One fin, 101 surface and 102 surface of the second fin form isolation film, and the top surface of the isolation film is higher than the first fin
101 and 102 top surface of the second fin；It is etched back to the isolation film and forms isolation structure 103, and 103 top table of isolation structure
Face is lower than 102 top surface of the first fin 101 and the second fin.
The present embodiment forms the isolation film using mobility chemical vapor deposition process, so that the isolation structure formed
The filling of corner between 103 corner, substrate 100 and the second fin 102 between substrate 100 and the first fin 101
Effect is good.
It in other embodiments of the present invention, can also be in the first fin portion surface and the second fin before forming isolation structure
Portion surface forms liner oxidation layer, and the liner oxidation layer can repair the damage that the first fin and the second fin side wall are subject to
(being damaged caused by the first fin and etching technics when the second fin for example, being formed), for formed isolation structure provide it is good
Interfacial state contacts isolation structure and the first fin and the second fin side wall close.
Referring to FIG. 4, in 103 surface of isolation structure, 101 top surface of the first fin and sidewall surfaces, Yi Ji
Two fins, 102 top surface and sidewall surfaces form the first mask layer 104.
The effect of first mask layer 104 are as follows: the first mask layer 104 of subsequent removal first area I retains the secondth area
The first mask layer 104 of domain II, to prevent the foreign ion in the first impurity layer being subsequently formed from diffusing into the second fin
In 102, avoid carrying out unnecessary doping to the second fin 102.
The material of first mask layer 104 is silica, silicon nitride, silicon oxynitride or amorphous carbon；First exposure mask
Layer 104 is single layer structure or laminated construction.Described is formed using low-pressure chemical vapor deposition process or atom layer deposition process
One mask layer 104.
It is subsequent when first area I forms the first impurity layer, first impurity layer is also formed into the of second area II
One mask layer, 104 surface, if the thickness of the first mask layer 104 is excessively thin, the foreign ion of the first impurity layer can pass through described
One mask layer 104 diffuses into the second fin 102, causes to carry out unnecessary doping to the second fin 102, influences to be formed
The electric property of fin field effect pipe；If the thickness of the first mask layer 104 is blocked up, subsequent etching removes the first of first area I
Etch period needed for mask layer 104 is longer, and the etching technics increases by the 101 bring adverse effect of the first fin, and after
Etch period needed for the first mask layer 104 of continuous etching removal second area I is also longer, and the same etching technics is to the
Two fins, 102 bring adverse effect also increases.
In summary consider analysis, the first mask layer 104 with a thickness of 500 angstroms to 2000 angstroms in the present embodiment.
In the present embodiment, first mask layer 104 is single layer structure, and the material of the first mask layer 104 is silicon nitride.
Referring to FIG. 5, forming the first photoresist layer 105 on 104 surface of the first mask layer of the second area II.
Exposure mask of first photoresist layer 105 as subsequent etching removal the first mask layer of first area I 104.
As a specific embodiment, the forming step of first photoresist layer 105 includes: in the first area I
Initial lithographic glue-line is formed with 104 surface of the first mask layer of second area II；The initial lithographic glue-line is exposed, is shown
Shadow processing, removal are located at the initial lithographic glue-line of first area I, form first photoresist layer 105.
Referring to FIG. 6, with first photoresist layer 105 (please referring to Fig. 5) for exposure mask, etching removal first area I's
First mask layer 104 exposes 101 sidewall surfaces of the first fin and top surface；Remove first photoresist layer 105.
Using dry etch process or the first mask layer 104 of wet-etching technology etching removal first area I.
In the present embodiment, the first mask layer 104 of removal first area I, the dry method are etched using dry etch process
The technological parameter of etching technics are as follows: etching gas includes CHF3And CF4, CHF3Gas flow be 10sccm to 100sccm, CH4
Gas flow be 10sccm to 100sccm, etching cavity pressure be 1 support to 50 supports, etching cavity power be 100 watts to 2000
Watt.
7 are please referred to, forms the first separation layer 106 in 101 top surface of the first fin and sidewall surfaces.
The material of first separation layer 106 is silica or silicon oxynitride.Quarter of the etching technics to the first separation layer 106
It is different from the etch rate to the first fin 101 to lose rate, and etching technics to the etch rate of the first separation layer 106 with to rear
The etch rate of continuous the first intrinsic layer formed is different, therefore first separation layer 106 plays the work of the first fin 101 of protection
With；It is subsequent etching remove the first intrinsic layer when, first separation layer 106 plays the role of etching stop layer, prevents subsequent
The first fin 101 is caused to etch when etching removes the first intrinsic layer, to keep the dimensional integrity of the first fin 101, together
When keep the integrality of the first doped region being subsequently formed, improve the electric property of the fin field effect pipe of formation.
Simultaneously as forming the first separation layer 106, subsequent first impurity layer at 101 top of the first fin and sidewall surfaces
In N-type ion or P-type ion by can just diffuse into the first fin 101, prevent N after first separation layer 106
The depth that type ion or P-type ion diffuse into the first fin 101 is too deep.
Due to subsequent after 106 surface of the first separation layer forms the first impurity layer, N-type ion or P in the first impurity layer
Type ion can be diffused into the first fin 101 by first separation layer 106；If the thickness of the first separation layer 106 is uniform
Property is poor, then the N-type ion or P-type ion in each region diffuse into the first fin 101 in the first impurity layer being subsequently formed
The distance of diffusion path is different, and will lead to the first doped region formed in the first fin 101 is non-conformal doping.Therefore, originally
Embodiment requires the thickness uniformity for the first separation layer 106 to be formed good.
In order to obtain the first good separation layer 106 of the thickness uniformity, the present embodiment uses atom layer deposition process or oxidation
Technique forms first separation layer 106, and according to the characteristic of atom layer deposition process, the first separation layer 106 of formation is also covered
In 104 surface of 103 surface of isolation structure and the first mask layer.
As a specific embodiment, the technological parameter of the atom layer deposition process are as follows: reaction gas includes silicon source gas
Body and oxygen source gas, reaction gas further include current-carrying gas, wherein silicon source gas SiH4、SiH2Cl2、SiHCl3Or Si2Cl6,
Oxygen source gas is O2Or O3, current-carrying gas N2Or Ar, silicon source gas flow are 100sccm to 5000sccm, oxygen source gas flow
For 100sccm to 2000sccm, current-carrying gas flow is 100sccm to 5000sccm, and reaction chamber temperature is 50 degree to 450
Degree, reaction chamber pressure are 1 support to 200 supports.
In other embodiments, in order to obtain the first good separation layer of the thickness uniformity, oxidation technology shape can also be used
At first separation layer, the oxidation technology is remote plasma (remote plasma) oxidation or decoupled plasma
(decouple plasma) oxidation, after wherein remote plasma oxidation technology is generates plasma oxygen outside reaction chamber,
The plasma oxygen is introduced in reaction chamber by carrier gas or other modes, thus the first fin top surface of oxidation and
Sidewall surfaces form the first separation layer in the first fin top surface and sidewall surfaces.
In remote plasma oxidation technology or decoupled plasma oxidation technology, avoid in reaction chamber generate etc. from
Daughter, the plasma contacted with the first fin portion surface is milder, can reduce plasma damage caused by the first fin；
Also, it is 3 D stereo due to introducing the indoor plasma of reaction chamber, and the first fin is also three-dimensional structure, it can
So that the first separation layer to be formed is uniformly distributed in the first fin portion surface, is conducive to the even concentration for making to be subsequently formed the first doped region
Distribution.
As a specific embodiment, when forming the first separation layer using decoupled plasma oxidation technology, the decoupling
The technological parameter of plasma oxidation process are as follows: reaction gas includes oxygen source gas, and the oxygen source gas is O2Or O3One of
Or two kinds, reaction gas flow is 20sccm to 2000sccm, and power is 50 watts to 3000 watts, and duty ratio is 5% to 100%,
Reaction chamber pressure is 5 millitorrs to 100 millitorrs, and when reaction is 20 seconds to 300 seconds a length of, and dilution can also be passed through into reaction chamber
Gas, the diluent gas are He or Ar.
In other embodiments, immersion treatment can also be carried out to first fin using deionized water ozoniferous,
Since the activity of ozone in deionized water is higher, aoxidize to form the first separation layer in first fin portion surface.If containing ozone
Deionized water in ozone ion mass percent it is too low, then the oxidisability of deionized water ozoniferous is poor, oxidation first
The difficulty that fin forms the first separation layer is larger；If the ozone ion mass percent in deionized water ozoniferous is excessively high,
The oxidisability of deionized water ozoniferous is too strong, be easy to cause the first fin of excessive oxidation；For this purpose, when using it is ozoniferous go from
When sub- the first fin of water oxygenization forms the method for the first separation layer, in the deionized water ozoniferous, ozone concentration 20ppm
To 100ppm.
Wherein, as soon as ppm indicates the quality of contained solute in the solution of million parts of unit masses, a few millionths is called several
A ppm, ppm=(quality/solution quality of solute) * 1000000.
If the thickness of the first separation layer 106 is excessively thin, subsequent when etching removes the first intrinsic layer, the first separation layer 106 holds
Easily by all etching removals, causes the first fin 101 to be exposed, etching technics is caused to cause to etch to the first fin；If
The thickness of first separation layer 106 is blocked up, and the N-type ion in the first impurity layer or P-type ion being subsequently formed diffuse into first
Difficulty in fin 101 is excessive.
The above analysis, the first separation layer 106 with a thickness of 5 angstroms to 10 angstroms in the present embodiment.
Referring to FIG. 8, forming the first impurity layer 107 on 106 surface of the first separation layer.
In other embodiments, when the first separation layer is only located at the first fin top surface and sidewall surfaces, then described
One impurity layer is also covered in isolation structure surface and the first exposure mask layer surface.
There is atom identical with 101 material of the first fin, due to the first fin of this implementation in first impurity layer 107
101 material is identical as the material of substrate 100, and the material of the first fin 101 is silicon, therefore is had in first impurity layer 107
There is silicon atom, there can also be germanium atom in first impurity layer 107.
In first impurity layer 107 also have N-type ion or P-type ion, wherein the N-type ion be P, As or Sb,
The P-type ion is B, Ga or In.First impurity layer 107 is subsequent to form the first doped region in the first fin 101 and mention
For N-type ion or P-type ion.
The present embodiment does exemplary illustrated, then the first impurity layer in the present embodiment so that first area I is PMOS area as an example
There is P-type ion in 107 materials, do exemplary illustrated, the material of first impurity layer 107 so that the P-type ion is B as an example
For the silicon of boron-doping or the SiGe of boron-doping, 107 material of the first impurity layer is single phase material or polycrystalline state material.
The reason of having atom identical with 101 material of the first fin in first impurity layer 107, is: the first fin 101
Material be silicon, germanium, SiGe, silicon carbide or GaAs, the atomic radius of the material of the first fin 101 and boron atom radius compared with
It for approximation, therefore can guarantee when forming the first impurity layer 107 integrality of the crystal growth of first impurity layer 107, subtract as far as possible
The uniformity of B ion concentration distribution in the first impurity layer 107 is improved, to mention the defects of lacking the hole in the first impurity layer 107
The ion concentration distribution uniformity for the doped region that height is subsequently formed.
In order to which the Doped ions concentration range for making first be subsequently formed adulterate each region is consistent, the first impurity of the present embodiment
Each region B ion concentration should will be uniformly distributed in layer 107, prevent from causing described since some regions B ion concentration is higher
Doped ions concentration in corresponding first fin, 101 region in region is high, and the depth adulterated is deeper.
For this purpose, the present embodiment forms first impurity layer 107 using low-pressure chemical vapor deposition (LPCVD) technique, by
It is lower in pressure in the reaction chamber of low-pressure chemical vapor deposition process, under the conditions of pressure is lower, the gaseous state of reaction gas
Molecule mean free path (under certain conditions, a gas molecule twice in succession collision between may by each section
The average value of free path) increase, the indoor reaction gas of reaction chamber can quickly achieve the purpose that concentration is uniform, eliminate by boron
The problem of the gas phase concentration gradient bring boron ion concentration distribution unevenness of source gas, so that in the first impurity layer 107 formed
Boron ion even concentration it is high.
As a specific embodiment, the material of the first impurity layer 107 is the silicon of boron-doping, using low-pressure chemical vapor deposition
Technique forms first impurity layer 107, the technological parameter of the low-pressure chemical vapor deposition process are as follows: reaction gas includes silicon
Source gas and boron source gas, wherein silicon source gas SiH4、SiH2Cl2Or SiHCl3, boron source gas BH3Or B2H6, silicon source gas
Body flow is 100sccm to 2000sccm, and boron source gas flow is 100sccm to 2000sccm, and deposition reaction chamber pressure is 5
For support to 100 supports, deposition reaction chamber temp is 400 degree to 800 degree.
In the present embodiment, first impurity layer 107 with a thickness of 50 angstroms to 300 angstroms, B atom in the first impurity layer 107
Concentration is 1E21atom/cm3To 5E25atom/cm3。
Referring to FIG. 9, carrying out the first annealing 108 to the substrate 100, make the first impurity layer 107 (please referring to Fig. 8)
In P-type ion diffuse into the first fin 101, the first doped region 109, and the first impurity are formed in the first fin 101
Layer 107 is converted into the first intrinsic layer 110.
First doped region 109 is lightly doped district or well region.
Since the thickness uniformity of the first separation layer 106 of the present embodiment formation is good, each region of the first impurity layer 107
Boron ion diffuse into the first fin 101 diffusion path it is consistent；And the boron ion concentration in each region of the first impurity layer 107 is equal
Even distribution, therefore the boron ion concentration in each region reaches unanimity in the first doped region 109, so that form conformal doping first mixes
Miscellaneous area 109 is avoided since each region has adverse effect caused by larger boron ion concentration difference, optimization in the first doped region 109
The electric property of the fin field effect pipe of formation.
Also, this embodiment avoids the decrystallized problems of ion implantation technology bring, so that the first fin 101 maintains
Higher performance.
Simultaneously as being formed with the first separation layer 106, the first impurity between the first impurity layer 107 and the first fin 101
B ion in layer 107 after first separation layer 106 by can just diffuse into the first fin 101, first separation layer
106 presence, the depth that can prevent B ion from diffusing into the first fin 101 is too deep, to meet the first doped region formed
The demand of 109 shallower (shallow).
After the annealing of experience first 108, the B ion in the first impurity layer 107 is diffused into the first fin 101,
The content of remaining B ion is considerably less in first impurity layer 107 or even does not contain B ion, therefore at the first annealing of experience
After reason 108, the first impurity layer 107 is converted into the first intrinsic layer 110, and the material of first intrinsic layer 110 is silicon or SiGe,
A small amount of B ion can also be contained in the material of first intrinsic layer 110.
In the present embodiment, the first annealing 108 is carried out after forming first impurity layer 107, makes the first impurity layer
Boron ion in 107 diffuses into the first fin 101, and the first doped region 109 is formed in the first fin 101.
First annealing 108 includes one of annealing steps or multiple tracks annealing steps；First annealing 108
Technique be one or more of spike annealing, Millisecond annealing or solid phase epitaxial regrowth annealing process.
In the present embodiment, the technique of first annealing 108 is solid phase epitaxial regrowth (SPER, Solid Phase
Epitaxial Recrystallization) annealing, the technological parameter of the solid phase epitaxial regrowth annealing are as follows: annealing temperature
It is 400 degree to 650 degree, annealing pressure is 1 support to 760 supports, and anneal duration is 1min to 120min, in N2Or atmosphere of inert gases
Lower progress.
Since the annealing temperature of solid phase epitaxial regrowth annealing process is relatively low (for 450 degree to 600 degree), to fin field
The adverse effect of the electric property of effect pipe is smaller.
In other embodiments, when the technique of the first annealing is spike annealing or Millisecond annealing, the first annealing
Annealing temperature be 750 degree to 900 degree.
In other embodiments, the first annealing can also be carried out while forming the first impurity layer, that is, is being formed
(in-situ) in situ annealing is carried out when the first impurity layer, so that while forming the first impurity layer, established first impurity
N-type ion or P-type ion in layer diffuse into the first fin.
Referring to FIG. 10, being etching stop layer with first separation layer 106, etching removes first intrinsic layer 110
(please referring to Fig. 9).
Since the material of the first intrinsic layer 110 is silicon or SiGe, and the boron ion content in the first intrinsic layer 110 is very
It is few even without therefore the material properties of first intrinsic layer 110 and the material properties of the first fin 101 are closer to, and are etched
Technique is almost the same with the etch rate to the first fin 101 to the etch rate of the first intrinsic layer 110.And etching technics is to
The etch rate of one separation layer 106 compares small more of etch rate of the first intrinsic layer 110, thus when etch expose first every
The etching technics stops after absciss layer 106, so as to prevent the etching technics from continuing to carve after etching the first intrinsic layer 110
The first fin 101 is lost, the integrality of 101 size of the first fin is kept, and keep the integrality of the first doped region 109, prevents
First doped region 109 is caused to etch, improves the electric property of fin field effect pipe.
If the first intrinsic layer 110 is being etched located immediately at 101 top of the first fin and sidewall surfaces, the etching technics
After removing the first intrinsic layer 110, the first fin 101 that be exposed can be caused to etch, 101 size of the first fin is caused to subtract
It is small；If also, the etching technics causes to etch to the first fin 101, then part or all of first doped region 109 also can be by
Etching removal, influences the performance of the first doped region 109, to influence the electric property and reliability of fin field effect pipe.
Etching technics described in the present embodiment is wet-etching technology, as a specific embodiment, the wet etching work
The etch liquids of skill are tetramethylammonium hydroxide (TMAH) or ammonium hydroxide.
In other embodiments, it can also be etched with dry etch process and remove first intrinsic layer, for example, using reaction
Ion etch process, the etching gas of the reactive ion etching process include HBr, Cl2Or HCl.
Figure 11 is please referred to, etching removes first separation layer 106 (please referring to Figure 10), until exposing the first fin
101 tops and sidewall surfaces；Etching removes first mask layer 104 (please referring to Figure 10).
In the present embodiment, first separation layer 106, the quarter of wet-etching technology are removed using wet-etching technology etching
Erosion liquid is hydrofluoric acid solution, wherein the volume ratio of hydrogen fluoride and deionized water is 1:300 to 1:700.
In other embodiments, first separation layer can also be removed using dry etch process etching.
In the present embodiment, first mask layer 104, the quarter of wet-etching technology are removed using wet-etching technology etching
Erosion liquid is hot phosphoric acid solution, wherein the mass percent of phosphoric acid is 65% to 85%, and solution temperature is 80 degree to 120 degree.
In other embodiments, first mask layer can also be removed using dry etch process etching.
Figure 12 is please referred to, on 103 surface of isolation structure, 101 top of the first fin and sidewall surfaces of the first area I
Form the second mask layer 111.
The forming step of second mask layer 111 include: to be formed be covered in the top of the first fin 101 and sidewall surfaces,
The second original mask layer at the second fin 102 top and 103 surface of sidewall surfaces and isolation structure；In the first area I
The second original mask layer surface form patterned second photoresist layer；It is to cover with patterned second photoresist layer
Film, etching removal are located at the second original mask layer of second area II, 103 surface of isolation structure of I, the first fin in first area
101 top of portion and sidewall surfaces form the second mask layer 111.
Figure 13 is please referred to, forms the second separation layer 112 in 102 top surface of the second fin and sidewall surfaces；Institute
It states 112 surface of the second separation layer and forms the second impurity layer 113, and second impurity layer 113 is also covered in 103 table of isolation structure
111 surface of face and the second mask layer.
The material and forming method of second separation layer 112 can refer to material and the formation of the first separation layer 106
Method, details are not described herein.
Second impurity layer 113 has atom identical with 102 material atom of the second fin, therefore second impurity layer
There is silicon atom in 113, and also there is N-type ion or P-type ion in the second impurity layer 113.
The present embodiment by second area II be NMOS area for do it is exemplary illustrated, then in the second impurity layer 113 have N
Type ion, the N-type ion are P, As or Sb, and the present embodiment is that P demonstrates with the N-type ion in second impurity layer 113
Property explanation.
The material of second impurity layer 113 be p-doped silicon or p-doped silicon carbide, the second impurity layer 113 with a thickness of 50 angstroms
To 300 angstroms.
Second impurity layer 113 is formed using low-pressure chemical vapor deposition process, specifically refers to aforementioned first impurity
The forming method of layer, the even concentration of the phosphonium ion in each region is high in the second impurity layer 113 that the present embodiment is formed, and is conducive to
It is subsequently formed the second doped region of conformal doping.
Figure 14 is please referred to, the second annealing 114 is carried out to the substrate 100, the second impurity layer 113 is made (to please refer to figure
13) N-type ion in diffuses into the second fin 102, the second doped region 115 is formed in the second fin 102, and second is miscellaneous
Matter layer 113 is converted into the second intrinsic layer 116.
Second doped region 115 is lightly doped district or well region.
The technique that the technique of second annealing 114 can refer to aforementioned first annealing.
During the second annealing 114, the P ion in the second impurity layer 113 is diffused by the second separation layer 112
Enter in the second fin 102, forms the second doped region 115 in the second fin 102；Since the P ion in the second impurity layer 113 is dense
Degree is evenly distributed, and the second separation layer 112 have uniform thickness, therefore formed the second doped region 115 in each region concentration
Region is consistent, forms the second doped region 115 of conformal doping.
The material of second intrinsic layer 116 is silicon or silicon carbide, can also be had in second intrinsic layer 116 a small amount of
P ion.
Figure 15 is please referred to, is etching stop layer with second separation layer 112, etching removes second intrinsic layer 116
(please referring to Figure 14)；Etching removes second separation layer 112 (please referring to Figure 14), until exposing 102 top of the second fin
And sidewall surfaces；Etching removes second mask layer 111 (please referring to Figure 14).
Etching remove second intrinsic layer 116, the second separation layer 112, the second mask layer 111 technique can refer to respectively
The technique of the first intrinsic layer of aforementioned etching removal, the first mask layer, details are not described herein.
The technical solution of the forming method of fin field effect pipe provided by the invention has the advantage that
Firstly, form separation layer in fin side wall and top surface, and etching technics to the etch rate of separation layer with it is right
The etch rate of fin is different；Impurity layer is formed in insulation surface, there is original identical with fin material in the impurity layer
Son, and also there is N-type ion or P-type ion in the impurity layer；Substrate is made annealing treatment, make N-type in impurity layer from
Son or P-type ion are diffused into fin by separation layer, doped region are formed in fin, and impurity layer is converted into intrinsic layer,
There is atom identical with fin material atom, and the content of the N-type ion or P-type ion in intrinsic layer in corresponding intrinsic layer
It is considerably less or even be not present, therefore the material properties of the intrinsic layer and fin material properties are very close, etching technics is to this
Etch rate and the etch rate to fin for levying layer are very close.And the present invention is formed with isolation between intrinsic layer and fin
Layer, and etch rate of the etching technics to separation layer is different from the etch rate to fin, therefore when etching removes intrinsic layer,
The separation layer plays the role of etching stop layer, prevents the etching technics of etching removal intrinsic layer from causing to etch to fin, protects
The integrality of fin size is held, and avoids and the doped region formed in fin is caused to etch, maintains the complete of doped region
Property, to improve the electric property and reliability of fin field effect pipe.
Secondly, the embodiment of the present invention using in impurity layer N-type ion or P-type ion fin diffused by separation layer
The method for forming doped region, since N-type ion or P-type ion after separation layer by can just diffuse into fin, with existing skill
Art is compared, and the doped region that the embodiment of the present invention is formed can be done more shallow.Also, the formation provided through the embodiment of the present invention is mixed
The method in miscellaneous area avoids the decrystallized problem of ion implantation technology bring, and compared with prior art, shape of the embodiment of the present invention
At doped region ion concentration distribution more evenly.
Again, the embodiment of the present invention forms impurity layer using low-pressure chemical vapor deposition process, reacts under environment under low pressure
The mean free path of the gaseous molecular of gas is bigger, so that the indoor reacting gas concentration of reaction chamber quickly reaches concentration distribution
Uniform state, to improve the even concentration of the N-type ion or P-type ion in the impurity layer of formation, and then make to be formed mixes
The concentration distribution in miscellaneous area more evenly, further increases the electric property of fin field effect pipe.
Finally, separation layer of the embodiment of the present invention with a thickness of 5 angstroms to 10 angstroms, both guaranteed the subsequent work for playing etching stop layer
With, but avoid as separation layer thickness it is blocked up caused by the excessively shallow problem of doped region.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of fin field effect pipe characterized by comprising
Substrate is provided, the substrate surface is formed with several discrete fins；
Separation layer is formed in the fin side wall and top surface, and etching technics is to the etch rate of separation layer and to fin
Etch rate is different, the separation layer with a thickness of 5 angstroms to 10 angstroms；
Impurity layer is formed in the insulation surface, there is atom identical with fin material in the impurity layer, and described miscellaneous
Also there is N-type ion or P-type ion in matter layer；
In N2Or the substrate is made annealing treatment under atmosphere of inert gases, lead to N-type ion or P-type ion in impurity layer
It crosses separation layer to diffuse into fin, forms doped region in fin, and impurity layer is converted into intrinsic layer；
Using the separation layer as etching stop layer, etching removes the intrinsic layer；
Etching removes the separation layer, until exposing fin top and sidewall surfaces.
2. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the material of the intrinsic layer be silicon,
SiGe or silicon carbide.
3. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the material of the separation layer is oxidation
Silicon.
4. the forming method of fin field effect pipe as claimed in claim 3, which is characterized in that using atomic layer deposition or oxidation work
Skill forms the separation layer.
5. the forming method of fin field effect pipe as claimed in claim 4, which is characterized in that use deionized water pair ozoniferous
The fin carries out immersion treatment, and the fin portion surface is aoxidized to form the separation layer.
6. the forming method of fin field effect pipe as claimed in claim 5, which is characterized in that the deionized water ozoniferous
In, ozone concentration is 20ppm to 100ppm.
7. the forming method of fin field effect pipe as claimed in claim 4, which is characterized in that the work of the atom layer deposition process
Skill parameter are as follows: reaction gas includes silicon source gas and oxygen source gas, and reaction gas further includes current-carrying gas, wherein silicon source gas
For SiH4、SiH2Cl2、SiHCl3Or Si2Cl6, oxygen source gas O2Or O3, current-carrying gas N2Or Ar, silicon source gas flow are
100sccm to 5000sccm, oxygen source gas flow be 100sccm to 2000sccm, current-carrying gas flow be 100sccm extremely
5000sccm, reaction chamber temperature are 50 degree to 450 degree, and reaction chamber pressure is 1 support to 200 supports.
8. the forming method of fin field effect pipe as claimed in claim 4, which is characterized in that the oxidation technology be it is long-range equal from
Daughter oxidation or decoupled plasma oxidation.
9. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the impurity layer with a thickness of 50 angstroms
To 300 angstroms.
10. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the N-type ion be P, As or
Sb, the P-type ion are B, Ga or In.
11. the forming method of fin field effect pipe as claimed in claim 10, which is characterized in that the material of the impurity layer is to mix
The silicon of P-type ion or the SiGe for mixing P-type ion.
12. the forming method of fin field effect pipe as claimed in claim 11, which is characterized in that the material of the impurity layer is to mix
When the silicon of boron, boron atom concentration is 1E21atom/cm in impurity layer3To 5E25atom/cm3。
13. the forming method of fin field effect pipe as claimed in claim 10, which is characterized in that the material of the impurity layer is to mix
The silicon of N-type ion or the silicon carbide of doped type N ion.
14. the forming method of fin field effect pipe as claimed in claim 10, which is characterized in that use low-pressure chemical vapor deposition
Technique forms the impurity layer.
15. the forming method of fin field effect pipe as claimed in claim 14, which is characterized in that the low-pressure chemical vapor deposition
The deposition reaction chamber temp of technique is 400 degree to 800 degree, and deposition reaction chamber pressure is 5 supports to 100 supports.
16. the forming method of fin field effect pipe as described in claim 1, which is characterized in that using tetramethylammonium hydroxide or
Ammonium hydroxide etching removes the intrinsic layer.
17. the forming method of fin field effect pipe as described in claim 1, which is characterized in that in the mistake for forming the impurity layer
In journey or after forming the impurity layer, the annealing is carried out.
18. the forming method of fin field effect pipe as claimed in claim 17, which is characterized in that the technique of the annealing is
One or more of spike annealing, Millisecond annealing or solid phase epitaxial regrowth annealing.
19. the forming method of fin field effect pipe as claimed in claim 18, which is characterized in that the solid phase epitaxial regrowth moves back
Fire technological parameter are as follows: annealing temperature be 400 degree to 650 degree, annealing pressure be 1 support to 760 supports, anneal duration for 1min extremely
120min, in N2Or it is carried out under atmosphere of inert gases.
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Effective date of registration: 20200311 Address after: 201203 5th floor, building 3, No. 18, Zhangjiang Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Zhongxin Nanfang integrated circuit manufacturing Co., Ltd Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corp. |