CN105279127B - A kind of FPGA program downloading systems and method based on PCI or PCIe buses - Google Patents
A kind of FPGA program downloading systems and method based on PCI or PCIe buses Download PDFInfo
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- CN105279127B CN105279127B CN201510829561.7A CN201510829561A CN105279127B CN 105279127 B CN105279127 B CN 105279127B CN 201510829561 A CN201510829561 A CN 201510829561A CN 105279127 B CN105279127 B CN 105279127B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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Abstract
A kind of FPGA program downloading systems and method based on PCI or PCIe buses, the present invention relates to the FPGA program downloading systems and method based on PCI or PCIe buses.The present invention causes system reliability to decline to solve the problems, such as that traditional JTAG modes download dismounting circuit board or external cable when FPGA program efficiencies lowly and in existing system update FPGA programs.A kind of FPGA program downloading systems based on PCI/PCIe buses include host computer, FPGA and EPCS configuration chips；It is attached between host computer and FPGA by PCI/PCIe buses；FPGA includes PCI/PCIe bus control units, Avalon buses, EPCS controllers and user-defined functional unit, and FPGA intrawares are connected by Avalon buses；EPCS configuration chips are connected with FPGA.The present invention is applied to FPGA download programs field.
Description
Technical field
The present invention relates to the FPGA program downloading systems and method based on PCI or PCIe buses.
Background technology
Traditional field programmable gate array (Field Programmable Gate Array, FPGA) device is due to it
Have the characteristics that architecture and logic unit are flexible, integrated level is high and the scope of application is wide etc., exploitation flexibly, high speed, in electricity
Many fields such as son, communication, Industry Control all have extensive use.Main flow FPGA framework mainly has SRAM Base and Anti-
Two kinds of fuse design patterns, it is repeatable programming, low-power consumption the characteristics of wherein SRAM Base, system reconfiguration can be carried out；Anti-
Fuse can not carry out repeating modification due to the characteristic with a burning.Most of FPGA currently used in the market are to be based on
SRAM Base techniques, because SRAM has the characteristics of data are lost in power down, its internal logic of FPGA power down will also disappear.Cause
This, generally requires nonvolatile memory such as EPROM, FLASH outside using piece come storage program, upper electricity in FPGA product designs
FPGA therefrom reads configuration data afterwards.In order to which into configuration chip, download program is often needed into external interface and cable, such as
JTAG and the corresponding interface download.In actual applications, FPGA products may be inconvenient to dismantle or external cable, upgrade
Or when safeguarding, if with conventional method more new procedures, it will seem it is sufficiently complex with it is difficult, or even some are brought not to system
The problem of necessary.
PCI (Peripheral Component Interconnect) bus is 1992 by peripheral parts interconnected specialty
(Peripheral Component Interconnect Special Interest Group, PCI-SIG) is organized to propose
A kind of local bus standard, it, which instead of previous isa bus, becomes second generation IO buses.From data width, PCI is total
Line has 32bit, 64bit point；From bus speed point, there is two kinds of 33MHz, 66MHz, widely used at present be 32-bit,
33MHz pci bus.Pci bus has the advantages that transmission speed is high, stability is high, compatibility is good, is widely used in digitized map
Shape, image and speech processes, and the field such as high-speed real data acquisition and processing.PCIe(Peripheral
ComponentInterconnect Express) bus is on the advantages of inheriting second generation bus architecture, using serial
The technology such as transmission and Delamination Transmission, and a kind of third generation IO buses that developed, it is the EBI of current main flow.Its energy
Realize that the serial, communication of point-to-point, the single channel theoretical peak bandwidth of the PCIe buses of the third generation have reached between equipment
984MB/s.Due to PCIe buses, to provide high speed bandwidth, expansible, high efficiency, high stability, etc. compatible with PCI many excellent
Gesture, its application is from traditional PC and graphics workstation field to external expansion, in server, storage, route, more displays
Very extensive application is obtained in device calculating and industrial embedded system.
At present, the download program of traditional FPGA is all that download program is arrived using jtag interface
In FPGA configuration chip.This downloading mode is suitable for the production phase of laboratory debugging and product.But when product is handed over
After paying and after installation, if necessary to carry out FPGA program renewals, then need circuit board to disassemble, then connect in jtag interface
Upper download cable carries out download program.When systematic comparison is complicated, the dismounting of circuit board can cause the decline of system reliability, even
It can trigger the problem of new.In addition, the installation environment of equipment may not allow the entrance of personnel, such as high temperature, strong radiation environment.Work as production
When product quantity is bigger, send someone to handle the FPGA programs of equipment caused by human cost will be very huge.
The content of the invention
The invention aims to solve prior art to carry out when FPGA programs update, it is necessary to dismantle down circuit board
Come, then connecting download cable in jtag interface carries out download program；When systematic comparison is complicated, the dismounting of circuit board can cause be
The decline for reliability of uniting, the installation environment of equipment may not allow the entrance of personnel, and when product quantity is bigger, send someone
The problem of human cost caused by being handled the FPGA programs of equipment will be very huge, and the one kind proposed is based on
The FPGA program downloading systems and method of PCI or PCIe buses.
Above-mentioned goal of the invention is achieved through the following technical solutions：
A kind of FPGA program downloading systems based on PCI/PCIe buses, including host computer, FPGA and EPCS configuration chips；
Carried out data transmission between host computer and FPGA by PCI/PCIe buses；FPGA includes PCI/PCIe bus marcos
Device, Avalon buses, EPCS controllers and user-defined functional unit；
Host computer is connected by PCI/PCIe buses with PCI/PCIe bus control units, PCI/PCIe bus control units with
Avalon buses are connected, and Avalon buses are connected with user-defined functional unit and EPCS controllers respectively, EPCS controls
Device is connected with EPCS configuration chips；
FPGA is field programmable gate array；
Pci bus is PCI bus；
PCIe buses are peripheral parts interconnected high-speed bus；
EPCS is erasable programmable serial storage.
A kind of FPGA program down-loading methods based on PCI/PCIe buses are specifically to be prepared according to following steps：
Step 1: start；
Step 2: open the FPGA configuration file of flash forms to be downloaded using the fopen functions of C language and treat down
The NiosII project files of the flash forms of load；
Step 3: by the FPGA configuration file of flash forms to be downloaded and the NiosII works of flash forms to be downloaded
Journey file data is converted into that both are merged into a binary format file after binary data, draws the binary system after merging
Formatted file；
Step 4: the binary format file after merging is read into calculator memory using the fread functions of C language；
Step 5: host computer is called in the alt_epcs_flash_write functions control FPGA in Altera function libraries
Binary format file write-in EPCS in calculator memory is configured chip by EPCS controllers；
Step 6: host computer calls the alt_epcs_flash_memcmp functions in Altera function libraries, pass through control
EPCS controllers in FPGA read binary format file in EPCS configuration chips and merge in step 3 after binary system lattice
Formula file simultaneously carries out contrast verification；Verification error, performs step 7；Verification is correct, performs step 8；
Step 7: error number performs step 5 when being 1, during more than or equal to 2, step 9 is performed；
Step 8: download program success；Perform step 10；
Step 9: download program fails；Perform step 10；
Step 10: terminate；
FPGA is field programmable gate array；
Pci bus is PCI bus；
PCIe buses are peripheral parts interconnected high-speed bus；
EPCS is erasable programmable serial storage.
Invention effect
For problem above, this programme proposes a kind of based on the FPGA program downloading systems of PCI or PCIe buses and side
Method, the FPGA boards using interfaces such as PCI/PXI/CPCI/PC104 or PCIe/PXIE are primarily adapted for use in, this programme is according to PCI
The characteristics of with PCIe boards, realize FPGA download programs directly by pci bus or PCIe buses directly from host computer
Into FPGA configuration chip, without carrying out board dismounting and external JATG download cables, therefore can solve tradition well
The inconvenience of JTAG downloading modes, the dismounting of circuit board or the decline of system reliability caused by external download cable are avoided,
The entrance of personnel may not be allowed or when product quantity is bigger by solving the installation environment of equipment, be sent someone to equipment
FPGA programs are updated human cost will be very huge the problem of caused by processing, to the FPGA products of practical application
Maintenance and upgrade is provided convenience.According to actual test, enter what line program renewal was spent to FPGA boards using this downloading mode
Time, Billy shorten 80% with traditional JTAG downloading modes renewal FPGA programs, high degree improve system update and
The efficiency of maintenance, at the same avoid because more new procedures and caused by the stability of a system decline.The hardware block diagram of system is such as
Shown in Fig. 1, with the FPGA of altera corp and EPCS (Erasable Programmable Configurable in figure
Serial) Flash is described in detail exemplified by configuring chip.
Brief description of the drawings
Fig. 1 is the FPGA program downloading system hardware structure diagrams based on PCI/PCIe buses；
Fig. 2 is the upper computer software surface chart of the FPGA program downloading systems based on PCI/PCIe buses；
Fig. 3 is flow chart of the present invention；
Fig. 4 is to change process display figure of the sof files into flash file；
Fig. 5 is to change process display figure of the elf files into flash file；
Fig. 6 is to open the display figure after upper computer software success；
Fig. 7 is the FPGA configuration file selection interface display figure of flash forms to be downloaded；
Fig. 8 is host computer interface display figure after the FPGA configuration file of flash forms to be downloaded is opened successfully；
Fig. 9 is host computer interface display figure when choosing " NiosII programs " option；
Figure 10 is the NiosII program files display figure for opening flash forms to be downloaded；
Figure 11 is host computer interface display figure after the NiosII program files of flash forms to be downloaded are opened successfully；
Figure 12 is that information columns show download program state diagram；
Figure 13 is that download program completes backed off after random upper computer software display figure.
Embodiment
Embodiment one：A kind of FPGA program downloading systems based on PCI/PCIe buses of present embodiment, bag
Include host computer, FPGA and EPCS configuration chips；The hardware block diagram of system is as shown in figure 1, with altera corp in figure
It is described in detail exemplified by FPGA and EPCS Flash configuration chips；
Carried out data transmission between host computer and FPGA by PCI/PCIe buses；Host computer in the system is calculating
Machine；FPGA includes PCI/PCIe bus control units, Avalon buses, EPCS controllers and user-defined functional unit
(user needs oneself to add according to actual development, such as analog acquisition function, switch acquisition function, 1553B monitoring bus
Function etc.)；
Host computer is connected by PCI/PCIe buses with PCI/PCIe bus control units, PCI/PCIe bus control units with
Avalon buses are connected, and Avalon buses are connected with user-defined functional unit and EPCS controllers respectively, EPCS controls
Device is connected with EPCS configuration chips；
FPGA is field programmable gate array；
Pci bus is PCI bus；
PCIe buses are peripheral parts interconnected high-speed bus；
EPCS is erasable programmable serial storage；
Avalon buses are a kind of bus on chip that altera corp defines, and realize the interconnection of each component inside FPGA；
EPCS configures chip-stored FPGA configuration file and NiosII project files, EPCS configuration chip connection EPCS controls
Device；FPGA configuration file and NiosII project files are used to configure FPGA, and FPGA is realized by EPCS controllers and EPCS is configured
The access and control of chip.
Upper computer software interface such as Fig. 2, the function that the host computer is mainly realized have：Select the FPGA journeys to be downloaded to EPCS
Preface part, the Read-write Catrol of EPCS chips, board state are shown and some important informations of system are shown.
Embodiment two：Illustrate present embodiment with reference to Fig. 3, one kind of present embodiment is based on PCI/PCIe buses
FPGA program down-loading methods, specifically according to following steps prepare：
Step 1: start；
Step 2: open the FPGA configuration file of flash forms to be downloaded using the fopen functions of C language and treat down
The NiosII project files of the flash forms of load；
Step 3: by the FPGA configuration file of flash forms to be downloaded and the NiosII works of flash forms to be downloaded
Journey file data is converted into that both are merged into a binary format file after binary data, draws the binary system after merging
Formatted file；
Step 4: the binary format file after merging is read into calculator memory using the fread functions of C language；
Step 5: host computer is called in the alt_epcs_flash_write functions control FPGA in Altera function libraries
Binary format file write-in EPCS in calculator memory is configured chip by EPCS controllers；
Step 6: host computer calls the alt_epcs_flash_memcmp functions in Altera function libraries, pass through control
EPCS controllers in FPGA read binary format file in EPCS configuration chips and merge in step 3 after binary system lattice
Formula file simultaneously carries out contrast verification；Verification error, performs step 7；Verification is correct, performs step 8；
Step 7: error number performs step 5 when being 1, during more than or equal to 2, step 9 is performed；
Step 8: download program success；Perform step 10；
Step 9: download program fails；Perform step 10；
Step 10: terminate；
FPGA is field programmable gate array；
PCI (Peripheral Component Interconnect) bus is PCI bus；
PCIe (Peripheral Component Interconnect Express) bus is peripheral parts interconnected high speed
Bus；
EPCS (Erasable Programmable Configurable Serial) serially deposits for erasable may be programmed
Reservoir.
Embodiment three：Present embodiment is unlike embodiment two：C languages are utilized in the step 2
The fopen functions of speech open the FPGA configuration file of flash forms and the NiosII works of flash forms to be downloaded to be downloaded
Journey file；Detailed process is：
In the design due to by download program into EPCS Flash, so selection program file to be downloaded must be
Suitable for the fixed file format of Flash devices, the design of this host computer employs conventional .flash formatted files, generally can be with
Utilize such as Flash downloaders of the instrument in NiosII Integrated Development softwares (Flash Programmer) or command Window
(ShellCommand) the NiosII project files of the FPGA configuration file of .sof forms to be downloaded and .elf forms are changed
Into the FPGA configuration file and NiosII project files of corresponding flash forms, the fopen of C language is then utilized in host computer
Function opens the FPGA configuration file of flash forms to be downloaded and the NiosII project files of flash forms to be downloaded, institute
It is computer to state host computer.
Other steps and parameter are identical with embodiment two.
Embodiment four：Present embodiment is unlike embodiment two or three：Will in the step 3
The NiosII project files of the FPGA configuration file of flash forms to be downloaded and flash forms to be downloaded are converted into two and entered
Both are merged into a binary format file after data processed, draws the binary format file after merging；Detailed process is：
In the NiosII project files of the FPGA configuration file of flash forms to be downloaded and flash forms to be downloaded
Data be character format, open both of these documents respectively using the fopen functions of C language in host computer and utilize fread
Function reads FPGA configuration file data and NiosII project file data, then according to character data and two in ASCII character table
The FPGA configuration file data read and NiosII project files data are converted into by the corresponding relation of binary data respectively
Binary format data, finally merge both, recycle fwrite functions to write data into a new binary format text
Part, draw the binary format file after merging.
Other steps and parameter are identical with embodiment two or three.
Embodiment five：Present embodiment is unlike embodiment two, three or four：In the step 5
Host computer calls the EPCS controllers in the alt_epcs_flash_write functions control FPGA in Altera function libraries to count
Binary format file write-in EPCS configuration chips in calculation machine internal memory；Detailed process is：
Host computer is called in the function library (being carried during installation NiosII Integrated Development softwares) that altera corp provides
Alt_epcs_flash_write functions, host computer will will be calculated by the EPCS controllers in PCI/PCIe bus marcos FPGA
In binary format file write-in EPCS configuration chips in machine internal memory.
After download program success, the board after more new procedures is obtained, the board FPGA after more new procedures is restarted and just will
The configurator configured from EPCS after renewal is read in chip completes the configuration to FPGA, and now user is it is seen that after renewal
The running situation of program.
Other steps and parameter are identical with embodiment two, three or four.
Other steps and parameter are identical with embodiment two, three, four or five.
Beneficial effects of the present invention are verified using following examples：
Embodiment one：
Using a kind of FPGA program down-loading methods based on PCI or PCIe buses of the present invention, specifically according to following step
Suddenly prepare：
Step 1：.sof file (this example for being generated required Quartus II using Nios II Shell Command
In Test.sof) and NiosII IDE generation elf files (Test.elf in this example) be converted to .flash formatted files,
Fig. 4 is to change process of the sof files into flash file；Fig. 5 is to change process of the elf files into flash file；
Step 2：Upper computer software is opened, such as Fig. 6 after opening successfully；
Step 3：" opening file " button in " FPGA configurators (.flash) " a line is clicked on, file selection occurs
Interface, find the flash form FPGA files for needing to download and open, as shown in Figure 7；Host computer interface after File Open success
Such as Fig. 8；
Step 4：Square frame before " NiosII programs (.flash) " is chosen in interface, and the row " opens file after choosing
Button " is available, clicks on to open NiosII program files, as shown in Figure 9；After there is file selection interface, selection needs
The NiosII program files of the flash forms to be downloaded simultaneously are opened, such as Figure 10；Host computer interface is shown such as after File Open success
Figure 11；
Step 5：" starting to download " button is clicked on, software starts execution and downloaded, and all buttons will in host computer interface
Unavailable, information columns show download program state, such as Figure 12：
Step 6：Wait download program complete, when host computer interface information columns prompt " download program completion " and
When button reverts to state before program starts to download, representation program, which is downloaded, to be completed, and can now be exited upper computer software, such as be schemed
Shown in 13.Now restart the configurator that FPGA boards will just import FPGA newest download from EPCS.
The present invention can also have other various embodiments, in the case of without departing substantially from spirit of the invention and its essence, this area
Technical staff works as can make various corresponding changes and deformation according to the present invention, but these corresponding changes and deformation should all belong to
The protection domain of appended claims of the invention.
Claims (4)
1. a kind of FPGA program down-loading methods based on PCI/PCIe buses, it is characterised in that a kind of based on PCI/PCIe buses
FPGA program down-loading methods are specifically to be prepared according to following steps：
Step 1: start；
Step 2: open the FPGA configuration file of flash forms to be downloaded and to be downloaded using the fopen functions of C language
The NiosII project files of flash forms；
It is Step 3: the FPGA configuration file of flash forms to be downloaded and the NiosII engineerings of flash forms to be downloaded is literary
Number of packages evidence is converted into that both are merged into a binary format file after binary data, draws the binary format after merging
File；
Step 4: the binary format file after merging is read into calculator memory using the fread functions of C language；
Step 5: host computer calls the EPCS in the alt_epcs_flash_write functions control FPGA in Altera function libraries
Binary format file write-in EPCS in calculator memory is configured chip by controller；
Step 6: host computer calls the alt_epcs_flash_memcmp functions in Altera function libraries, by controlling in FPGA
EPCS controllers read EPCS configuration chip in binary format file with merge in step 3 after binary format file
And carry out contrast verification；Verification error, performs step 7；Verification is correct, performs step 8；
Step 7: error number performs step 5 when being 1, during more than or equal to 2, step 9 is performed；
Step 8: download program success；Perform step 10；
Step 9: download program fails；Perform step 10；
Step 10: terminate；
FPGA is field programmable gate array；
Pci bus is PCI bus；
PCIe buses are peripheral parts interconnected high-speed bus；
EPCS is erasable programmable serial storage.
A kind of 2. FPGA program down-loading methods based on PCI/PCIe buses according to claim 1, it is characterised in that：It is described
In step 2 the FPGA configuration file of flash forms to be downloaded and to be downloaded is opened using the fopen functions of C language
The NiosII project files of flash forms；Detailed process is：
The NiosII project files of the FPGA configuration file of .sof forms to be downloaded and .elf forms are converted into corresponding flash
The FPGA configuration file and NiosII project files of form, then opened in host computer using the fopen functions of C language under treating
The NiosII project files of the FPGA configuration file of the flash forms of load and flash forms to be downloaded.
A kind of 3. FPGA program down-loading methods based on PCI/PCIe buses according to claim 2, it is characterised in that：It is described
By the FPGA configuration file of flash forms to be downloaded and the NiosII project files of flash forms to be downloaded in step 3
It is converted into that both are merged into a binary format file after binary data, draws the binary format file after merging；
Detailed process is：
Number in the NiosII project files of the FPGA configuration file of flash forms to be downloaded and flash forms to be downloaded
According to for character format, both of these documents is opened respectively using the fopen functions of C language in host computer and utilizes fread functions
FPGA configuration file data and NiosII project file data are read, then according to character data and binary system in ASCII character table
The FPGA configuration file data read and NiosII project files data are converted into two and entered by the corresponding relation of data respectively
Formatted data processed, finally merges both, recycles fwrite functions to write data into a new binary format file, obtains
The binary format file gone out after merging.
A kind of 4. FPGA program down-loading methods based on PCI/PCIe buses according to claim 3, it is characterised in that：It is described
Host computer calls the EPCS controls in the alt_epcs_flash_write functions control FPGA in Altera function libraries in step 5
Binary format file write-in EPCS in calculator memory is configured chip by device processed；Detailed process is：
Host computer calls the alt_epcs_flash_write functions in the function library that altera corp provides, and host computer will pass through
EPCS controllers in PCI/PCIe bus marcos FPGA configure the binary format file write-in EPCS in calculator memory
In chip.
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| CN106528217B (en) * | 2016-10-26 | 2019-12-06 | 武汉船舶通信研究所 | on-site programmable gate array program loading system and method |
| CN108228221A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of programmable logic online upgrading method based on 1553B buses |
| CN108400899A (en) * | 2018-06-08 | 2018-08-14 | 山东超越数控电子股份有限公司 | A kind of remote update system and method for FPGA |
| CN108804232B (en) * | 2018-06-26 | 2022-02-18 | 郑州云海信息技术有限公司 | Method, host server and system for supporting cloud FPGA deployment |
| CN109542478A (en) * | 2018-11-09 | 2019-03-29 | 中电科仪器仪表有限公司 | A kind of system and method updating FPGA program in SPI Flash |
| CN109599048A (en) * | 2019-01-09 | 2019-04-09 | 惠科股份有限公司 | A kind of display device and its driving method and display |
| CN109918325B (en) * | 2019-03-06 | 2020-12-04 | 苏州浪潮智能科技有限公司 | Interface conversion bridge based on Avalon bus, interface conversion method and system |
| CN109901506B (en) * | 2019-03-19 | 2020-10-30 | 浙江中控研究院有限公司 | Configurable PLC based on PCIe bus |
| CN110955620B (en) * | 2019-12-13 | 2023-06-13 | 中国兵器装备集团自动化研究所 | 1553B bus protocol system based on PCIE |
| CN111414325B (en) * | 2020-02-29 | 2021-09-17 | 苏州浪潮智能科技有限公司 | Method for converting Avalon bus into Axi4 bus |
| CN114328342B (en) * | 2020-09-29 | 2023-09-26 | 中国船舶集团有限公司第七二四研究所 | Novel program control configuration method for PCIe heterogeneous accelerator card |
| CN117692344B (en) * | 2024-02-02 | 2024-04-16 | 成都大征创智科技有限公司 | Network equipment simulation method based on FPGA code compiling |
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| KR100445636B1 (en) * | 2002-06-17 | 2004-08-25 | 삼성전자주식회사 | Computer system test device using FPGA and programmable memory modules and the test method thereof |
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| CN201628870U (en) * | 2010-04-02 | 2010-11-10 | 广西民族师范学院 | High-precision multi-channel temperature measuring device |
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