CN105279094A - NAND Flash operation processing method, NAND Flash operation processing device and logic device - Google Patents
NAND Flash operation processing method, NAND Flash operation processing device and logic device Download PDFInfo
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- CN105279094A CN105279094A CN201410253586.2A CN201410253586A CN105279094A CN 105279094 A CN105279094 A CN 105279094A CN 201410253586 A CN201410253586 A CN 201410253586A CN 105279094 A CN105279094 A CN 105279094A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F12/02—Addressing or allocation; Relocation
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Abstract
The invention provides a NAND Flash operation processing method, a NAND Flash operation processing device and a logic device. The NAND Flash operation processing method comprises the steps of establishing an address protecting table which protects a NAND Flash protection zone; determining whether an address for operating the NAND Flash exists in the address protecting table; and on condition that determination result is yes, shielding the operation to the NAND Flash. The NAND flash operation processing method, the NAND Flash operation processing device and the logic device settle problems of mistaken erasing and mistaken writing on the NAND Flash in related technology. Furthermore the NAND Flash operation processing method, the NAND Flash operation processing device and the logic device have effects of effectively preventing damage of an important storage area and effectively improving reliability of data stored in the NAND Flash.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of NANDFlash operation processing method, device and logical device.
Background technology
More common nonvolatile memory comprises NORFlash (NOR flash memory) and NANDFlash (nand flash memory) two kinds at present, compared to NORFlash, NANDFlash storer possess writing speed faster than NOR Flash memory a lot, erasing speed is fast more than NOR Flash memory, monolithic capacity is comparatively large, unit memory capacity low cost and other advantages, is applicable to the storage of mass data.Due to technical development demand and cost aspect, NANDFlash has had and has applied very widely in various electronic product.
Select in the occasion of NANDFlash various, improper operation from software likely causes NANDFlash to be erased during normal operation, more serious consequence can be caused, especially cannot be started when system even may causes during erroneous erasure for the Boot of System guides and system cloud gray model version.
Therefore, in the related, there is the insecure problem caused with write by erroneous erasure in NANDFlash.
Summary of the invention
The invention provides a kind of NANDFlash operation processing method, device and logical device, there is to solve NANDFlash in correlation technique the insecure problem caused with write by erroneous erasure.
According to an aspect of the present invention, provide a kind of NANDFlash operation processing method, comprising: set up the address protection table that NANDFlash protected location is protected; Judge whether the address operated described NANDFlash is present in described address protection table; When judged result is for being, shield the operation to described NANDFlash.
Preferably, the described address protection table set up described NANDFlash protected location is protected comprises: divide rank to the significance level that the zones of different of described NANDFlash protected location is protected; According to the address that the described zones of different divided after rank is corresponding, set up address protection table.
Preferably, after setting up the described address protection table that described NANDFlash protected location is protected, also comprise: described address protection table is upgraded.
Preferably, judge whether the address operated described NANDFlash is present in described address protection table and comprises: resolve the signal command that described NANDFlash is operated from central processor CPU; More described signal command for the address of described NANDFlash whether mate with the address in described address protection table; In the event of a match, determine whether the address operated described NANDFlash is present in described address protection table.
Preferably, shield the operation of described NANDFlash is comprised: judge whether to the action type of the operation of described NANDFlash be retouching operation; When judged result is for being, shield the operation to described NANDFlash.
According to a further aspect in the invention, provide a kind of NANDFlash operational processes device, comprising: set up module, for setting up the address protection table protected NANDFlash protected location; Judge module, for judging whether the address operated described NANDFlash is present in described address protection table; Shroud module, for when the judged result of described judge module is for being, shields the operation to described NANDFlash.
Preferably, described module of setting up comprises: division unit, divides rank for the significance level protected the zones of different of described NANDFlash protected location; Set up unit, divide address corresponding to the described zones of different after rank for foundation, set up address protection table.
Preferably, this device also comprises: update module, for upgrading described address protection table.
Preferably, described judge module comprises: resolution unit, for resolving the signal command operated described NANDFlash from central processor CPU; Comparing unit, for more described signal command for the address of described NANDFlash whether mate with the address in described address protection table; Determining unit, in the event of a match, determines whether the address operated described NANDFlash is present in described address protection table.
Preferably, described shroud module comprises: judging unit, for judging whether to the action type of the operation of described NANDFlash be retouching operation; Screen unit, for when the judged result of described judging unit is for being, shields the operation to described NANDFlash.
In accordance with a further aspect of the present invention, provide a kind of logical device, comprise the device described in above-mentioned any one.
By the present invention, adopt the address protection table set up and NANDFlash protected location is protected; Judge whether the address operated described NANDFlash is present in described address protection table; When judged result is for being, the operation of shielding to described NANDFlash, solve NANDFlash in correlation technique and there is the insecure problem of storage caused with write by erroneous erasure, and then reach and can not only effectively avoid important storage area damaged, and effectively improve the effect that NANDFlash stores the reliability of data.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, and form a application's part, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the process flow diagram of the NANDFlash operation processing method according to the embodiment of the present invention;
Fig. 2 is the structured flowchart of the NANDFlash operational processes device according to the embodiment of the present invention;
Fig. 3 is the structured flowchart setting up module 22 in the NANDFlash operational processes device according to the embodiment of the present invention;
Fig. 4 is the preferred structure block diagram of the NANDFlash operational processes device according to the embodiment of the present invention;
Fig. 5 is the structured flowchart of judge module 24 in the NANDFlash operational processes device according to the embodiment of the present invention;
Fig. 6 is the structured flowchart of shroud module 26 in the NANDFlash operational processes device according to the embodiment of the present invention;
Fig. 7 is the structured flowchart of the logical device according to the embodiment of the present invention;
Fig. 8 is wiped by mistake and is missed the configuration diagram of write according to the NANDFlash that prevents of the embodiment of the present invention;
Fig. 9 is wiped by mistake and is missed the implementation method function declaration figure of write according to the NANDFlash that prevents of the embodiment of the present invention;
Figure 10 is wiped by mistake and is missed the process flow diagram of the implementation method of write according to the NANDFLASH that prevents of the embodiment of the present invention;
Figure 11 is wiped by mistake and is missed the process flow diagram of the increase of the implementation method of write or amendment protected location according to the NANDFLASH that prevents of the embodiment of the present invention.
Embodiment
Hereinafter also describe the present invention in detail with reference to accompanying drawing in conjunction with the embodiments.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.
Provide a kind of NANDFlash operation processing method in the present embodiment, Fig. 1 is the process flow diagram of the NANDFlash operation processing method according to the embodiment of the present invention, and as shown in Figure 1, this flow process comprises the steps:
Step S102, sets up the address protection table protected NANDFlash protected location;
Step S104, judges whether the address operated NANDFlash is present in address protection table;
Step S106, when judged result is for being, shields the operation to NANDFlash.
Pass through above-mentioned steps; protect according to setting up the storage area of address protection table to NANDFlash; not only efficiently solve in correlation technique and NANDFlash region is not protected; the storage causing NANDFlash to be caused by erroneous erasure and write is unreliable; even may cause the problem that system cannot start, and effectively improve the effect that NANDFlash stores the reliability of data.
When the address protection table that foundation is protected NANDFlash protected location, can adopt various ways, such as, when needs are treated with a certain discrimination each protection zone, the significance level can protected the zones of different of NANDFlash protected location divides rank; According to the address that the zones of different divided after rank is corresponding, set up address protection table.By such process, make the data of NANDFlash area stores have the differentiation of significance level, such as, that can not delete for particular importance can arrange the highest by its protection level, can arrange lower a little for generally important.
Preferably; after setting up the address protection table that NANDFlash protected location is protected; can also upgrade address protection table; such as; in different periods, the importance of NANDFlash storage area can change, therefore; need to upgrade amendment accordingly to address protection table, to adapt to the needs of different times.
When whether the address judging to operate NANDFlash is present in address protection table, the signal command that NANDFlash is operated from central processor CPU first can be resolved; Comparison signal order for the address of NANDFlash whether mate with the address in address protection table; In the event of a match, determine whether the address to NANDFlash operates is present in address protection table.
Preferably; when shielding the operation to NANDFlash; for preventing causing significant data (data that protection corresponding region, address stores) erasing or the operation of amendment (such as; some simple read operations) also shield, cause the possibility affecting Consumer's Experience.Before whether the address judging to operate NANDFlash is present in address protection table, can also judge whether to the action type of the operation of NANDFlash be retouching operation; When judged result is for being, the just operation of shielding to NANDFlash.
Additionally provide a kind of NANDFlash operational processes device in the present embodiment, this device is used for realizing above-described embodiment and preferred implementation, has carried out repeating no more of explanation.As used below, term " module " can realize the software of predetermined function and/or the combination of hardware.Although the device described by following examples preferably realizes with software, hardware, or the realization of the combination of software and hardware also may and conceived.
Fig. 2 is the structured flowchart of the NANDFlash operational processes device according to the embodiment of the present invention, and as shown in Figure 2, this device comprises sets up module 22, judge module 24 and shroud module 26, is described below to this device.
Set up module 22, for setting up the address protection table protected NANDFlash protected location; Judge module 24, is connected to and above-mentionedly sets up module 22, for judging whether the address operated NANDFlash is present in address protection table; Shroud module 26, is connected to above-mentioned judge module 24, for when the judged result of judge module is for being, shields the operation to NANDFlash.
Fig. 3 is the structured flowchart setting up module 22 in the NANDFlash operational processes device according to the embodiment of the present invention, and as shown in Figure 3, this is set up module 22 and comprises division unit 32 and set up unit 34, below this is set up to module 22 and is described.
Division unit 32, divides rank for the significance level protected the zones of different of NANDFlash protected location; Set up unit 34, be connected to above-mentioned division unit 32, divide address corresponding to the zones of different after rank for foundation, set up address protection table.
Fig. 4 is the preferred structure block diagram of the NANDFlash operational processes device according to the embodiment of the present invention, and as shown in Figure 4, this device, except comprising all structures shown in Fig. 2, also comprises: update module 42, is described below to this update module 42.
Update module 42, is connected to and above-mentionedly sets up module 22 and judge module 24, for upgrading address protection table.
Fig. 5 is the structured flowchart of judge module 24 in the NANDFlash operational processes device according to the embodiment of the present invention, and as shown in Figure 5, this judge module 24 comprises: resolution unit 52, comparing unit 54 and determining unit 56, is described below to this judge module 24.
Resolution unit 52, for resolving the signal command operated NANDFlash from central processor CPU; Comparing unit 54, is connected to above-mentioned resolution unit 52, for comparison signal order for the address of NANDFlash whether mate with the address in address protection table; Determining unit 56, is connected to above-mentioned comparing unit 54, in the event of a match, determines whether the address to NANDFlash operates is present in address protection table.
Fig. 6 is the structured flowchart of shroud module 24 in the NANDFlash operational processes device according to the embodiment of the present invention, and as shown in Figure 6, this shroud module 26 comprises: judging unit 62 and screen unit 64, is described below to this shroud module 26.
Judging unit 62, for judging whether to the action type of the operation of NANDFlash be retouching operation; Screen unit 64, is connected to above-mentioned judging unit 62, for when the judged result of judging unit is for being, shields the operation to NANDFlash.
Fig. 7 is the structured flowchart of the logical device according to the embodiment of the present invention, and as shown in Figure 7, this logical device 70 comprises the NANDFlash operational processes device 72 of above-mentioned any one.
For in correlation technique; owing to not protecting the specific region of nand flash memory; thus cause nand flash memory to exist and write mistakenly or wipe and cause the insecure problem of storage; in the present embodiment; specific region on NANDFlash is protected by the implementation method wiping and miss write by mistake by a kind of NANDFlash of preventing; such as; the way of address filtering is adopted to protect specific memory section; thus effectively prevent important storage area by erroneous erasure and write, add the reliability of electronic product.
This prevents NANDFlash from being wiped by mistake and missing the implementation method of programming (write) by mistake, by the method for this address filtering and shielding, to avoid particular memory region not damaged when faulty operation.Following processing mode can be adopted realize:
To in the access of NANDFlash, interface signal being resolved for the address protection table of NANDFlash protected location by setting up one, if having the erasing to protected interval or programming operation, then the operation shield of correspondence being fallen.Fig. 8 is wiped by mistake and is missed the configuration diagram of write according to the NANDFlash that prevents of the embodiment of the present invention, as shown in Figure 8, the physical feature that the device that this implementation method relates to comprises mainly comprises: central processing unit (CentralProcessingUnit, referred to as CPU), logical device (field programmable gate array (FieldProgrammableGateArray, referred to as FPGA) or CPLD (ComplexProgrammableLogicDevice, referred to as CPLD)), NANDFlash.
In this scenario, CPU by the inside Flash of control interface access logic device, can provide Flash interface to logical device simultaneously.The interface of CPU access logic device inside Flash can be various types of, and the interface of the forms such as such as IIC, LOCALBUS, SPI, these depend on the interface that processor provides.
Logical device can select FPGA also can select CPLD, and currently marketed various logic device all possesses built-in Flash, and address protection table leaves in the Flash of logical device, and CPU can to the read and write access of address protection table and storage.
In general, protected location may be starting factor district, Boot district, large paper edition district, and the memory block etc. of other important information.Physics block address corresponding to these protected locations is all left in address protection table.RowAddress corresponding to these block addresses can extract by logical device, compares with the RowAddress in NANDFlash port, once identical, just will wipe or program command shielding.
Preferably, the program also comprises foundation and the renewal of protection address table, the signal resolution of NANDFlash interface, by mistake erasing and the shielding missing program command, and state instruction etc.
Relative in correlation technique, generally adopt the address space that staggers to make Flash can not be accessed to the protection of flash storage, and this mode be confined to the application scenario of NORFlash.By the mode of address above mentioned protection table; achieve and erasing by mistake and the protection of by mistake programming are prevented to the memory block of starting factor district on NANDFlash, Boot district, large paper edition district and other important information etc.; by this guard method; to in the accessing operation of NANDFlash; software is not needed to do extra intervention; reduce the complicacy of software, decrease the workload of processor, improve system reliability.
Below in conjunction with accompanying drawing, the embodiment of the present invention is described.
Fig. 9 is wiped by mistake and is missed the implementation method function declaration figure of write according to the NANDFlash that prevents of the embodiment of the present invention; as shown in Figure 9; based on framework shown in Fig. 1; the building blocks of function of the program comprises: 101 processors (CPU); 102NANDFlash, 103 address protection tables, 104NANDFlashI/O interface resolver; 105NANDFlashI/O address filter, 106 Access status indicators.
101 processors (CPU) by 103 address protection tables in the inside Flash of control interface access logic device, can provide Flash interface to logical device simultaneously.The interface of CPU access logic device inside Flash can be various types of, and the interface of the forms such as such as IIC, LOCALBUS, SPI, the type of physical interface depends on CPU.
Logical device can select FPGA also can select CPLD, and CPU can conduct interviews (read-write) to 103 address protection tables in the built-in Flash of logical device.The signal of 104NANDFlashI/O interface resolver to the Flash interface from CPU in logical device is resolved; the address parsed and comparing in 103 address protection tables, 105NANDFlashI/O address filter determines whether shield erasing or program command.
What 106 Access status indicator instructions were current forbids the state wiping, programme or allow normal access.
At the head of 103 address protection tables, have specifically the need of the mark of protection.This mark can be different from value when Flash does not write with check bit.
In this programme, memory device is that each block on 102NANDFlash, 102NANDFlash can be read, wipes, programmes.NANDFlash be used for storing starting factor code, Boot code, large paper edition code, other important information and some other be not too important information etc. relatively.
Figure 10 is wiped by mistake and is missed the process flow diagram of the implementation method of write according to the NANDFLASH that prevents of the embodiment of the present invention, and as shown in Figure 10, this flow process comprises the steps:
Steps A. system reset or after powering on, logical device first makes CPU be in reset mode, wait for that logic reads address protection table;
Step B. logic reads address protection table from built-in Flash;
If step C. reads the interval not needing to protect from the head of address protection table, the mode process that protection address is then logically given tacit consent in code, such as, transparent transmission address and order.Otherwise according to information extraction guard interval in flash;
Step D. logic, according to the guard interval information extracted, determines the address needing to filter, such as, and the RowAddress of protected block;
Step e. the reset of release processor CPU, makes CPU start;
Step F. after processor CPU starts, NANDFlash is accessed, logic is by interface message collection, first the type of order is judged, if the order parsed is not Erase (erasing) or Program (program editing write), be then read operation (Read), this order is directly transparent to NANDFlash, normally accesses NANDFlash;
If the order that step G. logical analysis goes out is Erase or Program, then the RowAddress of protected block in comparison step D, if address is not mated, this order is directly transparent to NANDFlash, normally accesses NANDFlash;
If the order that step H. logical analysis goes out is Erase or Program, then the RowAddress of protected block in comparison step D, if matching addresses, masks order accordingly, feeds back to sign register simultaneously, show illegal Erase or Program.
Figure 11 is wiped by mistake and is missed the process flow diagram of the increase of the implementation method of write or amendment protected location according to the NANDFLASH that prevents of the embodiment of the present invention, and as shown in figure 11, if guard interval needs to change, then this flow process comprises the steps:
Steps A. system background starts version updating in NANDFlash;
Step B. notifications logic, removes logical address protection, to all order transparent transmissions in the original protected interval of NANDFLASH arranged;
Step C. system starts the content in down loading updating NANDFlash;
If step D. system downloads upgrades NANDFlash failure, then stop down loading updating, arrange renewal failure flags simultaneously, logic recovers original logical address protection;
Step e. if system downloads upgrades NANDFlash success, then scheduler protection table, arranges simultaneously and is updated successfully mark;
Step F. the protective emblem position of scheduler protection table, indicates the address section that needs are protected;
Step G. logic is filtered according to the address protection table enabling address upgraded.
Obviously, those skilled in the art should be understood that, above-mentioned of the present invention each module or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on network that multiple calculation element forms, alternatively, they can realize with the executable program code of calculation element, thus, they can be stored and be performed by calculation element in the storage device, and in some cases, step shown or described by can performing with the order be different from herein, or they are made into each integrated circuit modules respectively, or the multiple module in them or step are made into single integrated circuit module to realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a NANDFlash operation processing method, is characterized in that, comprising:
Set up the address protection table that NANDFlash protected location is protected;
Judge whether the address operated described NANDFlash is present in described address protection table;
When judged result is for being, shield the operation to described NANDFlash.
2. method according to claim 1, is characterized in that, the described address protection table set up described NANDFlash protected location is protected comprises:
Rank is divided to the significance level that the zones of different of described NANDFlash protected location is protected;
According to the address that the described zones of different divided after rank is corresponding, set up address protection table.
3. method according to claim 1, is characterized in that, after setting up the described address protection table protected described NANDFlash protected location, also comprises:
Described address protection table is upgraded.
4. method according to claim 1, is characterized in that, judges whether the address operated described NANDFlash is present in described address protection table and comprises:
Resolve the signal command that described NANDFlash is operated from central processor CPU;
More described signal command for the address of described NANDFlash whether mate with the address in described address protection table;
In the event of a match, determine whether the address operated described NANDFlash is present in described address protection table.
5. method according to any one of claim 1 to 4, is characterized in that, shields and comprises the operation of described NANDFlash:
Judge whether to the action type of the operation of described NANDFlash be retouching operation;
When judged result is for being, shield the operation to described NANDFlash.
6. a NANDFlash operational processes device, is characterized in that, comprising:
Set up module, for setting up the address protection table protected NANDFlash protected location;
Judge module, for judging whether the address operated described NANDFlash is present in described address protection table;
Shroud module, for when the judged result of described judge module is for being, shields the operation to described NANDFlash.
7. device according to claim 6, is characterized in that, described module of setting up comprises:
Division unit, divides rank for the significance level protected the zones of different of described NANDFlash protected location;
Set up unit, divide address corresponding to the described zones of different after rank for foundation, set up address protection table.
8. device according to claim 6, is characterized in that, also comprises:
Update module, for upgrading described address protection table.
9. device according to claim 6, is characterized in that, described judge module comprises:
Resolution unit, for resolving the signal command operated described NANDFlash from central processor CPU;
Comparing unit, for more described signal command for the address of described NANDFlash whether mate with the address in described address protection table;
Determining unit, in the event of a match, determines whether the address operated described NANDFlash is present in described address protection table.
10. the device according to any one of claim 6 to 9, is characterized in that, described shroud module comprises:
Judging unit, for judging whether to the action type of the operation of described NANDFlash be retouching operation;
Screen unit, for when the judged result of described judging unit is for being, shields the operation to described NANDFlash.
11. 1 kinds of logical devices, is characterized in that, comprise the device according to any one of claim 6 to 10.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410253586.2A CN105279094A (en) | 2014-06-09 | 2014-06-09 | NAND Flash operation processing method, NAND Flash operation processing device and logic device |
| PCT/CN2014/087232 WO2015188511A1 (en) | 2014-06-09 | 2014-09-23 | Nand flash operation processing method and apparatus, and logic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410253586.2A CN105279094A (en) | 2014-06-09 | 2014-06-09 | NAND Flash operation processing method, NAND Flash operation processing device and logic device |
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| CN105279094A true CN105279094A (en) | 2016-01-27 |
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| CN201410253586.2A Pending CN105279094A (en) | 2014-06-09 | 2014-06-09 | NAND Flash operation processing method, NAND Flash operation processing device and logic device |
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| CN (1) | CN105279094A (en) |
| WO (1) | WO2015188511A1 (en) |
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| CN107608905A (en) * | 2017-09-11 | 2018-01-19 | 杭州中天微系统有限公司 | The method and device of Flash erase/write data |
| CN111966611A (en) * | 2020-08-03 | 2020-11-20 | 南京扬贺扬微电子科技有限公司 | SPI flash memory control chip with logic-to-physical address architecture |
| CN113407453A (en) * | 2021-06-29 | 2021-09-17 | 芯天下技术股份有限公司 | Verification method and device of data protection bit, electronic equipment and storage medium |
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| CN102207913A (en) * | 2011-06-09 | 2011-10-05 | 中兴通讯股份有限公司 | Write protection control method and device in embedded system |
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| CN107145805A (en) * | 2017-03-21 | 2017-09-08 | 芯海科技（深圳）股份有限公司 | A kind of anti-error erasable implementation method of FLASH/MTP internal datas |
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| CN107608905A (en) * | 2017-09-11 | 2018-01-19 | 杭州中天微系统有限公司 | The method and device of Flash erase/write data |
| US11249677B2 (en) | 2017-09-11 | 2022-02-15 | C-Sky Microsystems Co., Ltd. | Method and apparatus for erasing or writing flash data |
| CN111966611A (en) * | 2020-08-03 | 2020-11-20 | 南京扬贺扬微电子科技有限公司 | SPI flash memory control chip with logic-to-physical address architecture |
| CN111966611B (en) * | 2020-08-03 | 2023-12-12 | 南京扬贺扬微电子科技有限公司 | SPI flash memory control chip with logic-to-physical address architecture |
| CN113407453A (en) * | 2021-06-29 | 2021-09-17 | 芯天下技术股份有限公司 | Verification method and device of data protection bit, electronic equipment and storage medium |
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