CN105205017A - Storage controller based on PCIE SSD - Google Patents
Storage controller based on PCIE SSD Download PDFInfo
- Publication number
- CN105205017A CN105205017A CN201510548650.4A CN201510548650A CN105205017A CN 105205017 A CN105205017 A CN 105205017A CN 201510548650 A CN201510548650 A CN 201510548650A CN 105205017 A CN105205017 A CN 105205017A
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- CN
- China
- Prior art keywords
- controller
- pciessd
- ssd
- pcie bus
- memory controller
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a storage controller based on a PCIE SSD. The storage controller is characterized in that the PCIE SSD is used as a second-level cache, and communication among the SSD, a controller CPU (central processing unit) and a memory is realized by the aid of a PCIE bus.
Description
Technical field
The present invention relates to storage hardware field, be specifically related to the memory controller of a kind of Based PC IESSD.
Background technology
In conventional hardware stores, generally comprise controller and disk two large divisions, controller carries out communicating and identifying with disk by SASexpander usually, because disk is all mechanical hard disk, need magnetic head in disk, carry out the address space that tracking finds deposit data in data write or when reading, thus cause IO to postpone.
Along with the development of SSD magnetic disc, in the disk chassis of storage hardware equipment, adopt SSD as L2 cache, be used for storing hot spot data, improve the readwrite performance of memory controller.But be limited to SSD to be communicated with controller by rear end SASexpander backboard, the lifting of performance is also very limited, and the maximum rate of current SAS3.0 is 12Gb/S.Conventional SSD is as the storage architecture of L2 cache
as Fig. 1shown in.
Summary of the invention
In order to solve above technical matters, the invention provides the memory controller of a kind of Based PC IESSD, compared with existing memory device, this device has elevator system readwrite performance, reduces delay, improves the utilization factor of disk chassis, does not affect the advantages such as the I/O performance of driver rack.
The invention provides the memory controller of a kind of Based PC IESSD, it is characterized in that completing communication between SSD and controller CPU, internal memory by PCIE bus.
Further, described memory controller comprises two controller modules.
Further, described controller module is by PCIE bus interconnection.
Further, described controller module is furnished with two channel adapters respectively.
Further, described controller module has two driver interfaces respectively.
Further, described memory controller utilizes PCIESSD as L2 cache.
Further, described PCIESSD is arranged in controller module, does not take disk chassis slot.
Further, described PCIESSD is connected with controller CPU by PCIE bus.
Further, described PCIESSD supports hot plug.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from instructions, or understand by implementing the present invention.Object of the present invention and other advantages by instructions, claims and
in accompanying drawingspecifically noted structure realizes and obtains.
Accompanying drawing explanation
accompanying drawingbe used to provide the further understanding to technical solution of the present invention, and form a part for instructions, be used from the embodiment one of the application and explain technical scheme of the present invention, do not form the restriction to technical solution of the present invention.
fig. 1for prior art SSD is as the storage architecture of L2 cache;
fig. 2for PCIESSD memory controller framework according to an embodiment of the invention
figure.
Embodiment
The present invention is as the memory controller device of a kind of Based PC IESSD, and this device completes communication between SSD and controller CPU, internal memory by PCIE bus.
For making the object, technical solutions and advantages of the present invention clearly understand, hereinafter will be in conjunction with
accompanying drawingembodiments of the invention are described in detail.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combination in any mutually.
as Fig. 2shown in, memory controller framework involved in the present invention comprises two controller modules, and these two modules are by PCIE bus interconnection, and each module is furnished with two channel adapters and two driver interfaces respectively.Memory controller utilizes PCIESSD as L2 cache, and PCIESSD is connected with controller CPU by PCIE bus, and supports hot plug.PCIESSD is arranged in controller, instead of in disk chassis.
Three assemblies, have operating unit, management by district and metadata management, fragment data to store respectively.
Operating unit: to the United Dispatching of write task with the task of reading, process is unified to write operation and read operation;
Management by district and metadata management: manage all burst information and metadata information, burst information and metadata information are stored in NVDIMM, the characteristic guarantee access performance that fast and power-off is not lost by the access speed of NVDIMM and reliability;
Fragment data stores: store all actual fragment datas, these fragment datas are stored on actual hard disk, according to the mode increasing progressively write during write data;
as Fig. 2shown in, when there being write request, carry out burst to write content and be written to by fragment data in fragment data storage, burst information is written in management by district and metadata management assembly; The write request of reality will be converted into completely to the operation increasing write, promote hard disk write performance;
as Fig. 2shown in, when there being reading task, operating unit can obtain the burst situation of data from management by district machine metadata management assembly according to reading of content, read data according to burst situation is actual from fragment data memory module;
It is exactly to sum up the method for the high speed writein based on discrete storage.
Although the embodiment disclosed by the present invention is as above, the embodiment that described content only adopts for ease of understanding the present invention, and be not used to limit the present invention.Those of skill in the art belonging to any the present invention; under the prerequisite not departing from the spirit and scope disclosed by the present invention; any amendment and change can be carried out in the form implemented and details; but scope of patent protection of the present invention, the scope that still must define with appending claims is as the criterion.
Claims (9)
1. a memory controller of Based PC IESSD, is characterized in that, comprising:
The communication between PCIESSD and controller CPU, internal memory is completed by PCIE bus.
2. device according to claim 1, is characterized in that, described memory controller comprises two controller modules.
3. device according to claim 2, is characterized in that, described controller module is by PCIE bus interconnection.
4. device according to claim 2, is characterized in that, described controller module is furnished with two channel adapters respectively.
5. device according to claim 2, is characterized in that, described controller module has two driver interfaces respectively.
6. device according to claim 1, is characterized in that, described memory controller utilizes PCIESSD as L2 cache.
7. device according to claim 6, is characterized in that, described PCIESSD is arranged in controller module, does not take disk chassis slot.
8. device according to claim 6, is characterized in that, described PCIESSD is connected with controller CPU by PCIE bus.
9. device according to claim 6, is characterized in that, affiliated PCIESSD supports hot plug.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510548650.4A CN105205017A (en) | 2015-08-31 | 2015-08-31 | Storage controller based on PCIE SSD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510548650.4A CN105205017A (en) | 2015-08-31 | 2015-08-31 | Storage controller based on PCIE SSD |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105205017A true CN105205017A (en) | 2015-12-30 |
Family
ID=54952711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510548650.4A Pending CN105205017A (en) | 2015-08-31 | 2015-08-31 | Storage controller based on PCIE SSD |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105205017A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107301021A (en) * | 2017-06-22 | 2017-10-27 | 郑州云海信息技术有限公司 | It is a kind of that the method and apparatus accelerated to LUN are cached using SSD |
| CN107977280A (en) * | 2017-12-08 | 2018-05-01 | 郑州云海信息技术有限公司 | Verify that ssd cache accelerate the method for validity during a kind of failure transfer |
Citations (5)
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| WO1992012482A1 (en) * | 1991-01-04 | 1992-07-23 | Array Technology Corporation | Fluid transfer device and method of use |
| US5548711A (en) * | 1993-08-26 | 1996-08-20 | Emc Corporation | Method and apparatus for fault tolerant fast writes through buffer dumping |
| CN101354633A (en) * | 2008-08-22 | 2009-01-28 | 杭州华三通信技术有限公司 | Method for improving writing efficiency of virtual storage system and virtual storage system thereof |
| CN101493795A (en) * | 2008-01-24 | 2009-07-29 | 杭州华三通信技术有限公司 | Storage system, storage controller, and cache implementing method in the storage system |
| CN103092786A (en) * | 2013-02-25 | 2013-05-08 | 浪潮(北京)电子信息产业有限公司 | Double-control double-active storage control system and method |
-
2015
- 2015-08-31 CN CN201510548650.4A patent/CN105205017A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992012482A1 (en) * | 1991-01-04 | 1992-07-23 | Array Technology Corporation | Fluid transfer device and method of use |
| US5548711A (en) * | 1993-08-26 | 1996-08-20 | Emc Corporation | Method and apparatus for fault tolerant fast writes through buffer dumping |
| CN101493795A (en) * | 2008-01-24 | 2009-07-29 | 杭州华三通信技术有限公司 | Storage system, storage controller, and cache implementing method in the storage system |
| CN101354633A (en) * | 2008-08-22 | 2009-01-28 | 杭州华三通信技术有限公司 | Method for improving writing efficiency of virtual storage system and virtual storage system thereof |
| CN103092786A (en) * | 2013-02-25 | 2013-05-08 | 浪潮(北京)电子信息产业有限公司 | Double-control double-active storage control system and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107301021A (en) * | 2017-06-22 | 2017-10-27 | 郑州云海信息技术有限公司 | It is a kind of that the method and apparatus accelerated to LUN are cached using SSD |
| CN107977280A (en) * | 2017-12-08 | 2018-05-01 | 郑州云海信息技术有限公司 | Verify that ssd cache accelerate the method for validity during a kind of failure transfer |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
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| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151230 |