CN105190531A - Memory power savings in idle display case - Google Patents
Memory power savings in idle display case Download PDFInfo
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- CN105190531A CN105190531A CN201480025931.5A CN201480025931A CN105190531A CN 105190531 A CN105190531 A CN 105190531A CN 201480025931 A CN201480025931 A CN 201480025931A CN 105190531 A CN105190531 A CN 105190531A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3218—Monitoring of peripheral devices of display devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/455—Image or video data
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/121—Frame memory handling using a cache memory
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Human Computer Interaction (AREA)
- Multimedia (AREA)
- Computing Systems (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Controls And Circuits For Display Device (AREA)
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Abstract
In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
Description
Technical field
The present invention relates to the field of digital systems comprising integrated circuit, display device and high-speed cache.
Background technology
Various types of digital display circuit generally includes or is connected to the display carrying out mutual user with equipment.Display can be incorporated in equipment.The example of the display be incorporated to comprises the touch-screen in various smart phone, panel computer or other personal digital assistants.In conjunction with another example of display be the notebook computer with screen in upper cover.Display also can be connected to equipment via cable.The example of the display connected comprises various desk-top computer and the workstation of the stand alone display on the desk that has and be positioned at before user.Some desk-top computers also have be incorporated to display (various such as, purchased from AppleInc.
computing machine).Display provides user can check to carry out mutual visualization interface with system and the application program that performs in system.In some cases (such as, touch-screen), display is also for user is provided for the interface being input to system.Also can comprise other user input devices (such as, keyboard, mouse or other sensing equipments etc.).
In many cases, the image shown within a period of time is static substantially.Such as, if user's reading electronic book just over the display, then display can show the page of text statically until user runs through this page.When film suspension, change may not be there is in image in the time that time-out works.When user browses webpage, user also may attract by content, and image may be static.When existing hardly in the still image be shown or when there is not change completely, all may causing waste for the memory bandwidth consumed at each refresh cycle acquisition image of screen in bandwidth and in power consumption.
Summary of the invention
In one embodiment, a kind of system comprises the Memory Controller with memory cache and the display controller being configured to control display.This system can be configured to detect that shown image is essentially static, and can be configured such that display controller request source frame buffered data distributes in memory cache.To the electric power of external memory interface be consumed in by carrying out high-speed cache to frame buffered data (or frame buffered data at least partially) and save in memory cache.In certain embodiments, the power management configuration that this system also can change in memory cache is closed to prevent memory cache or reduces its effective dimensions during free screen situation, makes frame buffered data to keep high-speed cache.At the time durations of shown image dynamic change, frame buffered data can not be cached in memory cache and power management configuration can allow memory cache closedown/size to reduce.
Accompanying drawing explanation
Carry out brief description to accompanying drawing now, illustrating below is described with reference to the accompanying drawings.
Fig. 1 is the block diagram of an embodiment of the system comprising SOC (system on a chip) (SOC), storer, imageing sensor and display device.
Fig. 2 is the process flow diagram of the operation that the embodiment of system under Dynamic Announce state is shown.
Fig. 3 is the process flow diagram of the operation that the embodiment of system under free time display state is shown.
Fig. 4 is the block diagram of the various software modules that can perform in of a system embodiment.
Fig. 5 is for illustrating the process flow diagram of the operation of an embodiment of the driver of PMGR shown in Fig. 4.
Fig. 6 is the diagram of the embodiment that CPU filtrator is shown.
Fig. 7 is the process flow diagram of the operation of the embodiment that CPU filtrator is shown.
Fig. 8 is the process flow diagram of the operation of an embodiment of the PMGR driver illustrated in response to CPU filtrator.
Fig. 9 is the block diagram of an embodiment of computing machine accessible storage medium.
Figure 10 is for comprising the block diagram of another embodiment of the system of the SOC shown in Fig. 1.
Although the present invention is subject to the impact of various modification and alternative form, shows its specific embodiment in accompanying drawing by way of example and will describe in detail herein.But, be to be understood that, to its accompanying drawing and to describe in detail and the present invention is limited to particular forms disclosed by not intended to be, and antithesis, its object is to cover all modifications form, equivalents and the alternative form in the spirit and scope of the invention that drop on and limited by claims.The object of title used herein only for organizing, and be not intended to the scope for limiting instructions.As in whole patented claim use, with the meaning allowed (that is, meaning that there is possibility) instead of compulsory meaning (that is, mean must) use " can " word.Similarly, word " comprises " (" include ", " including " and " includes ") refers to and includes but not limited to.
Various unit, circuit or miscellaneous part can be described to, and " being configured to " performs one or more task.In this type of context, " being configured to " is to generally meaning that " having " performs the wide in range statement of the structure of this or the multi-task " circuit " during operation.Therefore, though unit/circuit/component can be configured to unit/circuit/component is current be not energized time also perform described task.In general, the circuit forming the structure corresponding with " being configured to " can comprise hardware circuit and/or store the storer that can perform the programmed instruction realizing this operation.Storer can comprise volatile memory such as static RAM or dynamic RAM and/or nonvolatile memory such as optical storage or disk storage device, flash memories, programmable read only memory etc.Similarly, in order to the convenience in describing, various unit/circuit/component can be described as performing one or more task.This type of description should be construed as comprising phrase and " be configured to ".Unit/circuit/component that statement is configured to perform one or more task is intended to not quote the explanation of 35U.S.C. § the 112, six section to this unit/circuit/component clearly.
This instructions comprises quoting " embodiment " (" oneembodiment " and " anembodiment ").Occur that phrase " embodiment " (" oneembodiment " and " anembodiment ") not necessarily refers to identical embodiment, but imagination comprises the embodiment of the combination of any feature usually, unless clearly denied herein.Special characteristic, structure or characteristic can meet any suitable mode of the present disclosure and combine.
Embodiment
Now turn to Fig. 1, it illustrates the block diagram that SOC10 is coupled to an embodiment of storer 12, one or more imageing sensor 26 and one or more display 20.As by title inferred, the parts of SOC10 can be used as integrated circuit " chip " and are integrated in single Semiconductor substrate.In certain embodiments, parts can two or more individual chips in systems in which realize.But SOC10 will use in this article as an example.In the illustrated embodiment, the parts of SOC10 comprise CPU (central processing unit) (CPU) complex 14, display tube 16, peripheral components 18A-18B (more simply, " peripherals "), Memory Controller 22, image-signal processor (ISP) 24, Graphics Processing Unit (GPU) 34, power supervisor (PMGR) 32 and communication structure 27.Parts 14,16,18A-18B, 22,24,32 and 34 all can be coupled to communication structure 27.Memory Controller 22 can be coupled to storer 12 during use.Similarly, ISP24 can be coupled to imageing sensor 26 during use, and display tube 16 can be coupled to display 20 during use.In the illustrated embodiment, CPU complex 14 comprises one or more processor 28 and secondary (L2) high-speed cache 30.In the illustrated embodiment, Memory Controller comprises memory cache 36.Memory Controller 22 and display tube 16 all can comprise configuration register 38A-38B respectively.Miscellaneous part also can comprise configuration register, and it is not shown in FIG.Storer 12 can store one or more frame buffer during use, and this one or more frame buffer comprises frame buffer 40A and comprises frame buffer 40B alternatively.
Display tube 16 can comprise for the treatment of one or more frozen frozen mass and/or one or more video sequence hardware for display on the display 20.In general, for each source frozen frozen mass or source video sequence frame, display tube 16 can be configured to generate and read storage operation to be read the data representing frame from storer 12 by Memory Controller 22.Each frame can be stored in the frame buffer 40A-40B in such as storer 12, and display tube 16 can utilize the pointer of the frame buffer 40A-40B pointed in storer 12 to programme to read frame from frame buffer.Each frame can comprise the view data describing image to be shown, such as pixel, color component, α mixed number etc.
Display tube 16 can be configured to process view data being performed to any type.In one embodiment, display tube 16 can be configured to convergent-divergent frozen frozen mass and the frame of video sequence is shaken, convergent-divergent and/or perform color space conversion.Display tube 16 can be configured to mix frozen frozen mass and video sequence frame to produce the output frame for display.Display tube 16 also can be called as indicative control unit more at large.Indicative control unit (or display controller) usually can be and is configured to prepare any hardware for the frame (from one or more source, such as frozen frozen mass and/or video sequence frame) of display.The various process performed by display tube 16 can be called as synthesis usually.Synthesis can comprise by its by from various image view data combine with any process producing output image.
Memory Controller 22 can comprise circuit usually, and this circuit is for receiving storage operation from the miscellaneous part of SOC10 and for accessing storer 12 to complete storage operation.Memory Controller 22 can be configured to the storer 12 of accessing any type.Such as, storer 12 can be the such as synchronous DRAM (SDRAM) of static RAM (SRAM), dynamic ram (DRAM), comprises double data rate (DDR, DDR2, DDR3 etc.) DRAM.The DDRDRAM (such as, LPDDR, mDDR etc.) of low-power/mobile model can be supported.
In the illustrated embodiment, Memory Controller 22 can comprise memory cache 36 to store the memory data of access recently.In SOC specifically implements, such as memory cache 36 is by avoiding again accessing to it power consumption reduced in SOC to when again accessing from the data in storer 12 soon in expection.Therefore, memory cache 36 can visit before access storer 12, detect the hit of storage operation/miss by Memory Controller 22.If storage operation is the hit in memory cache 36, then can not access storer 12.Interconnection structure 27 can utilize storage operation to support that transmitting high speed buffer memory points out to identify for being stored in the candidate in memory cache 36.Therefore, memory cache 36 can store the data corresponding with any parts of the access storer in SOC10.In some cases, memory cache also can be described as system cache, and it is contrary with the high-speed cache in private high-speed cache such as the L2 high-speed cache 30 or processor 28 of only serving some parts.In addition, in certain embodiments, system cache is without the need to being positioned at Memory Controller 22.
With regard to the data in frame data such as frame buffer 40A-40B, consumer is display tube 16.Usually, can be read once by display tube 16 to frame buffer, because before display tube 16 initiates new frame, frame is usually variable more for carrying out the next image shown.Such as, the frame rate of 30 frames per second or 60 frames is often used.Therefore, reading frame per second 30 times or 60 times.Therebetween, the source (such as, Video Decoder, GPU34 etc.) of frame data just can generate new frame to be shown and just can write frame data in different memory position.When next frame reads beginning, frame can be read from different memory location.Therefore, when shown image carries out interframe change, the high-speed cache of frame data can be forbidden in memory cache 36.The usual time dependent situation of frame data can be described as Dynamic Announce or Dynamic Announce state.The image shown by display can be described as dynamically.
On the other hand, the situation that multiple successive frame has static content can be there is.In general, static content can refer to the unconverted content of interframe (such as, each pixel is identical between different frame) or refer to be less than the content of threshold quantity change, makes former frame closely present frame.Detect the idle display states of multiple successive frame identifiable design with static content or idle display situation (or free screen in this case, because display screen is still opened and just shown still image).Idle display situation can be that shown vision content does not change or there is the situation of very little change and display unlatching within a period of time.User may check shown data, such as e-book, webpage or Email.Or user may paused video.Frame data are generally static situation and can be described as idle display or idle display state, and the image just shown by display can be described as free time or static state.
In free time display situation, what display tube 16 still can be frame data only has consumer.But identical frame data can repeatedly be read.Therefore, high-speed cache is allowed to can be desirable for free time display situation.More specifically, display tube 16 can be that programmable (such as, in configuration register 38B) is to allow or to forbid carrying out high-speed cache in memory cache 36.When enabling high-speed cache, display tube 16 can be configured to transmission memory read operation and indicate the caching hint of the data should distributed in memory cache 36 to read frame buffer 40A-40B to utilize.In certain embodiments, if synthesize to produce output frame to more than one frame, then can carry out high-speed cache (by comprising cache assignment prompting) to the frame comprising most of frame data and high-speed cache can not carried out to other frames.In other embodiments, multiple frame can to fit in memory cache 36 and can carry out high-speed cache to multiple frame.In other embodiments, only a part for frame can to fit in memory cache 36 and display tube 16 can be configured to provide cache assignment to point out to a part for frame.On the other hand, when disabling cache, display tube 16 can provide instruction not have the caching hint of high-speed cache.As mentioned above, in Dynamic Announce situation, high-speed cache can be disabled.In one embodiment, idle display situation also can comprise other memory access parts closedown determining to have benefited from the high-speed cache in memory cache 36.Such as, processor 28, GPU34, ISP24 and other media devices may have benefited from high-speed cache.The miscellaneous part may not having benefited from high-speed cache without the need to closing, such as, for interface such as I
2the various interface controllers of C (built-in integrated circuit), universal asychronous receiver transmitter (UART), system packet interface (SPI) etc.Therefore, idle display situation can comprise the subset of at least parts of the display image using the memory cache 36 of closing, display tube 16/ display 20 of unlatching and static state.
In certain embodiments, memory cache 36 can support various power management features.By carrying out programming to control power management features to configuration register 38A.Can in response to detecting that the change showing state from Dynamic Announce state to the free time is to revise power management features.Such as, even if display tube 16 repeatedly can read frame data under free screen state, reading also can be spaced apart by many clock period under the frequency of memory cache 36.In addition, as mentioned above, many miscellaneous parts of SOC10 can be idle under free time display state.Such as, because the content that be not performed generates, therefore other audio/video devices such as GPU34, ISP24, video encoder/decoder etc. can be idle.Therefore, system can show for Memory Controller 22/ memory cache 36 relative free, and this may make electric power management mechanism activate.This mechanism can comprise such as by making a part of power-off of high-speed cache reduce the effective dimensions of high-speed cache, make the power remove etc. of high-speed cache.During free time display state, Memory Controller 22 can be programmed to forbid these electric power management mechanisms and make memory cache 36 keep energising and life size, thus storage frame data.During Dynamic Announce state, Memory Controller 22 can be programmed to enable electric power management mechanism.
In one embodiment, as mentioned above, the software performed by processor 28 can detect idle display state and Dynamic Announce state, and can programme to configuration register 38A-38B.Software can comprise the power supervisor driver (PMGR driver) corresponding with PMGR32, the display driver corresponding with display tube 16 and the Memory Controller driver corresponding with Memory Controller 22/ memory cache 36.The more details of an embodiment are discussed hereinafter further in detail.Software can store and obtain for by processor 28 and perform in memory 12, and also in cacheable high-speed cache in L2 high-speed cache 30 and/or processor 28.Software also can store in nonvolatile memory in systems in which, such as flash memories, solid magnetic disc memory storage, disk or optical disk storage apparatus etc.
Display 20 can be the visual display device of any kind.Display can comprise such as the display of the touch-screen pattern of mobile device such as smart phone, panel computer etc.Various display 20 can comprise LCDs (LCD), light emitting diode (LED), plasma, cathode-ray tube (CRT) (CRT) etc.In display accessible site to the system comprising SOC10 (such as, smart phone or panel computer) and/or can be individual packages equipment such as computer monitor, televisor or other equipment.
ISP24 can be configured to receive the vision sensor data from imageing sensor 26, and can be configured to process data to produce the picture frame that may be suitable for showing on the display 20.Imageing sensor 26 can comprise camera (such as, charge-coupled image sensor (CCD), complementary metal oxide semiconductor (CMOS) (CMOS) sensor).
GPU24 can comprise one or more GPU processor, and can comprise for the local cache of GPU and/or carry out mutual interface circuit (such as, to the interface of communication structure 27) with the miscellaneous part of SOC10.In general, GPU processor can be make object be converted into the operation of frame and the processor optimized to perform in graphics pipeline.Such as, operation can comprise conversion and illumination, triangle split, rasterisation, painted, veining etc.
CPU complex 14 can comprise one or more CPU processors 28 of the CPU as SOC10.The CPU of system comprises one or more processors of the main control software of executive system such as operating system.In general, the miscellaneous part of the software controllable system performed by CPU is during use to realize the desired function of system.The software performed by processor 28 can comprise to be mentioned and above at hereafter various in greater detail driver.Processor 28 also can perform other softwares such as application program.Application program can provide user function, and the responsible operating system for controlling compared with low category devices.Therefore, processor 28 also can be described as application processor.CPU complex 14 also can comprise the interface (such as, to the interface of communication structure 27) of other hardware such as L2 high-speed cache 30 and/or miscellaneous part to system.
Peripherals 18A-18B can be any one group of additional firmware function be included in SOC10.Such as, peripherals 18A-18B can comprise video peripheral such as video encoder/decoder, scaler, spinner, mixer etc.Peripherals can comprise audio peripheral device such as microphone, loudspeaker, interface, audio process, digital signal processor, mixer etc. to microphone and loudspeaker.Peripherals can comprise for SOC10 outside (such as, peripherals 18B) the interface controller of various interfaces, comprise interface such as USB (universal serial bus) (USB), comprise peripheral parts interconnected (PCI), serial port and the parallel port etc. of universal serial bus (PCIExpress) (PCIe).Peripherals can comprise networking peripherals such as MAC controller (MAC).Any one group of hardware can be comprised.
Communication structure 27 can be for carrying out any communication interconnect of communicating and agreement between the parts of SOC10.Communication structure 27 can be based on bus, comprises shared bus configuration, gauche comformer and has the classification bus of bridge.Communication structure 27 also can be based on packet, and can be stagewise, staggered form, point-to-point or other cross tie parts with bridge.
PMGR32 can be configured to powering on of the miscellaneous part of control SOC10 and power-off.That is, PMGR32 can make miscellaneous part power on and power-off.PMGR32 can under software directly controls (such as, software can directly the powering on and/or power-off of requesting component) and/or can be configured to monitoring SOC10 and determine when to make all parts power on or power-off.PMGR32 also can be configured to the converting member between different electrical power state (such as, voltage/frequency combination).PMGR32 can be further configured to the various voltage values from the parts external power source controller request SOC10.
Should be noted, the quantity of the parts of SOC10 (and the parts shown in Fig. 1, the quantity of the subassembly in such as CPU complex 14) can be different according to different embodiment.Can exist than the more or less each parts/subassembly shown in Fig. 1.
Now turn to Fig. 2, it illustrates process flow diagram, and this process flow diagram illustrates the operation of the embodiment of the system shown in Fig. 1 under Dynamic Announce state, and this operation is for detecting idle display situation and being transformed into idle display state.Other operations occurred under Dynamic Announce state are not illustrated.Although illustrate frame for the ease of understanding with certain order, other order can be used.In one embodiment, the operation of Fig. 2 can realize in software, and therefore software can be included in the instruction realizing the operation shown in Fig. 2 when being performed.Other embodiments can realize the feature shown in Fig. 2 in the combination of hardware and/or hardware and software.
In Dynamic Announce state, system can monitor to detect idle display situation.Idle display detects by various mode: by analyzing the successive frame of change, by pointing out that same number of frames impact damper is for successive frame etc.In addition, in certain embodiments, the state such as miscellaneous part such as CPU complex 14, GPU34, ISP24 and/or peripherals 18A-18B can become the factor idle display situation whether being detected.If idle display situation (decision box 50, "Yes" branch) detected, then system can programme to ask the cache assignment (frame 52) for frame buffer reading to display tube configuration register 38B.In another way, frame data can be allowed to carry out high-speed cache.In one embodiment, the storage operation transmitted by communication structure 27 can comprise caching hint, and display tube can use caching hint to indicate whether to enable high-speed cache to cache assignment.System also can be programmed to Memory Controller configuration register 38A the power management revised memory cache 36 and be controlled (frame 54).Particularly, can forbid making high-speed cache 36 power-off (guaranteeing that memory cache 36 keeps " waking up " during free time display state).High-speed cache automatic adjust size feature (it is by making the part power-off of high-speed cache for reducing the effective dimensions of high-speed cache 36) also can be disabled to guarantee that high-speed cache 36 still remains on full-size in free time display situation.System can be converted to idle display state (frame 56).
Fig. 3 is for illustrating the process flow diagram of the operation of the embodiment of the system shown in Fig. 1 under free time display state, and this operation is for detecting Dynamic Announce situation and being transformed into Dynamic Announce state.Although illustrate frame for the ease of understanding with certain order, other order can be used.Under free time display state, other operations contingent are not illustrated.In one embodiment, the operation of Fig. 3 can realize in software, and therefore software can be included in the instruction realizing the operation shown in Fig. 3 when being performed.Other embodiments can realize the feature shown in Fig. 3 in the combination of hardware and/or hardware and software.
Under free time display state, system can monitor to detect Dynamic Announce situation.Idle display detects by various mode: by analyzing the successive frame of change, by pointing out for the change etc. in the frame buffer of successive frame.In addition, in certain embodiments, the state of miscellaneous part such as CPU complex 14, GPU34, ISP24 and/or peripherals 18A-18B etc. can become factor Dynamic Announce situation whether being detected.If Dynamic Announce situation (decision box 60, "Yes" branch) detected, then system can programme not ask the cache assignment (frame 62) for frame buffer reading to display tube configuration register 38B.In one embodiment, instruction is supported without the caching hint of high-speed cache, and the frame buffered data that can be used under Dynamic Announce state reads.In another way, can the high-speed cache of disable frame data.System also can be programmed to Memory Controller configuration register 38A the power management revised memory cache 36 and be controlled (frame 64).Particularly, can allow to make high-speed cache 36 power-off (high-speed cache sleep) and high-speed cache automatic adjust size feature (it is by making the power remove of the part of high-speed cache for reducing the effective dimensions of high-speed cache 36) can be allowed to allow the power-off when cache availability is low.System can be converted to Dynamic Announce state (frame 66).
Fig. 4 illustrates the block diagram of the various software modules of an embodiment that can participate in idle display/Dynamic Announce state and determine and manage.Shown embodiment comprises display driver 70, GPU driver 72, ISP driver 74, other media drives 76, other peripheral equipment drivers 78, CPU filtrator 80, PMGR driver 82 and Memory Controller driver 84.PMGR driver 82 can comprise frame buffer open/close state 86, display open/close state 87 and other open/close states 88.Some communication between driver is also show in Fig. 4.In general, the driver shown in Fig. 4 can store in memory 12 during use and can perform on processor 28 during use.Driver also can be stored in the non-volatile memory medium of system and (such as, be coupled to flash memories or other nonvolatile memories of SOC10).
PMGR driver 82 can be responsible for the power supply status of all parts of monitoring SOC10, and can receive from the energising of respective drivers and power down request to make parts power on and power-off.PMGR driver 82 can carry out mutual to make parts power on and power-off with PMGR32, and it is called energising and power cut-off incident.That is, power-on event can be the event making the power supply of the parts of power remove energising (powering on also referred to as making the parts of power-off).Power cut-off incident can be the event of the power remove (the parts power-off also referred to as making to power on) of the parts that power supply is energized.PMGR32 can comprise for the local power supply switch in control SOC10 with parts are powered on and power-off circuit and for asking various voltage levvl to be supplied to the circuit of SOC10 based on power supply input.In certain embodiments, PMGR32 also can be configured to based on hardware monitoring, parts be powered on and power-off automatically.
Therefore, as shown in Figure 4, when there is pending GPU work, GPU driver 72 can ask GPU34 is powered on.GPU driver 72 various can present activity by operating system and/or the application call performed on processor 28 to perform.Similarly, complete unsolved work as GPU34 and do not have in current time other work pending, then GPU driver 72 can ask to make GPU34 power-off.
Similarly, if operating system/application program needs to catch some vision sensor data and ISP24 power remove, then operating system/application program can call ISP driver 74 with make ISP24 be energized and ISP driver 74 can from PMGR driver 82 ask energising.When no longer there is view data to be captured, ISP driver 74 can ask to make ISP24 power-off.Other media drives 76 and other peripheral equipment drivers 78 can transmit power on/off request to PMGR driver 82 similarly.When display is closed or stop using, display driver 70 can ask to make display tube power on/off (the display ON/OFF request in Fig. 4).
PMGR driver 82 can programme to make asked parts power on/off to PMGR32 and can in response to various power on/off request to record the power on/off state of the corresponding component under open/close state 88.Display open/close state 87 can upgrade for the display ON/OFF request from display driver 70.In certain embodiments, at least relative to determine free time/Dynamic Announce situation, the counting of the parts interested that PMGR driver 82 can only be held open.When counting reaches 0, affect free time/all parts that Dynamic Announce state is determined can be closed.The quantity of this base part that non-zero count instruction is opened.
In the illustrated embodiment, frame buffer is also virtualized as parts, and is recorded as On/Off 86 times at open/close state.PMGR driver 82 can be configured to the open/close state recording frame buffer according to the FB ON/OFF request transmitted by display driver 70, and this request can generate based on the detection of display driver 70 pairs of static frames (the N number of static frames 71 in Fig. 4).In this embodiment, display driver 70 can be responsible for monitoring static frames, and can indicate N number of continuous static frame when detected, wherein N be greater than 1 integer.In certain embodiments, N can be programmable parameter.In response to N number of static frames being detected, display driver 70 can ask to make frame buffer power-off (the FB ON/OFF request in Fig. 4).If detect and be less than N number of static frames (comprising zero static frames), then display driver 70 can ask frame buffer is energized.Based on the open/close state of the miscellaneous part in the request of frame buffer ON/OFF and SOC10, PMGR driver 82 can detect free time/Dynamic Announce state.Based on detected free time/Dynamic Announce state, PMGR driver 82 can enable/and the high-speed cache of disable frame buffered data (is sent to display driver 70, this display driver can be programmed to display tube 16) and high-speed cache power management control (be connected to Memory Controller driver 84, it can be programmed to Memory Controller 22/ memory cache 36) can be revised.
More specifically, whether some parts can be idle relevant to display.Such as, if GPU34 energising, then it can present the new frame for showing.If ISP24 is energized, then can catch the view data that may show very soon.Also can exist may to free time/relevant other media component of Dynamic Announce state or peripheral units.In addition, CPU complex 14 state may to free time/Dynamic Announce state is relevant.As detailed below, can filter the state of CPU.Can determine free time/Dynamic Announce state process in consider any subset of SOC parts.In addition, as previously mentioned, some parts can have benefited from using memory cache 36, and if this base part being in idle display state may do not detected, then frame buffered data declines the data brought from miscellaneous part.
Display driver 70 can detect N number of static frames in every way.Such as, display tube 16 can comprise hardware supported to detect static frames (such as, relatively can calculate the cyclic redundancy check (CRC) (CRC) that frame carries out, or can relatively calculate the CRC that configuration information carries out).And for example, frame buffer position can be programmed in display tube 16 by display driver 70, and can detect one or more same number of frames impact damper for N number of successive frame.
CPU filtrator 80 can monitor sleep and the wake events (power-off and power-on event) of processor 28, and can filter may with free time/Dynamic Announce situation some ON/OFF event incoherent.Such as, processor 28 can be waken up to process various system management events (such as, device interrupt, periodical operation system code perform to guarantee that system is normally run and arranges the thread etc. for performing possibly).These events can be (that is, may follow idle event closely after wake events, this idle event makes processor get back to sleep state) of short-term.CPU filtrator 80 can perform to monitor cpu activity time and cpu idle time based on wake events and idle event.The time being less than threshold quantity can by filtering.CPU filtrator 80 can to PMGR driver 82 provide corresponding activity/free time instruction with determine processor 28 whether for free time/Dynamic Announce detects and is regarded as being energized.In one embodiment, movable/idle instruction can be the probability being in active state and idle condition.
Fig. 5 be illustrate PMGR driver 82 for free time/process flow diagram of operation of an embodiment that detects of Dynamic Announce.Although illustrate frame for the ease of understanding with certain order, other order can be used.In one embodiment, the operation of Fig. 5 can realize in software, and therefore software can be included in the instruction realizing the operation shown in Fig. 5 when being performed.Other embodiments can realize the feature shown in Fig. 5 in the combination of hardware and/or hardware and software.
If PMGR driver 82 has received the energising request (decision box 90 of output from driver, "Yes" branch), display opens (display open/close state 87 is opened) (decision box 92, "Yes" branch), and affect free time/one or more other resources that Dynamic Announce state is determined open (decision boxs 94, "Yes" branch), then PMGR driver 82 can show state from the free time and becomes Dynamic Announce state, thus can in display tube 16 disabling cache (by display driver 70 transmit instruction--frame 96), and allow high-speed cache sleep/adjust size (by Memory Controller driver 84 transmission instruction--frame 98) automatically.As mentioned above, in certain embodiments, can follow the tracks of the quantity of miscellaneous part of opening, thus by determining that whether this quantity be zero to realize decision box 94.Therefore, decision box 90 "Yes" branch, decision box 92 "Yes" branch and decision box 94 "Yes" branch can together with as detect Dynamic Announce situation (decision box 60 in Fig. 3, "Yes" branch) embodiment.PMGR driver 82 also can complete the unlatching process (frame 100) of asked parts.Complete open process can comprise such as programme to make parts to be energized to PMGR32 and open/close state 88 times be " unlatchings " and/or increase by state recording for free time/quantity of turned parts determined of Dynamic Announce state.Monitor the subset of parts to determine free time/Dynamic Announce situation embodiment in, decision box 90 parts that only antithetical phrase is concentrated can consider energising request.If PMGR driver 82 has received the energising request (decision box 90 of output from driver, "Yes" branch) and arbitrary display is current does not all open (decision box 92, "No" branch) or affect free time/other resources of determining of Dynamic Announce state at least one resource open (decision box 94, "No" branch), then PMGR driver 82 can complete the unlatching process of asked parts, and without the need to free time/Dynamic Announce detects relevant any additional work (frame 100).
If PMGR driver 82 receives the power down request (decision box 102, "Yes" branch) of output from driver, then display is current is in Dynamic Announce state.PMGR driver 82 can be determined that display is current and whether open (decision box 106, "Yes" branch), and if be, then can determine that the needs of SOC10 are closed and whether close (decision box 104) with the miscellaneous part being transformed into idle display state.Determine that miscellaneous part is closed such as by checking that open/close state 88 or the number count by inspection turned parts realize.If (decision box 104, "Yes" branch), then PMGR driver 82 can become idle display state from Dynamic Announce state and can enable high-speed cache (by transmitting instruction to display driver 70--frame 110) display tube 16, and forbids carrying out high-speed cache (by transmitting instruction to Memory Controller driver 84--frame 112) to the adjust size of sleep/automatically.Therefore, decision box 102-is branch, decision box 104-to be branch with decision box 106-be branch can together with as the embodiment detecting idle display and determine (such as, the decision box 50 in Fig. 2, "Yes" branch).PMGR driver 82 also can complete the closing process (frame 114) of asked parts.Closing process can comprise such as programme to make parts to be energized to PMGR32 and open/close state 88 times state become close and/or reduction be used for free time/quantity of turned parts determined of Dynamic Announce state.If PMGR driver 82 has received the power down request (decision box 102 of output from driver, "Yes" branch) and arbitrary miscellaneous part that need be transformed into idle display state do not close or detect and be less than N number of static frames (decision box 104 and 106 is respectively "No" branch), then PMGR driver 82 can complete the closing process of asked parts, and without the need to any additional work (frame 114).Finally, if the request received is energising request for the parts that need change display state or power down request (decision box 90 and 102, "No" branch), then PMGR driver 82 can complete the process (frame 116) of request, and this request can comprise energising request for the parts without the need to determining display state or power down request.
As previously mentioned, CPU filtrator 80 can be used for determining whether processor 28 need be determined for display state and be regarded as opening or closing.The block diagram of an embodiment of model of Fig. 6 for showing CPU filtrator 80 and using.In this embodiment, processor 28 is in the probability of activity or free time is distribute based on the preceding activity/free time of processor 28.The horizontal axis of cpu idle time in the figure of Fig. 6 illustrates, and cpu activity time vertical axis in the graphic illustrates.Transient activity/free time is classified as " blind area " 120.Blind area 120 can be defined as being less than the activity time of first threshold and being less than the free time of Second Threshold, and it is respectively as shown in the dotted line 122 and 124 in Fig. 6.In various embodiments, first threshold and Second Threshold can be identical or different time quantum.In various embodiments, first threshold and Second Threshold can be programmable parameter or preset parameter.In blind area 120, CPU is in movable probability of state (P
a) and CPU be in idle probability of state (P
i) be all assigned to zero.
Be greater than first threshold and the cpu activity time being up to first upper limit (dotted line 126) can be in movable probability of state (P by the CPU be mapped to linearly between 0 and 1
a).The cpu activity time being greater than first upper limit is assigned with probability 1.Similarly, the cpu idle time between Second Threshold and second upper limit (dotted line 128) can be in idle probability of state (P by the CPU be mapped to linearly between 0 and 1
i).The cpu idle time being greater than second upper limit is assigned with probability 1.First upper limit and second upper limit can be identical value or different value, and can be fixing or programmable.Other embodiments can otherwise or use other functions that activity/free time is mapped to probability.
As above distributed probability is instant probability (P
a, P
i).These probability can generate when the idle event of each CPU and CPU wake events.In certain embodiments, probability with historical record carry out filtering (such as, as shown in the formula of figure in following Fig. 6, its as by the probability filtered recently caught).Therefore, filtered movable probability F can be generated
awith filtered idle probability F
i.Filtered probability can be provided to PMGR driver 82 to show detection to determine CPU open/close state for dynamically/free time.Filtration coefficient α and β can be programmable parameter, and can select by rule of thumb based on the order of accuarcy of the actual open/close state of filtered probabilistic forecasting processor 28.
Fig. 7 is the process flow diagram of the operation of the embodiment showing CPU filtrator 80.Although illustrate frame for the ease of understanding with certain order, other order can be used.In one embodiment, the operation of Fig. 7 can realize in software, and therefore software can be included in the instruction realizing the operation shown in Fig. 7 when being performed.Other embodiments can realize the feature shown in Fig. 7 in the combination of hardware and/or hardware and software.
CPU wave filter 80 can be configured to perform when entering and leave idle condition.Idle condition can be the state that processor 28 does not actively perform work.Idle condition can comprise processor 28 and keep power supply but the sleep state not performing instruction, and the off-position of processor 28 power-off.Therefore, CPU filtrator 80 only performs filtrator 80 without the need to making processor 28 periodically wake up.And contrary, filtrator 80 at processor 28 owing to performing when other reasons wakes up.
CPU filtrator 80 can calculate nearest free time/activity time (frame 130).Such as, computation-free time when can be performed during CPU filtrator 80 leaves from CPU idle condition.Can during entering CPU idle condition the computational activity time.Activity/free time can calculate according to the special timer that freely operates, and CPU filtrator 80 can be removed this special timer that freely operates after each computational activity/free time.In various embodiments, the timer that freely operates can increase progressively based on the clock used by PMGR32 in processor clock or SOC10.In another embodiment, the timer (such as, time-based register) used on SOC10 for various uses can be used.In this type of embodiment, CPU filtrator 80 can read timer and calculates the difference between value that the currency that reads from timer and CPU filtrator 80 previously read from timer.
Based on latest activities time and free time, CPU filtrator 80 can calculate instant probability (P
a, P
i) (frame 132).CPU filtrator 80 can calculate filtered probability (F for current time based on instant probability and previous filtered probability
a, F
i) (frame 134).Filtered probability can be transferred to PMGR driver 82 to calculate CPU open/close state (frame 136) by CPU filtrator 80.Alternatively, CPU filtrator 80 can calculate CPU open/close state according to filtered probability and CPU open/close state can be transferred to PMGR driver 82.
Next turn to Fig. 8, it illustrates PMGR driver 82 in response to the filtered probability from CPU filtrator 80 to determine the process flow diagram of the operation of an embodiment of CPU open/close state.As mentioned above, in other embodiments, the operation of Fig. 8 can realize in CPU filtrator 80.Although illustrate frame for the ease of understanding with certain order, other order can be used.In one embodiment, the operation of Fig. 8 can realize in software, and therefore software can be included in the instruction realizing the operation shown in Fig. 8 when being performed.Other embodiments can realize the feature shown in Fig. 8 in the combination of hardware and/or hardware and software.
If be in the filtered probability (F of Idle state
i) be greater than the filtered probability (F being in Mobile Forms
a) (decision box 138, "Yes" branch), then PMGR driver 82 can determine that CPU closes (frame 140).If because current idle/activity time is in blind area 120, instant probability (P
a, P
i) being zero (decision box 142, "Yes" branch), then PMGR driver 82 can keep the CPU open/close state (frame 144) previously determined.That is, if the CPU open/close state determined recently is for closing, then CPU open/close state keeps closing.Similarly, if the CPU open/close state determined recently is for opening, then CPU open/close state is held open.Finally, if the filtered probability (Fi) being in Idle state is not more than the filtered probability (Fa) and instant probability (Pi that are in Mobile Forms, Pa) zero (decision box 138 and 142 is not, "No" branch), then PMGR driver 82 can determine that CPU open/close state is for opening (frame 146).
Fig. 9 is the block diagram of an embodiment of computing machine accessible storage medium 200.In general, computing machine accessible storage medium can comprise computing machine during use can by any storage medium of computer access to provide instruction and/or data to computing machine.Such as, computing machine accessible storage medium can comprise storage medium such as magnetic or optical medium, such as, and disk (fixing or detachable), tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW or blue light.Storage medium also can comprise volatibility or nonvolatile memory medium, such as RAM (such as, synchronous dynamic ram (SDRAM), RambusDRAM (RDRAM), static RAM (SRAM) (SRAM) etc.), ROM or flash memories.Storage medium can be physically included in computing machine, and instruction/data is provided to this computing machine by storage medium.Alternatively, storage medium can be connected with computing machine.Such as, storage medium is connected with computing machine by network or wireless link such as network additive storage device.Storage medium connects by perimeter interface such as USB (universal serial bus) (USB).In general, computing machine accessible storage medium 200 non-transient state mode can store data, and the non-transient state wherein in context can refer to not to carry out transfer instruction/data via signal.Such as, non-transient state memory storage can be volatibility (and may in response to power-off lose store call instruction/data) or non-volatile.More specifically, in an embodiment of portable set such as mobile phone, panel computer etc., computing machine accessible storage medium 200 can comprise storer 12 and/or nonvolatile memory and such as comprise flash memories in a device.
Computing machine accessible storage medium 200 in Fig. 9 can store various software as herein described.Such as, computing machine accessible storage medium can store one or more in display driver 70, GPU driver 72, other media drives 76, CPU filtrator 80, ISP driver 74, other peripheral equipment drivers 78, PMGR driver 82 and Memory Controller driver 84.Various driver 70,72,74,76,78,82 and 84 and CPU filtrator 80 can be included in when being performed by processor 28 and realize above for the instruction of the operation described in each driver.In addition, PMGR driver 82 can be included in when being performed and realize Fig. 2, the instruction of the operation shown in 3,5 and/or 8.CPU filtrator 80 can be included in the instruction realizing the operation shown in Fig. 7 and/or Fig. 8 when being performed.Mounting medium can comprise computing machine accessible storage medium and transmission medium such as wired or wireless transmission.
Next turn to Figure 10, it illustrates the block diagram of an embodiment of system 150.In an illustrated embodiment, system 150 comprises at least one example of the SOC10 being couple to one or more peripherals 154 and external storage 12.Provide power supply 156, this power supply is supplied supply voltage to SOC10 and is supplied one or more supply voltage to storer 12 and/or peripherals 154.In certain embodiments, the more than one example (also can comprise more than one storer 12) of SOC10 can be comprised.
According to the type of system 150, peripherals 154 can comprise the circuit of any desired.Such as, in one embodiment, system 150 can be mobile device (as personal digital assistant (PDA), smart phone etc.), and peripherals 154 can comprise the equipment for all kinds radio communication, such as wifi, bluetooth, honeycomb, GPS etc.Peripherals 154 also can comprise additional memory devices, and this additional memory devices comprises RAM memory device, solid-state storage device or disk storage device.Peripherals 154 can comprise user interface apparatus such as display screen, and this display screen comprises touch display screen or many touch display screens, keyboard or other input equipments, microphone, loudspeaker etc.In certain embodiments, display 20 and/or imageing sensor 26 can be peripherals 154.In other embodiments, system 150 can be the computing system (such as, desktop PC, notebook computer, workstation, all-in-one desktop machine etc.) of any type.
External storage 12 can comprise the storer of any type.Such as, external memory storage 12 can be SRAM, dynamic ram (DRAM) such as synchronous dram (SDRAM), double data rate (DDR, DDR2, DDR3 etc.) SDRAM, RAMBUSDRAM etc.This external memory storage 12 can comprise one or more memory modules that memory devices is installed to, such as single row direct insert memory modules (SIMM), dual inline memory module (DIMM) etc.Alternatively, external memory storage 12 can be included in chip-stack or encapsulate during lamination is specifically implemented the one or more memory devices be arranged on SOC10.
Once open more than having fully understood, then a lot of variants and modifications will become apparent for a person skilled in the art.The present invention is intended to be interpreted as by following claims containing this type of variants and modifications all.
Claims (15)
1. a method, comprising:
The free screen of the display device in detection system; And
In response to described free screen being detected, frame data are allowed to be cached in intrasystem memory cache, wherein do not detecting that the time durations of described free screen is forbidden carrying out high-speed cache to frame data, wherein said memory cache is coupled to accumulator system and is configured to carry out high-speed cache to the data of accessing in the memory systems, wherein in response to the hit come check in described memory cache of storage operation in the described accumulator system of access.
2. method according to claim 1, also comprises:
In response to described free screen being detected, revise the power management configuration in described memory cache.
3. method according to claim 2, wherein said amendment comprises the high-speed cache power-off forbidden in described memory cache.
4. according to the method in claim 2 or 3, wherein said amendment comprises the reduction of forbidden storage device cache size.
5. the method according to any one of claim 1-4, also comprises:
Detect and exit from described free screen; And
Exit described in detecting, forbid described frame data to be cached in described memory cache.
6. method according to claim 5, also comprises and exiting described in detecting:
Allow the high-speed cache power-off in described memory cache; And
Memory cache size is allowed to reduce.
7. the method according to claim 5 or 6, exits described in wherein detecting and comprises at least one parts detected in described system and will be energized.
8. the method according to any one of claim 5-7, exits to comprise detecting that graphics device is asking to be energized described in wherein detecting.
9. the method according to any one of claim 5-8, also comprises:
Filter and wake/sleep event up for one or more processor in described system; And
In response to filtered waking up/sleep event detect described in exit, filter wake up/sleep event indicates described processor may be movable.
10. a device, comprising:
Accumulator system;
Memory cache, described memory cache is coupled to described accumulator system and is configured to carry out high-speed cache to the data of accessing in the memory systems, wherein in response to the hit come check in described memory cache of storage operation in the described accumulator system of access; With
Display controller, described display controller is coupled to described memory cache and described accumulator system, wherein said display controller is configured to generate storage operation to read storage at least one frame buffer in the memory systems to be shown on the display device by image, and wherein said display controller is programmed during use in response to the described image on described display device to be the free time, and request distributes in described memory cache.
11. devices according to claim 10, wherein said display controller is programmed it is dynamic and do not ask to distribute in described memory cache in response to the described image on described display device during use.
12. devices according to claim 10 or 11, wherein in response to N number of continuous static frame being detected, described image on described display device is detected as idle, wherein N be greater than 1 integer, and wherein said image is detected as dynamically, unless described N number of continuous static frame is detected.
13. devices according to claim 11 or 12, wherein in response to described still image and described dynamic image being detected, the power management configuration of described memory cache is modified.
14. devices according to claim 13, wherein in response to described still image, described power management configuration is modified with cache-inhibited power-off.
15. devices according to claim 13 or 14, wherein in response to described still image, described power management configuration is modified with the automatic adjust size of cache-inhibited.
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| CN108196809A (en) | 2018-06-22 |
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