CN105182377B - A kind of receiver board and receiver - Google Patents
A kind of receiver board and receiver Download PDFInfo
- Publication number
- CN105182377B CN105182377B CN201510520389.7A CN201510520389A CN105182377B CN 105182377 B CN105182377 B CN 105182377B CN 201510520389 A CN201510520389 A CN 201510520389A CN 105182377 B CN105182377 B CN 105182377B
- Authority
- CN
- China
- Prior art keywords
- data
- storage region
- read
- dual port
- port ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/33—Multimode operation in different systems which transmit time stamped messages, e.g. GPS/GLONASS
Abstract
The embodiment of the invention discloses a kind of receiver board and receivers.In the embodiment of the present invention, baseband processing module is used to obtain the first data according to satellite digital intermediate-freuqncy signal, writes first data into N number of dual port RAM, and sends the first instruction to positioning calculation module；And in the case where receiving the second instruction, the second data are read from N number of dual port RAM；N is the integer more than 1；Positioning calculation module receives, in the case where receiving the first instruction, the first data to be read from N number of dual port RAM by EMIF buses；According to the first data, the second data are obtained, the second data are written in N number of dual port RAM by EMIF buses, and the second instruction is sent to baseband processing module.The ability of the data interaction between baseband processing module and positioning calculation module is effectively increased in the embodiment of the present invention by EMIF buses and N number of dual port RAM.
Description
Technical field
The present invention relates to technical field of satellite navigation more particularly to a kind of receiver boards and receiver.
Background technology
In the system of global navigation satellite reception at present, mainly include and mainly include Chinese BDS (BeiDou
Navigation Satellite System, Beidou satellite navigation system), GPS of America (Global Navigation
Satellite System, global positioning system), Russia's GLONASS (GLONASS) and European galileo (Galileo), often
A satellite system has multiple frequency point signals again, has been added together more than ten of frequency point.The multimode that more multifrequency point can be accommodated for design is more
Frequency receiver, the Satellite Tracking channel in base band may reach hundreds of, and baseband processing module is each with positioning calculation module
Secondary data interaction amount can reach 10K or so.Satellite navigation receiver baseband processing module and positioning calculation module communication means
There are mainly two types of modes：First way：CPU (Central Processing Unit, processor) in positioning calculation module
Pass through the register in bus access baseband processing module；CPU in second way positioning calculation module passes through bus mode
Access the data of the single RAM (Random Access Memory, random access memory) in baseband processing module.
Satellite data is latched into register group by above-mentioned first way, baseband processing module at regular intervals, so
The CPU in positioning calculation module passes through the data in bus read-write register, therefore, the bus data update in this mode afterwards
Rate is by the clock control of baseband processing module, and communication efficiency is very low, and general maximum also can only achieve tens traffic rate；
In addition, all satellite channel registers are connect by a data selector with address logic, baseband processing module is influenced
The success rate of FPGA comprehensive wirings.
The above-mentioned second way using single RAM as the data buffering between bus and base band, on the one hand can lead to base
The fan-in of RAM is too big when tape handling inside modules connect up, and on the other hand, traditional single port RAM only has a data address port, reads
Writing cannot be carried out at the same time, and communication efficiency is relatively low.In addition, the data of all satellite channels are all written to one by baseband processing module
The long period is needed in RAM, bus utilization ratio when reducing communication, and when channel is enough, it is possible to it cannot meet and defend
Real-time processing time needed for star tracking.
To sum up, there is an urgent need for a kind of reliable and stable methods at present to be used to implement between baseband processing module and positioning calculation module
Data interaction.
Invention content
The embodiment of the present invention provides a kind of receiver board, to improve between baseband processing module and positioning calculation module
Data exchange capability.
A kind of receiver board provided in an embodiment of the present invention, including radio-frequency module, baseband processing module and positioning calculation
Module, the radio-frequency module are connect with the baseband processing module, and the baseband processing module leads to the positioning calculation module
Cross the connection of external memory interface EMIF buses；The baseband processing module includes N number of dual port RAM；The radio-frequency module is used for
By being handled the satellite navigation signals received to obtain satellite digital intermediate-freuqncy signal, and believing the satellite digital intermediate frequency into
Number it is sent to the baseband processing module；
The baseband processing module is used to obtain the first data according to the satellite digital intermediate-freuqncy signal received, by institute
It states the first data to be written in N number of dual port RAM, and the first instruction is sent to the positioning calculation module；And receiving second
In the case of instruction, the second data are read from N number of dual port RAM；N is the integer more than 1；
The positioning calculation module is used in the case where receiving first instruction, by the EMIF buses from institute
It states and first data is read in N number of dual port RAM；According to first data, second data are obtained and by described
Second data are written in N number of dual port RAM EMIF buses, and send the second instruction to the baseband processing module.
Preferably, the dual port RAM includes the first reading-writing port and the second reading-writing port；
The baseband processing module is used to first data N number of twoport is written by first reading-writing port
Second data are read from N number of RAM in RAM and by first reading-writing port；
The positioning calculation module is used to second data N number of twoport is written by second reading-writing port
First data are read from N number of dual port RAM in RAM and by second reading-writing port.
Preferably, the speed that the baseband processing module reads and writes data by first reading-writing port is believed by the first clock
Number control；
The speed that the positioning calculation module reads and writes data by second reading-writing port is controlled by second clock signal.
Preferably, the dual port RAM includes the first storage region and the second storage region；
The baseband processing module further includes the first read-write selecting unit；The first read-write selecting unit is used for by described in
First data are selectively written N number of first storage region or N number of second storage region and selectively from N
A first storage region or N number of second storage region read second data；
The positioning calculation module further includes the second read-write selecting unit；The second read-write selecting unit is used for by described in
Second data are selectively written N number of first storage region or N number of second storage region and selectively from N
A first storage region or N number of second storage region read first data；
Storage region and the described second read-write selecting unit write-in of the first data is written in the first read-write selecting unit
The storage region of second data is different.
Preferably, the first read-write selecting unit includes, N number of internal logic controls correspondingly with N number of RAM；
The first read-write selecting unit is used to first data N number of first storage region is selectively written
Or N number of second storage region and selectively from N number of first storage region or N number of second storage region
Second data are read, including：
First data are selectively written N number of described first by writing logic and deposited by the N number of internal logic control
Storage area domain or N number of second storage region and by reading logic selectively from N number of first storage region or N number of
Second storage region reads second data.
Preferably, the second read-write selecting unit includes EMIF bus control units；The baseband processing module further includes
RAM selects logic；
The second read-write selecting unit is used to second data N number of first storage region is selectively written
Or N number of second storage region and selectively from N number of first storage region or N number of second storage region
First data are read, including：
The EMIF bus control units select logic that second data are selectively written N number of institute by the RAM
State the first storage region or N number of second storage region and selectively from N number of first storage region or N number of institute
It states the second storage region and reads first data.
Preferably, first data include each satellite IQ channels accumulation amount, chip count value, code week count value, carrier wave
All count values；Second data include shift register taps word, shift register initial status word, shift register cut-off
State, carrier frequency control word, carrier phase control word, code frequency control word, code phase control word.
Preferably, the baseband processing module is field programmable gate array module FPGA；The positioning calculation module is
Digital signal processor DSP.
Preferably, the positioning calculation module includes enhanced direct memory access EDMA controllers；
The EDMA controllers are used to that the EMIF buses to be controlled to read first data from N number of dual port RAM,
And second data are written in N number of dual port RAM the control EMIF buses.
A kind of receiver provided in an embodiment of the present invention, including the receiver board described in antenna and above-described embodiment；
The satellite navigation signals for receiving satellite navigation signals, and are sent to the receiver card by the antenna
Card.
Receiver board in the embodiment of the present invention includes radio-frequency module, baseband processing module and positioning calculation module, penetrates
Frequency module is connect with baseband processing module, and baseband processing module is connect with positioning calculation module by EMIF buses；Base-Band Processing
Module includes N number of dual port RAM；Radio-frequency module is used for by being handled to obtain satellite digital to the satellite navigation signals received
Intermediate-freuqncy signal, and the satellite digital intermediate-freuqncy signal is sent to baseband processing module；Baseband processing module is used for according to satellite
Digital medium-frequency signal obtains the first data, writes first data into N number of dual port RAM, and sends first to positioning calculation module
Instruction；And in the case where receiving the second instruction, the second data are read from N number of dual port RAM；N is the integer more than 1；
Positioning calculation module is received in the case where receiving the first instruction, and the is read from N number of dual port RAM by EMIF buses
One data；According to the first data, the second data are obtained, the second data are written in N number of dual port RAM by EMIF buses, and
The second instruction is sent to baseband processing module.Baseband processing module and positioning calculation module, which use, in the embodiment of the present invention is based on
The data communication mode of EMIF buses and N number of dual port RAM so that baseband processing module can be in a parallel fashion simultaneously to N number of
Dual port RAM is written and read, and effectively shortens the time of baseband processing module read-write RAM, it is comprehensive to improve baseband processing module FPFA
Close the success rate of wiring；Moreover, baseband processing module and positioning calculation are effectively increased by EMIF buses and N number of dual port RAM
The ability of data interaction between module.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for this
For the those of ordinary skill in field, without having to pay creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1 is a kind of structure diagram of receiver board provided in an embodiment of the present invention；
Fig. 2 is a kind of concrete structure schematic diagram of receiver board provided in an embodiment of the present invention；
Fig. 3 is a kind of data interaction schematic diagram provided in an embodiment of the present invention；
Fig. 4 is EMIF buses provided in an embodiment of the present invention and the connected mode schematic diagram of the dual port RAM in FPGA；
Fig. 5 is a kind of structure diagram of receiver provided in an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention is made below in conjunction with attached drawing into
It is described in detail to one step, it is clear that described embodiment is only the implementation of part of the embodiment of the present invention rather than whole
Example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
All other embodiment, shall fall within the protection scope of the present invention.
Fig. 1 is a kind of structure diagram of receiver board provided in an embodiment of the present invention, should suitable for navigation neceiver
Receiver board includes the radio-frequency module 102, baseband processing module 103 and the positioning calculation module 104 that are connect with antenna 101, institute
It states radio-frequency module 102 to connect with the baseband processing module 103, the baseband processing module 103 and the positioning calculation module
104 are connected by EMIF (External Memory Interface, external memory interface) bus；The Base-Band Processing mould
Block 103 includes N number of dual port RAM；
The radio-frequency module 102 is used for by being handled the satellite navigation signals received to obtain satellite digital intermediate frequency
Signal, and the satellite digital intermediate-freuqncy signal is sent to the baseband processing module 103；
The baseband processing module 103 is used to obtain the first data according to the satellite digital intermediate-freuqncy signal received,
First data are written in N number of dual port RAM, and the first instruction is sent to the positioning calculation module 104；Receiving
In the case of two instructions, the second data are read from N number of dual port RAM；N is the integer more than 1；
The positioning calculation module 104 is used to, in the case where receiving first instruction, pass through the EMIF buses
First data are read from N number of dual port RAM；According to first data, second data are obtained, by described
Second data are written in N number of dual port RAM by EMIF buses, and send second to the baseband processing module 103
Instruction.
Baseband processing module and positioning calculation module are used based on EMIF buses and N number of dual port RAM in the embodiment of the present invention
Data communication mode so that baseband processing module can in a parallel fashion simultaneously N number of dual port RAM is written and read, effectively
The time of baseband processing module read-write RAM is shortened, improves the success rate of baseband processing module FPGA comprehensive wirings；Moreover,
The data interaction between baseband processing module and positioning calculation module is effectively increased by EMIF buses and N number of dual port RAM
Ability.
The satellite navigation signals that antenna receives in the embodiment of the present invention can be the signal of a variety of satellite navigation systems, preferably
, satellite navigation signals are one or several in the following contents：Global positioning system (Global Positioning
System, GPS), Beidou satellite navigation system (BeiDou Navigation Satellite System, BDS), global satellite
Navigation system (GLONASS), Galileo satellite navigation (GALILEO).
In the embodiment of the present invention, after antenna receives satellite navigation signals, the radio frequency in receiver board is sent it to
Module, radio-frequency module obtain satellite digital intermediate-freuqncy signal, and by described in by being handled the satellite navigation signals received
Satellite digital intermediate-freuqncy signal is sent to the baseband processing module, and the baseband processing module is according to the satellite number received
Word intermediate-freuqncy signal obtains the first data.
In the embodiment of the present invention, first data include each satellite IQ channels accumulation amount, chip count value, count in code week
Value, carrier cycle count value；Second data include shift register taps word, shift register initial status word, displacement
Register cut-off state, carrier frequency control word, carrier phase control word, code frequency control word, code phase control word.
In the embodiment of the present invention, dual port RAM includes the first reading-writing port and the second reading-writing port, so that Base-Band Processing
Module and positioning calculation module can access N number of dual port RAM by different reading-writing ports, and specifically, baseband processing module will
First data are written by first reading-writing port in N number of dual port RAM and pass through first reading-writing port
Second data are read from N number of RAM；Positioning calculation module is used to second data passing through the second port
It is written in N number of dual port RAM and first data is read from N number of dual port RAM by the second port.
Since baseband processing module and positioning calculation module can access N number of dual port RAM by different reading-writing ports, because
This, the speed of baseband processing module and positioning calculation module read-write data can also be controlled by different clock signals.
Specifically, baseband processing module reads and writes the speed of data by the first clock signal control by first reading-writing port
System, the speed that positioning calculation module reads and writes data by second reading-writing port are controlled by second clock signal, so as to fulfill
Baseband processing module and positioning calculation module are to the operating clock of dual port RAM mutual indepedent, and read-write is not interfere with each other.For example, base
Data parallel is written in dual port RAM with the clock of 50M for tape handling module, and the clock of 200M can be used by writing rear positioning calculation module
Data are read from dual port RAM, the two is synchronized without keeping, so that positioning calculation module can access at faster speed
Dual port RAM effectively increases the efficiency of the access dual port RAM of positioning calculation module.
In the embodiment of the present invention, the first instruction can be that baseband processing module is shaken hands to one that positioning calculation module is sent
Signal, the second instruction can be the handshake that positioning calculation module is sent to baseband processing module.
In the embodiment of the present invention, baseband signal processing module is can be with FPGA (FieldProgrammable Gate
Array, field programmable gate array module)；Positioning calculation module can be DSP (DigitalSignal Processors, number
Word signal processor).Receiver board based on DSP and FPGA given full play to Base-Band Processing process in FPGA may be programmed and
Data-handling capacity powerful DSP.
FPGA is connected with DSP by EMIF buses, realizes two-way communication.Specifically, FPGA is by the satellite data after capture
After (the first data) are written to N number of dual port RAM, a handshake is sent to DSP, after DSP receives handshake, is passed through
EMIF buses read satellite data from N number of dual port RAM, and obtain loop parameter value (the second data) according to satellite data.DSP
The second data are written in N number of dual port RAM by EMIF buses, and a handshake is sent to FPGA.FPGA is received
After handshake, the second data are taken out from N number of dual port RAM, with the parameter value according to each satellite channel of the second data point reuse, are protected
Demonstrate,prove the tight tracking to satellite-signal.
In the embodiment of the present invention, the size of N can once newer data volume be set according to base band satellite channel, simultaneously also
The fan-in for being considered as FPGA wirings is fanned out to size.For example, base band Satellite Tracking port number is M, per the newer total data of subchannel
It measures as Q, it is S to adjust channel parameters data volume every time, then the data volume in each RAM can be designed according to (Q+S)/N,
N, Q and S determines the bit wide and depth of RAM.In the embodiment of the present invention, the fan-in of the wiring of RAM is most when N is 1, in FPGA
Greatly, it is unfavorable for temporal constraint, it is therefore preferred that N is the integer more than 1.
After Q data are disposably written in dual port RAM due to FPGA, handshake just is sent to DSP, therefore,
The value of port number M is bigger, and the value of total amount of data Q is just higher, and the time needed for FPGA write-in data is longer, it is difficult to meet demand.
To further improve the data transmission efficiency between FPGA and DSP, the embodiment of the present invention is preferably by each dual port RAM in FPGA
Storage region be divided into two parts, i.e. the first storage region and the second storage region.Baseband processing module further includes the first reading
Selecting unit is write, for first data to be selectively written N number of first storage region or N number of second storage
Region and selectively second data are read from N number of first storage region or N number of second storage region；
Positioning calculation module further includes the second read-write selecting unit, for second data to be selectively written N number of described first
Storage region or N number of second storage region and selectively from N number of first storage region or N number of described second
Storage region reads first data.
In the embodiment of the present invention, the storage region of first read-write selecting unit the first data of write-in and the second read-write selection are single
The storage region that second data are written in member is different.If first data are written N number of first by the first read-write selecting unit
N number of second storage region is written in second data by storage region, then correspondingly, the second read-write selecting unit；If the first read-write choosing
It selects unit and N number of second storage region is written into first data, then correspondingly, the second read-write selecting unit writes the second data
Enter N number of first storage region.
Fig. 2 is a kind of concrete structure schematic diagram of receiver board provided in an embodiment of the present invention.It is as described above, this hair
The value of N in bright embodiment can be configured.The specific knot of receiver board in the embodiment of the present invention for convenience of explanation herein
Structure only shows two dual port RAMs in FPGA, i.e. dual port RAM 1 and dual port RAM 2.Wherein, dual port RAM 1 includes storage region 1a
With storage region 1b, dual port RAM 2 includes storage region 2a and storage region 2b.The structure of N number of dual port RAM and two dual port RAMs
Structure it is similar, can refer to the structure of two dual port RAMs, details are not described herein again.
Specifically, in the embodiment of the present invention, the first read-write selecting unit can include and the one-to-one N of N number of dual port RAM
A internal logic control, each internal logic control includes a reading logic and one is write logic, wherein, it reads logic and is used for from double
Data are read in a storage region of mouth RAM, write logic for writing data into another storage region of dual port RAM.
By writing logic N number of first storage region or N is selectively written in first data by N number of internal logic control
It a second storage region and is selectively deposited by reading logic from N number of first storage region or N number of described second
Read second data in storage area domain.
Second read-write selecting unit can be EMIF bus control units, wherein, a part of address wire in EMIF buses with
In dual port RAM address wire connection, another part in FPGA RAM select it is logically contiguous connect, this partial address line can lead to
Crossing the mode of combinational logic, piece selects all dual port RAMs successively, logic is selected to be counted described second so as to fulfill by the RAM
According to N number of first storage region or N number of second storage region being selectively written and selectively from N number of described
First storage region or N number of second storage region read first data.
DSP in the embodiment of the present invention includes processor, and EMIF buses can be controlled to carry out the reading of data by processor
It takes and is written.Preferably, EDMA (Enhanced Direct Memory Access, increasing can also be included in the embodiment of the present invention
Strong type direct memory access) controller, since EDMA controllers have the energy of the backstage bulk data transfer independently of processor
Therefore power, controls EMIF buses to carry out the reading and write-in of data, can effectively reduce the place in DSP by EDMA controllers
The utilization rate of device is managed, gives full play to the high speed performance of DSP so that processor there can be more resources to go to complete more multichannel
Satellite positioning resolves, and reduces the cost of DSP type selectings.
Fig. 3 is a kind of data interaction schematic diagram provided in an embodiment of the present invention.Similarly, the present invention is implemented for convenience of explanation
Data exchange process in example, only shows two dual port RAMs in FPGA.The data exchange process of N number of dual port RAM is double with two
The data exchange process of mouth RAM is similar, can refer to two dual port RAMs and obtains, details are not described herein again.
As shown in figure 3, FPGA includes dual port RAM 1 and dual port RAM 2, the first internal logic controls to control twoport
The reading and write-in of data in RAM1, the second internal logic control the reading and write-in for controlling data in dual port RAM 2；Its
In, the control of the first internal logic can be write data by writing logic in storage region 1b, by reading logic from storage region
Data are read in 1a, the control of the second internal logic can be write data by writing logic in storage region 2b, by reading logic
Data are read from storage region 2a；Alternatively, the control of the first internal logic can also write data into memory block by writing logic
In the 1a of domain, data are read from storage region 1b by reading logic, the control of the second internal logic can also be by writing logic by number
According in write-in storage region 2a, data are read from storage region 2b by reading logic.A kind of feelings therein are only shown in Fig. 3
Shape, the embodiment of the present invention are not specifically limited this.It can also include the first signal processing unit in FPGA, for receiving DSP
The handshake of transmission and to DSP send handshake.
DSP includes processor, EDMA controllers, EMIF bus control units, can also include second signal processing unit,
Handshake is sent for the handshake for receiving FPGA transmissions and to FPGA.On the one hand, processor is used in second signal
After processing unit receives the handshake of FPGA transmissions, start EDMA controllers, EMIF is controlled by EMIF bus control units
Bus reads data from the dual port RAM of FPGA；On the other hand, processor is used to pass through EDMA controllers, the total line traffic controls of EMIF
After device and EMIF bus processed is write data into the dual port RAM of FPGA, instruction second signal processing unit is sent to FPGA
Handshake, FPGA to be notified to be ready for data.
It is described further with reference to data interaction flows of the Fig. 3 between FPGA and DSP.
FPGA is calculated by capture, tracking to satellite including each path in-phase branch, quadrature branch coherent integration value
With code week count etc. satellite datas, by the first internal logic control and the second internal logic control in write logic by satellite number
According to the storage region 1b and storage region 2b being written in two dual port RAMs；After data write, FPGA by the first signal at
It manages unit and sends a handshake to DSP, for notifying DSP from the storage region 1b and storage region in two dual port RAMs
Data are read in 2b.First signal processing list of the processor in determining that second signal processing unit receives FPGA in DSP
After the handshake that member is sent, start EDMA controllers, EMIF buses are controlled by EMIF bus control units, using combinational logic
Mode read data from the storage region 1b of FPGA and storage region 2b.Processor in DSP to the data that read into
Row processing, and by data such as the carrier shift amount to generate and chip offsets, pass through EDMA controllers, EMIF bus marcos
Device is sent to EMIF buses, and then by EMIF buses, the memory block of two dual port RAMs is written to by the way of combinational logic
Domain 1a and storage region 2a；After data write, first signal processing list of the second signal processing unit into FPGA in DSP
Member sends a handshake, for FPGA is notified to complete the write-in of data.The first signal processing unit in FPGA connects
After receiving handshake, by the reading logic in the control of the first internal logic and the control of the second internal logic from two dual port RAMs
Storage region 1a and storage region 2a in read data.FPGA is used in the storage region 1a and storage region 2a read
The carrier frequency control word of M satellite channel of data update and code frequency control word, so as to preferably capture or tracking satellite letter
Number.
EMIF buses in the embodiment of the present invention and the connection mode of the dual port RAM in FPGA are specifically introduced below.
That selected in the embodiment of the present invention is the FPGA of Xilinx, and the block storage resource that FPGA is internally integrated can match
It is set to N number of dual port RAM, access speed can reach hundreds of million.There are two completely self-contained read-write ends for dual port RAM inside FPGA
Mouthful, it is the first reading-writing port and the second reading-writing port respectively, two reading-writing ports share the memory space of a RAM, and have
Independent address wire, data line, read-write control line, therefore, for any one RAM, can both be read by the first reading-writing port
Data are write, can also data be read and write by the second reading-writing port.In the embodiment of the present invention, DSP can be by EMIF buses, from
One reading-writing port accesses dual port RAM, and FPGA can access dual port RAM by the second reading-writing port, realize DSP and FPGA share
The memory space of dual port RAM.
Fig. 4 is EMIF buses provided in an embodiment of the present invention and the connected mode schematic diagram of the dual port RAM in FPGA.Equally
Ground, the EMIF buses in the embodiment of the present invention and the connection mode of dual port RAM, only show two pairs in FPGA for convenience of explanation
Mouth RAM, i.e. RAM1 and RAM2.EMIF buses and the connection mode of N number of dual port RAM, can refer to EMIF buses and two dual port RAMs
It obtains, details are not described herein again.
In the embodiment of the present invention, the bit wide of EMIF data/address bus E_DATA can be configured according to actual conditions, for example, can
It is configured to 8,16,32,64.Dual port RAM in the embodiment of the present invention includes the first reading-writing port and the second read-write
Port, the corresponding pin of the first reading-writing port include data-in port DIA, data-out port DOA, address wire ADRRA,
Read/write selection signal WEA, enable signal ENA, clock signal clk A, the corresponding pin of the second reading-writing port are inputted including data
Port DIB, data-out port DOB, address wire ADRRB, read/write selection signal WEB, enable signal ENB, clock signal
CLKB。
The connection relation of each pin and dual port RAM in EMIF bus control units is specifically introduced with reference to Fig. 4.The present invention
In embodiment, the pin of EMIF bus control units includes EMIF data/address bus E_DATA, SOE signal, EMIF address bus E_
ADDR, clock output signal E_CLKOUT1, address strobe control signal ADS, read-write control signal WE, chip selection signal CE, byte
Control BE.
As shown in figure 4, EMIF data/address bus E_DATA is inputted by data selector with the data of two dual port RAMs respectively
Port DIA is connected with data-out port DOA, and is to read data from dual port RAM or write data by the control of SOE signals
In dual port RAM.E_ADDR points of EMIF address bus is a high position [22:13] address wire and low level [12:0] two parts of address wire,
Wherein, a high position [22:13] piece of address wire and dual port RAM selects combinational logic to connect, piece select combinational logic respectively with two twoports
The ENA connections of RAM, select EMIF buses carry out data interaction with which dual port RAM by way of combinational logic；Low level
[12:0] address wire is connected with the address wire ADRRA of the first reading-writing port of dual port RAM, for accessing whole storages in RAM
Space.Clock output signal E_CLKOUT1 in EMIF bus control units respectively with the first reading-writing port of two dual port RAMs
Clock signal clk A connections, for controlling the speed of DSP read-write dual port RAMs.ADS, WE, CE, BE signal are through the group inside FPGA
Combinational logic circuit, on the one hand, for controlling RAM selections logic whether effective, on the other hand, for the WEA with two dual port RAMs
It is connected, control DSP is to the read-write capability of FPGA internal dual ports RAM.
The internal logic control in FPGA and the connection relation of dual port RAM are specifically introduced with reference to Fig. 4.
In the embodiment of the present invention, FPGA include with the inside of dual port RAM 1 corresponding first read-write logic and with dual port RAM 2
Corresponding second inside read-write logic.First inside read-write logic and second inside read-write logic respectively with dual port RAM 1 and twoport
The address wire ADRRB connections of the second reading-writing port of RAM2, for accessing whole memory spaces in RAM.First inside is read and write
Logic is connected by first selector with the data-in port DIB in dual port RAM 1 and data-out port DOB, in second
Portion's read-write logic is connected by second selector with the data-in port DIB in dual port RAM 2 and data-out port DOB,
So as to realize that it is to read data from dual port RAM or write data to control FPGA by first selector and second selector
Enter in dual port RAM.First inside read-write logic is connect respectively with WEB, ENB in dual port RAM 1, the second inside read-write logic point
It is not connect with WEB, ENB in dual port RAM 2.First inside read-write logic and second inside read-write logic also respectively with twoport
RAM1 is connected with the Clock Signal pin CLKB of dual port RAM 2, for controlling the speed of FPGA read-write dual port RAMs.
In the embodiment of the present invention, since the DSP speed for accessing two dual port RAMs is by the clock in EMIF bus control units
Output signal control, and FPGA accesses what the speed of two dual port RAMs was controlled by its internal clock signal, thus DSP and
FPGA is mutual indepedent to the operating clock of dual port RAM, and read-write is not interfere with each other.For example, data parallel is written with 50M clocks by FPGA
In dual port RAM, data can be read with the clock of 200M from dual port RAM by writing rear DSP, and the two is synchronized without keeping, so as to make
Dual port RAM can be accessed at faster speed by obtaining DSP, effectively increase the efficiency of the access dual port RAM of DSP.
Receiver board in the embodiment of the present invention includes radio-frequency module, baseband processing module and positioning calculation module, penetrates
Frequency module is connect with baseband processing module, and baseband processing module is connect with positioning calculation module by EMIF buses；Base-Band Processing
Module includes N number of dual port RAM；Radio-frequency module is used for by being handled to obtain satellite digital to the satellite navigation signals received
Intermediate-freuqncy signal, and the satellite digital intermediate-freuqncy signal is sent to baseband processing module；Baseband processing module is used for according to satellite
Digital medium-frequency signal obtains the first data, writes first data into N number of dual port RAM, and sends first to positioning calculation module
Instruction；And in the case where receiving the second instruction, the second data are read from N number of dual port RAM；N is the integer more than 1；
Positioning calculation module is received in the case where receiving the first instruction, and the is read from N number of dual port RAM by EMIF buses
One data；According to the first data, the second data are obtained, the second data are written in N number of dual port RAM by EMIF buses, and
The second instruction is sent to baseband processing module.Baseband processing module and positioning calculation module, which use, in the embodiment of the present invention is based on
The data communication mode of EMIF buses and N number of dual port RAM so that baseband processing module can be in a parallel fashion simultaneously to N number of
Dual port RAM is written and read, and effectively shortens the time of baseband processing module read-write RAM, it is comprehensive to improve baseband processing module FPGA
Close the success rate of wiring；Moreover, baseband processing module and positioning calculation are effectively increased by EMIF buses and N number of dual port RAM
The ability of data interaction between module.
Fig. 5 be a kind of structure diagram of receiver provided in an embodiment of the present invention, the receiver include antenna 501 and
Receiver board 502 as described in above-described embodiment；
The antenna 501 is used to receive satellite navigation signals, and the satellite navigation signals are sent to the receiver
Board 502.
It can be seen from the above：Receiver board in the embodiment of the present invention includes radio-frequency module, Base-Band Processing mould
Block and positioning calculation module, radio-frequency module are connect with baseband processing module, and baseband processing module passes through with positioning calculation module
EMIF buses connect；Baseband processing module includes N number of dual port RAM；Radio-frequency module is used for by believing the satellite navigation received
It number is handled to obtain satellite digital intermediate-freuqncy signal, and the satellite digital intermediate-freuqncy signal is sent to baseband processing module；Base
Tape handling module is used to obtain the first data according to satellite digital intermediate-freuqncy signal, writes first data into N number of dual port RAM, and
The first instruction is sent to positioning calculation module；And in the case where receiving the second instruction, is read from N number of dual port RAM
Two data；N is the integer more than 1；Positioning calculation module is received in the case where receiving the first instruction, total by EMIF
Line reads the first data from N number of dual port RAM；According to the first data, the second data are obtained, by EMIF buses by the second data
It is written in N number of dual port RAM, and the second instruction is sent to baseband processing module.In the embodiment of the present invention baseband processing module and
Positioning calculation module uses the data communication mode based on EMIF buses and N number of dual port RAM so that baseband processing module can be with
Parallel form is simultaneously written and read N number of dual port RAM, effectively shortens the time of baseband processing module read-write RAM, improves
The success rate of baseband processing module FPGA comprehensive wirings；Moreover, base band is effectively increased by EMIF buses and N number of dual port RAM
The ability of data interaction between processing module and positioning calculation module.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation
Property concept, then additional changes and modifications may be made to these embodiments.So appended claims be intended to be construed to include it is excellent
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of receiver board, which is characterized in that described including radio-frequency module, baseband processing module and positioning calculation module
Radio-frequency module is connect with the baseband processing module, and the baseband processing module passes through external storage with the positioning calculation module
Device interface EMIF buses connect；The baseband processing module includes N number of dual port RAM；N is the integer more than 1；
The receiver board includes M base band Satellite Tracking channel；The radio-frequency module is used to lead the satellite received
Boat signal is handled, and obtains satellite digital intermediate-freuqncy signal, and the satellite digital intermediate-freuqncy signal is sent at the base band
Manage module；
The baseband processing module is used to, according to the satellite digital intermediate-freuqncy signal received, obtain the M base band satellite
First data of tracking channel；After first data of the M base band Satellite Tracking channel are written N number of dual port RAM simultaneously, to
The positioning calculation module sends the first instruction；And in the case where receiving the second instruction, from N number of dual port RAM
Read the second data of the M base band Satellite Tracking channel；
The positioning calculation module is used in the case where receiving first instruction, by the EMIF buses from the N
The first data of the M base band Satellite Tracking channel are read in a dual port RAM；According to first data, the M are obtained
Second data of base band Satellite Tracking channel and by the EMIF buses by the of the M base band Satellite Tracking channel
After N number of dual port RAM is written in two data simultaneously, the second instruction is sent to the baseband processing module.
2. receiver board as described in claim 1, which is characterized in that the dual port RAM includes the first reading-writing port and the
Two reading-writing ports；
The baseband processing module is used to first data N number of dual port RAM is written by first reading-writing port
In and second data are read from N number of RAM by first reading-writing port；
The positioning calculation module is used to second data N number of dual port RAM is written by second reading-writing port
In and first data are read from N number of dual port RAM by second reading-writing port.
3. receiver board as claimed in claim 2, which is characterized in that the baseband processing module is read and write by described first
The speed of port read write data is controlled by the first clock signal；
The speed that the positioning calculation module reads and writes data by second reading-writing port is controlled by second clock signal.
4. receiver board as described in claim 1, which is characterized in that the dual port RAM includes the first storage region and the
Two storage regions；
The baseband processing module further includes the first read-write selecting unit；The first read-write selecting unit is used for described first
Data are selectively written N number of first storage region or N number of second storage region and selectively from N number of institutes
It states the first storage region or N number of second storage region reads second data；
The positioning calculation module further includes the second read-write selecting unit；The second read-write selecting unit is used for described second
Data are selectively written N number of first storage region or N number of second storage region and selectively from N number of institutes
It states the first storage region or N number of second storage region reads first data；
The first read-write selecting unit is written the storage region of the first data and described second and reads and writes described in selecting unit write-in
The storage region of second data is different.
5. receiver board as claimed in claim 4, which is characterized in that the first read-write selecting unit includes and the N
A RAM N number of internal logic controls correspondingly；
The first read-write selecting unit is used to first data N number of first storage region or N is selectively written
It a second storage region and is selectively read from N number of first storage region or N number of second storage region
Second data, including：
By writing logic N number of first memory block is selectively written in first data by N number of internal logic control
Domain or N number of second storage region and by reading logic selectively from N number of first storage region or N number of described
Second storage region reads second data.
6. receiver board as claimed in claim 4, which is characterized in that the second read-write selecting unit includes EMIF buses
Controller；The baseband processing module further includes RAM selection logics；
The second read-write selecting unit is used to second data N number of first storage region or N is selectively written
It a second storage region and is selectively read from N number of first storage region or N number of second storage region
First data, including：
The EMIF bus control units select logic that second data are selectively written N number of described the by the RAM
One storage region or N number of second storage region and selectively from N number of first storage region or N number of described
Two storage regions read first data.
7. receiver board as described in claim 1, which is characterized in that first data add up including each satellite IQ channels
Amount, chip count value, code week count value, carrier cycle count value；Second data include shift register taps word, displacement is posted
Storage initial status word, shift register cut-off state, carrier frequency control word, carrier phase control word, code frequency control word,
Code phase control word.
8. receiver board as described in claim 1, which is characterized in that the baseband processing module is field-programmable gate array
Row module FPGA；The positioning calculation module is digital signal processor DSP.
9. receiver board as described in claim 1, which is characterized in that the positioning calculation module includes enhanced directly interior
Access EDMA controllers；
The EDMA controllers for control the EMIF buses read from N number of dual port RAM first data and
Control the EMIF buses that second data are written in N number of dual port RAM.
A kind of 10. receiver, which is characterized in that the receiver card including antenna and as described in any in claim 1 to 9
Card；
The satellite navigation signals for receiving satellite navigation signals, and are sent to the receiver board by the antenna.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510520389.7A CN105182377B (en) | 2015-08-21 | 2015-08-21 | A kind of receiver board and receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510520389.7A CN105182377B (en) | 2015-08-21 | 2015-08-21 | A kind of receiver board and receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105182377A CN105182377A (en) | 2015-12-23 |
| CN105182377B true CN105182377B (en) | 2018-06-19 |
Family
ID=54904573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510520389.7A Active CN105182377B (en) | 2015-08-21 | 2015-08-21 | A kind of receiver board and receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105182377B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108226967B (en) * | 2016-12-15 | 2021-08-20 | 展讯通信（上海）有限公司 | GNSS signal tracking method and device |
| CN111224877A (en) * | 2019-12-10 | 2020-06-02 | 中国航空工业集团公司西安航空计算技术研究所 | VL query method and device of AFDX switch |
| CN111398996A (en) * | 2020-03-17 | 2020-07-10 | 广州南方卫星导航仪器有限公司 | Surveying and mapping satellite navigation receiver |
| CN111737191B (en) * | 2020-07-20 | 2021-01-15 | 长沙海格北斗信息技术有限公司 | Shared cache method, baseband processing unit and chip thereof |
| CN116232826A (en) * | 2023-03-13 | 2023-06-06 | 南京理工大学 | Very high frequency signal receiver |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101105401A (en) * | 2007-08-06 | 2008-01-16 | 北京航空航天大学 | SDINS/GPS combined guidance system time synchronism and synchronous data extraction method |
| CN101261129A (en) * | 2008-02-22 | 2008-09-10 | 北京航空航天大学 | Integrated navigation computer based on DSP and FPGA |
| CN104597458A (en) * | 2015-01-22 | 2015-05-06 | 上海海积信息科技股份有限公司 | Receiver board card and navigation receiver |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030191876A1 (en) * | 2000-02-03 | 2003-10-09 | Fallon James J. | Data storewidth accelerator |
| CN102760106A (en) * | 2011-04-28 | 2012-10-31 | 北京京师励耘教育科技有限公司 | PCI (peripheral component interconnect) academic data mining chip and operation method thereof |
| CN102832090B (en) * | 2012-08-29 | 2015-04-22 | 安徽华东光电技术研究所 | Heater assembly for space traveling wave tube and preparation method thereof |
-
2015
- 2015-08-21 CN CN201510520389.7A patent/CN105182377B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101105401A (en) * | 2007-08-06 | 2008-01-16 | 北京航空航天大学 | SDINS/GPS combined guidance system time synchronism and synchronous data extraction method |
| CN101261129A (en) * | 2008-02-22 | 2008-09-10 | 北京航空航天大学 | Integrated navigation computer based on DSP and FPGA |
| CN104597458A (en) * | 2015-01-22 | 2015-05-06 | 上海海积信息科技股份有限公司 | Receiver board card and navigation receiver |
Non-Patent Citations (2)
| Title |
|---|
| DSP EMIF与FPGA双口RAM高速通信实现;杨龙等;《现代电子技术》;20140701;第37卷(第13期);第10－12页，图2－3 * |
| 利用EDMA和DSP/BIOS实现高速数据搬移与处理;于凤芹等;《仪表技术与传感器》;20080229(第2期);第65－67页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105182377A (en) | 2015-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105182377B (en) | A kind of receiver board and receiver | |
| US8705313B2 (en) | DDR PSRAM and data writing and reading methods thereof | |
| CN105612580B (en) | Use the mass-storage system of standard controller component | |
| CN102760111B (en) | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof | |
| CN110097906A (en) | Adjust the memory device of duty ratio and the storage system with memory device | |
| CN113553277A (en) | High-throughput and low-delay PHY (physical layer) interface circuit device of DDR5SDRAM (synchronous dynamic random access memory) | |
| CN101876699A (en) | Control system and control method of satellite-borne microwave radiometer | |
| CN104778025B (en) | The circuit structure of pushup storage based on random access storage device | |
| CN102931994B (en) | Be applied to high speed signal sampling and synchronous framework and the method for signal processing chip | |
| CN102648456A (en) | Memory device and method | |
| JP2009527829A (en) | Common analog interface for multiple processor cores | |
| CN205229465U (en) | Baseband chip and multimode GNSS receiver of multimode GNSS receiver | |
| US8988962B2 (en) | Refresh circuit of a semiconductor memory device and refresh control method of the semiconductor memory device | |
| CN101887130B (en) | Programmable navigational satellite spread spectrum sequence generator | |
| CN110569596A (en) | Hybrid clock tree structure for system on chip | |
| CN102540146B (en) | Configurable digital correlator for complete polarization microwave radiometer system | |
| CN102436840A (en) | Digital radio frequency memory board | |
| CN101825997A (en) | Asynchronous first-in first-out storage | |
| KR101845368B1 (en) | Mapping memory controller connectors to memory connectors | |
| CN206431615U (en) | A kind of fifo controller of multichannel read-write multicapacity selection | |
| CN105608028A (en) | EMIF (External Memory Interface) and dual-port RAM (Random Access Memory)-based method for realizing high-speed communication of DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) | |
| CN102262595A (en) | Extended addressing method for microprocessor | |
| CN109376049B (en) | Performance test method of FPGA embedded block memory | |
| CN201589858U (en) | Microwave spaceborne radiometer data processing and scanning control system adopting FPGA technology | |
| CN103135097B (en) | 16-channel double-mode radar digital down conversion method based on field programmable gate array (FPGA) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A receiver board and receiver Effective date of registration: 20220826 Granted publication date: 20180619 Pledgee: China Merchants Bank Co.,Ltd. Shanghai Branch Pledgor: SHANGHAI HIGH GAIN INFORMATION TECHNOLOGY Co.,Ltd. Registration number: Y2022310000205 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20230818 Granted publication date: 20180619 Pledgee: China Merchants Bank Co.,Ltd. Shanghai Branch Pledgor: SHANGHAI HIGH GAIN INFORMATION TECHNOLOGY Co.,Ltd. Registration number: Y2022310000205 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A receiver board and receiver Effective date of registration: 20230829 Granted publication date: 20180619 Pledgee: China Merchants Bank Co.,Ltd. Shanghai Branch Pledgor: SHANGHAI HIGH GAIN INFORMATION TECHNOLOGY Co.,Ltd. Registration number: Y2023310000499 |