CN105158673B - A kind of generation method and device of ATE boards file - Google Patents
A kind of generation method and device of ATE boards file Download PDFInfo
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- CN105158673B CN105158673B CN201510536130.1A CN201510536130A CN105158673B CN 105158673 B CN105158673 B CN 105158673B CN 201510536130 A CN201510536130 A CN 201510536130A CN 105158673 B CN105158673 B CN 105158673B
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Abstract
Embodiments of the invention provide a kind of generation method and device of ATE boards file, are related to semiconductor test field, it is possible to increase the conversion efficiency of ATE board document converting processes.This method includes：Obtain in chip I P to be tested first test template file corresponding to the test sequence information of interface to be tested and chip I P to be tested, the test sequence information of interface to be tested includes interface to be tested the test value under different test sequences；According to the interface message of the interface to be tested included in the first test template file, the test sequence information of interface to be tested is added in the first test template file, obtains the second test template file；The test value of interface to be tested under different test sequences is read from the second test template file, ATE board files are generated according to the test value of interface to be tested under different test sequences.The ATE that the present invention is applied to chip is tested.
Description
Technical field
The present invention relates to semiconductor test field, more particularly to a kind of generation method and device of ATE boards file.
Background technology
At present, in semiconductor test field, ATE (Automatic Test Equipment, automatic testization are being carried out
Equipment) test when, to obtain the ATE board files required for ATE boards, prior art generally by following two modes come
Obtain：
First, during test in the IP test pattern supporting papers provided by board tester according to chip I P director
Sequence writes ATE board files manually, and still, this mode need to rely between chip I P director and board Test Engineer
Communication, and the omission of information occurs in communication process unavoidably, so as to cause the amendment ATE boards text of Test Engineer repeatedly
Part.
Second, by ATE board file switching softwares by EDA (Electronic Design Automation, electronics
Design automation) file be converted into board test ATE board files, although The method avoids chip I P director and machine
Communication between platform Test Engineer, still, because this mode needs IP director's offer EDA simulation document, therefore, when
, it is necessary to which chip I P director regenerates EDA simulation documents by EDA emulation when needing to be modified ATE board files, from
And cause whole transfer process efficiency low, take long.
The content of the invention
Embodiments of the invention provide a kind of generation method and device of ATE boards file, are turned with improving ATE boards file
Change the conversion efficiency of process.
To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：
First aspect, there is provided a kind of generation method of ATE boards file, including：
Obtain in chip I P to be tested corresponding to the test sequence information of interface to be tested and the chip I P to be tested
First test template file, the test sequence information of the interface to be tested include the interface to be tested in different test sequences
Under test value, the interface message of interface to be tested in the chip I P to be tested is included in the first test template file,
The first test template file is user's editable form document；
According to the interface message of the interface to be tested included in the first test template file, by the survey of the interface to be tested
Try timing information to be added in the first test template file, obtain the second test template file；
The test value of the interface to be tested under different test sequences is read from the second test template file, according to
The test value generation ATE board files of the interface to be tested under the different test sequences.
Second aspect, there is provided a kind of generating means of automatic testization device A TE board files, including：
Acquisition module, for obtaining in chip I P to be tested the test sequence information of interface to be tested and described to be tested
First test template file corresponding to chip I P, the test sequence information of the interface to be tested exist including the interface to be tested
Test value under different test sequences, interface to be tested in the chip I P to be tested is included in the first test template file
Interface message, the first test template file is user's editable form document；
Processing module, for the interface to be tested included in the first test template file for being obtained according to the acquisition module
Interface message, the test sequence information of the interface to be tested that the acquisition module is obtained is added to the described first test
In template file, the second test template file is obtained；
Generation module, during for reading different tests in the second test template file for being obtained from the processing module
The test value of the interface to be tested under sequence, generated according to the test value of the interface to be tested under the different test sequences
ATE board files.
The generation method and device for the ATE board files that embodiments of the invention provide, obtain and are treated in chip I P to be tested
First test template file corresponding to the test sequence information of test interface and chip I P to be tested, the survey of the interface to be tested
Examination timing information includes interface to be tested the test value under different test sequences, and the first test template file is according to be tested
The interface message generation of interface to be tested in chip I P, the first test template file is user's editable form document, according to
The interface message of the interface to be tested included in first test template file, the test sequence information of interface to be tested is added to
In the first test template file, the second test template file is obtained, then, is read from the second test template file different
The test value of interface to be tested under test sequence, ATE boards are generated according to the test value of interface to be tested under different test sequences
File.So when needing to be modified ATE board files, technical staff directly can be treated based on chip I P to be tested
In first test template file of the interface message generation of test interface, the test sequence of the chip I P to be tested after addition change
To obtain new ATE board files, after needing according to comprising change in change ATE board files every time compared to prior art
The chip I P to be tested IP test pattern supporting papers of test sequence re-start EDA emulation and imitated come EDA corresponding to obtaining
True file, being then converted into EDA simulation documents using switching software needs ATE board files, and scheme provided by the invention is more
To be quick and conveniently, and the conversion efficiency of overall ATE board document converting processes is higher.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be in embodiment or description of the prior art
The required accompanying drawing used is briefly described, it should be apparent that, drawings in the following description are only some realities of the present invention
Example is applied, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is a kind of schematic flow sheet of the generation method of ATE boards file provided in an embodiment of the present invention；
Fig. 2 is a kind of structural representation of the generating means of ATE boards file provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
Embodiments of the invention provide a kind of generation method of ATE boards file, as shown in figure 1, this method specifically includes
Following steps：
101st, the generating means of ATE boards file obtain the test sequence information of interface to be tested in chip I P to be tested with
And the first test template file corresponding to chip I P to be tested.
Exemplary, above-mentioned interface to be tested includes chip I P to be tested register interface, chip I P to be tested
Input interface, chip I P to be tested output interface in it is at least one.The test sequence packet of above-mentioned interface to be tested
Test value of the interface to be tested under different test sequences is included, for example, input value of the input interface under different test sequences, defeated
Outgoing interface corresponding output valve under same test sequence after input interface gives input value.In addition, the first above-mentioned test
Template file includes the interface message of interface to be tested in chip I P to be tested, the interface letter of the interface to be tested in the present embodiment
Breath includes the interface identifier of interface to be tested and the interface attributes information of interface to be tested, the interface attributes of the interface to be tested
Information is used to represent the affiliated interface type of interface to be tested.
Exemplary, when the generating means of ATE board files are entered to the interface to be tested of the chip I P to be tested for the first time
During row Self -adaptive ATE board files, before step 101, this method also includes following content：
The generating means of a1, ATE board file are according to chip I P to be tested testing requirement, from chip I P to be tested survey
In die trial formula supporting paper, the chip I P to be tested of extraction test parameter information.
The generating means of a2, ATE board file are according to the interface message of interface to be tested in chip I P to be tested, generation the
One test template file.
Wherein, it is the survey that the chip I P to be tested writes that above-mentioned test pattern supporting paper, which is specifically as follows tester,
Document is tried, as shown in table 1, it is necessary to illustrate, the interface type and number included in table 1 are only the test document here
A kind of example, in actual test document and it is not so limited.Above-mentioned chip I P to be tested testing requirement needs including user
The interface identifier of the interface to be tested of test, that is, need the interface identifier of which interface tested.In addition, above-mentioned core to be tested
Piece IP test parameter information can also be that technical staff directly inputs.It is exemplary, above-mentioned chip I P to be tested survey
Trying parameter information includes chip I P to be tested interface message, test pattern control information and the test clock of interface to be tested
Information is inputted with resetting.
The first test template file and the second test template file in the present embodiment can be Microsoft Excel file,
User's editable form document such as database table lattice file.
Table 1
If for example, when the test parameter information of the chip I P to be tested is as shown in table 1, the generation of the ATE board files
The acquisition flow that device generates the first test template file is as follows：
" Test Mode Control " regions, the test point title of control test pattern is read in device positioning table 1
And assignment；Then, positioning " IP Input Items " regions, is read pad titles corresponding to register configuration interface, and tested defeated
Enter pad title；Then, " IP Output Items " regions, read test exports pad title, finally, according to this for positioning
The template style of first test template file, generate the first test template file.
Corresponding first test template file content is as follows：
Table 2
102nd, the generating means of ATE boards file are according to the interface of the interface to be tested included in the first test template file
Information, the test sequence information of interface to be tested is added in the first test template file, obtains the second test template file.
It is used to represent each interface to be tested under different test sequences in the second test template file in the present embodiment
The main part of test value.Exemplary, if the generating means of ATE board files add chip I P to be tested test sequence
Into the first test template file formed based on table 1, then the second test template file content is as shown in table 3 below：
Table 3
TS1 and TS2 in above-mentioned table 3 are used to indicate some in current test can not be embodied in test and excitation description section
Content, for example, the input of analog signal, 20KHz sine wave is inputted in TS2.
Repeat information in above-mentioned table 3 is used to indicate that the input pad states of current line to keep constant, and hold period is
The numeral of repeat requirements.If for example, the row scratchpad register information is IDLE, Comment information for " repeat 20 ", then
Represent that the information of the row wants duplicate printing 20 times, that is, keep constant in 20 cycles.In the test of reality, in many situations
Under, input can keep constant a period of time, and to ensure to meet IP test request, therefore, repeat information can reduce input pad
The information largely repeated, reduce workload.
Scratchpad register configuration information is used to control that uses in test pattern to cross what scratchpad register configured in above-mentioned table 3
Information.
Pad input values are inputted in above-mentioned table 3：The corresponding each test in the part inputs input values of the pad in each cycle,
Wherein：1 represents high level, and 0 represents low level；
Pad detected values are exported in above-mentioned table 3 to be used to describe the scratchpad register and input pad State Drive giving
Under, expected results corresponding to pad are exported, wherein：L represents output low level, and H represents output high level, and X represents output don't
care.Board can contrast according to the partial information and the actual pad of the chip output pad states for sampling to obtain, and judge that test is
It is no to pass through.
It is exemplary, if the first test template file is user's editable EXCEL file, above-mentioned interface to be tested
Test sequence information be that user is directly directly filled up in above-mentioned EXCEL according to chip I P test specifications, and the ATE boards
The generating means of file are by the interface to be tested in the test sequence information of the interface to be tested and the first test template file
It is associated, so as to obtain the second test template file.
Exemplary, the test sequence information of above-mentioned interface to be tested can also be the generating means of ATE board files
Obtained from the chip I P to be tested editted in advance sequential file, wherein, above-mentioned chip I P to be tested when preface
Part includes the test sequence information of interface to be tested in chip I P to be tested.
103rd, the generating means of ATE boards file are read to be tested under different test sequences from the second test template file
The test value of interface, ATE board files are generated according to the test value of interface to be tested under different test sequences.
Exemplary, based on the second test template file content shown in table 3, obtained ATE board file contents are as follows
It is shown：
Exemplary, the generating means of ATE board files are reading interface pair to be tested from the second test template file
After the test sequence answered, the general ASCII Pattern (pattern in ATE boards file one) of meeting produce script and read in the information, from
And generate ASCII Format files.
The generation method for the ATE board files that embodiments of the invention provide, obtains to be measured in chip I P to be tested try
Mouthful test sequence information and chip I P to be tested corresponding to the first test template file, the test sequence of the interface to be tested
Information includes interface to be tested the test value under different test sequences, and the first test template file is according to chip I P to be tested
In interface to be tested interface message generation, the first test template file be user's editable form document, according to first survey
The interface message of interface to be tested included in examination template file, by the test sequence information of interface to be tested added to described the
In one test template file, the second test template file is obtained, then, when reading different tests from the second test template file
The test value of interface to be tested under sequence, ATE board files are generated according to the test value of interface to be tested under different test sequences.This
When needing to be modified ATE board files, technical staff's sample directly can be tried based on the to be measured of chip I P to be tested
Mouthful interface message generation the first test template file in, the test sequence of the chip I P to be tested after addition change obtains
New ATE board files, needed compared to prior art in change ATE board files every time according to be measured after comprising change
The IP test pattern supporting papers of examination chip I P test sequence re-start EDA emulation to obtain corresponding EDA simulation documents,
Then being converted into EDA simulation documents using switching software needs ATE board files, scheme provided by the invention it is more quick and
It is convenient, and the conversion efficiency of overall ATE board document converting processes is higher.
Embodiments of the invention provide a kind of generating means of ATE boards file, as shown in Fig. 2 the device 2 includes：Obtain
Modulus block 21, processing module 22 and generation module 23, wherein：
Acquisition module 21, for obtaining the test sequence information of interface to be tested and core to be tested in chip I P to be tested
First test template file corresponding to piece IP.
Wherein, the test sequence information of above-mentioned interface to be tested includes interface to be tested the survey under different test sequences
Examination value, the interface message of interface to be tested in chip I P to be tested, the first test template text are included in the first test template file
Part is user's editable form document.Test template file includes Microsoft Excel file, database table lattice file.
Processing module 22, for the interface to be tested included in the first test template file for being obtained according to acquisition module 21
Interface message, the test sequence information for the interface to be tested that acquisition module 21 is obtained is added to the first test template file
In, obtain the second test template file.
Generation module 23, for being read in the second test template file for being obtained from processing module 22 under different test sequences
The test value of interface to be tested, ATE board files are generated according to the test value of interface to be tested under different test sequences.
Optionally, above-mentioned acquisition module 21, it is additionally operable to obtain chip I P to be tested sequential file, chip I P's to be tested
Sequential file includes the test sequence information of interface to be tested in chip I P to be tested.
Optionally, as shown in Fig. 2 the device 2 also includes：Extraction module 24, wherein：
Extraction module 24, for the testing requirement according to chip to be tested, from chip I P to be tested test pattern explanation
In file, chip I P to be tested test parameter information is extracted, test parameter information includes the interface message of interface to be tested, treated
The testing requirement of test chip includes the interface identifier for the interface to be tested that user's needs are tested.
Generation module 23, it is additionally operable to the chip I P to be tested test parameter information extracted according to extraction module 24, generation
First test template file.
Optionally, the register interface of interface to be tested including chip I P to be tested, chip I P to be tested input interface,
It is at least one in chip I P to be tested output interface；The interface message of interface to be tested includes the interface mark of interface to be tested
Know and the interface attributes information of interface to be tested, the interface attributes information of interface to be tested are used to represent belonging to interface to be tested
Interface type.
The generating means for the ATE board files that embodiments of the invention provide, obtain to be measured in chip I P to be tested try
Mouthful test sequence information and chip I P to be tested corresponding to the first test template file, the test sequence of the interface to be tested
Information includes interface to be tested the test value under different test sequences, and the first test template file is according to chip I P to be tested
In interface to be tested interface message generation, the first test template file be user's editable form document, according to first survey
The interface message of interface to be tested included in examination template file, by the test sequence information of interface to be tested added to described the
In one test template file, the second test template file is obtained, then, when reading different tests from the second test template file
The test value of interface to be tested under sequence, ATE board files are generated according to the test value of interface to be tested under different test sequences.This
When needing to be modified ATE board files, technical staff's sample directly can be tried based on the to be measured of chip I P to be tested
Mouthful interface message generation the first test template file in, the test sequence of the chip I P to be tested after addition change obtains
New ATE board files, needed compared to prior art in change ATE board files every time according to be measured after comprising change
The IP test pattern supporting papers of examination chip I P test sequence re-start EDA emulation to obtain corresponding EDA simulation documents,
Then being converted into EDA simulation documents using switching software needs ATE board files, scheme provided by the invention it is more quick and
It is convenient, and the conversion efficiency of overall ATE board document converting processes is higher.
In several embodiments provided herein, it should be understood that disclosed terminal and method, it can be passed through
Its mode is realized.For example, device embodiment described above is only schematical, for example, the division of the unit, only
Only a kind of division of logic function, there can be other dividing mode when actually realizing, such as multiple units or component can be tied
Another system is closed or is desirably integrated into, or some features can be ignored, or do not perform.It is another, it is shown or discussed
Mutual coupling or direct-coupling or communication connection can be the INDIRECT COUPLINGs or logical by some interfaces, device or unit
Letter connection, can be electrical, mechanical or other forms.
The unit illustrated as separating component can be or may not be physically separate, show as unit
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple
On NE.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, can also
That the independent physics of unit includes, can also two or more units it is integrated in a unit.Above-mentioned integrated list
Member can both be realized in the form of hardware, can also be realized in the form of hardware adds SFU software functional unit.
The above-mentioned integrated unit realized in the form of SFU software functional unit, can be stored in one and computer-readable deposit
In storage media.Above-mentioned SFU software functional unit is stored in a storage medium, including some instructions are causing a computer
Equipment (can be personal computer, server, or network equipment etc.) performs the portion of each embodiment methods described of the present invention
Step by step.And foregoing storage medium includes：USB flash disk, mobile hard disk, read-only storage (Read-Only Memory, abbreviation
ROM), random access memory (Random Access Memory, abbreviation RAM), magnetic disc or CD etc. are various to store
The medium of program code.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
- A kind of 1. generation method of automatic testization device A TE board files, it is characterised in that including：Obtain in chip I P to be tested first corresponding to the test sequence information of interface to be tested and the chip I P to be tested Test template file, the test sequence information of the interface to be tested include the interface to be tested under different test sequences Test value, the interface message of interface to be tested in the chip I P to be tested is included in the first test template file, it is described First test template file is user's editable form document；According to the interface message of the interface to be tested included in the first test template file, during by the test of the interface to be tested Sequence information is added in the first test template file, obtains the second test template file；The test value of the interface to be tested under different test sequences is read from the second test template file, according to described The test value generation ATE board files of the interface to be tested under different test sequences.
- 2. according to the method for claim 1, it is characterised in that the test template file include Microsoft Excel file or Database table lattice file.
- 3. according to the method for claim 1, it is characterised in that described to be measured according to being included in the first test template file Try the interface message of mouth, the test sequence information of the interface to be tested be added in the first test template file, Before obtaining the second test template file, methods described also includes：The sequential file of the chip I P to be tested is obtained, the sequential file of the chip I P to be tested includes the core to be tested The test sequence information of interface to be tested in piece IP.
- 4. according to the method for claim 1, it is characterised in that the survey for obtaining interface to be tested in chip I P to be tested Before trying the first test template file corresponding to timing information and the chip I P to be tested, methods described also includes：According to the testing requirement of the chip I P to be tested, from the test pattern supporting paper of the chip I P to be tested, carry The test parameter information of the chip I P to be tested is taken, the interface that the test parameter information includes the interface to be tested is believed Breath, the testing requirement of the chip I P to be tested include the interface identifier for the interface to be tested that user's needs are tested；According to the test parameter information of the chip I P to be tested, the first test template file is generated.
- 5. according to the method described in any one of Claims 1-4, it is characterised in that the interface to be tested includes described to be measured In the register interface, the input interface of the chip I P to be tested, the output interface of the chip I P to be tested that try chip I P It is at least one；The interface identifier of the interface message of the interface to be tested including the interface to be tested and described to be tested The interface attributes information of interface, the interface attributes information of the interface to be tested are used to represent the affiliated interface of interface to be tested Type.
- A kind of 6. generating means of automatic testization device A TE board files, it is characterised in that including：Acquisition module, for obtaining the test sequence information of interface to be tested and the chip to be tested in chip I P to be tested First test template file corresponding to IP, the test sequence information of the interface to be tested include the interface to be tested in difference Test value under test sequence, connecing for interface to be tested in the chip I P to be tested is included in the first test template file Message ceases, and the first test template file is user's editable form document；Processing module, for connecing for the interface to be tested that is included in the first test template file for being obtained according to the acquisition module Message ceases, and the test sequence information for the interface to be tested that the acquisition module is obtained is added to first test template In file, the second test template file is obtained；Generation module, for being read in the second test template file for being obtained from the processing module under different test sequences The test value of the interface to be tested, ATE machines are generated according to the test value of the interface to be tested under the different test sequences Platform file.
- 7. device according to claim 6, it is characterised in that the test template file include Microsoft Excel file or Database table lattice file.
- 8. device according to claim 6, it is characterised in that：The acquisition module, it is additionally operable to obtain the sequential file of the chip I P to be tested, the sequential of the chip I P to be tested File includes the test sequence information of interface to be tested in the chip I P to be tested.
- 9. device according to claim 6, it is characterised in that described device also includes：Extraction module, for the testing requirement according to the chip to be tested, from the perspective of from the test pattern of the chip I P to be tested In prescribed paper, the test parameter information of the chip I P to be tested is extracted, the test parameter information includes described to be measured try The interface message of mouth, the testing requirement of the chip to be tested include the interface identifier for the interface to be tested that user's needs are tested；The generation module, the test parameter information of the chip I P to be tested extracted according to the extraction module is additionally operable to, Generate the first test template file.
- 10. according to the device described in any one of claim 6 to 9, it is characterised in that the interface to be tested includes described to be measured In the register interface, the input interface of the chip I P to be tested, the output interface of the chip I P to be tested that try chip I P It is at least one；The interface identifier of the interface message of the interface to be tested including the interface to be tested and described to be tested The interface attributes information of interface, the interface attributes information of the interface to be tested are used to represent the affiliated interface of interface to be tested Type.
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| CN106156422A (en) * | 2016-07-01 | 2016-11-23 | 合肥海本蓝科技有限公司 | A kind of method and apparatus encapsulating standard in combination simulation modeling interface |
| CN106844126B (en) * | 2016-12-23 | 2019-03-22 | 中国空间技术研究院 | A kind of the spacecraft hard IP kernel function of number and performance evaluation methodology |
| CN111105839B (en) * | 2018-10-26 | 2022-04-15 | 长鑫存储技术有限公司 | Chip testing method and device, electronic equipment and computer readable medium |
| CN112444731B (en) * | 2020-10-30 | 2023-04-11 | 海光信息技术股份有限公司 | Chip testing method and device, processor chip and server |
| CN112710947A (en) * | 2020-12-22 | 2021-04-27 | 上海华岭集成电路技术股份有限公司 | ATE-based functional test method and tool |
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| US6016515A (en) * | 1997-04-04 | 2000-01-18 | Microsoft Corporation | Method, computer program product, and data structure for validating creation of and routing messages to file object |
| US8423959B1 (en) * | 2006-12-11 | 2013-04-16 | Synopsys, Inc. | Techniques for coordinating and controlling debuggers in a simulation environment |
| CN102929627B (en) * | 2012-10-29 | 2015-08-12 | 无锡江南计算技术研究所 | Based on test procedure automatic generation method and the ATE method of testing of ATE |
| CN103440133A (en) * | 2013-08-30 | 2013-12-11 | 上海高清数字科技产业有限公司 | Development method and system of chip testing software |
| CN104298501A (en) * | 2014-08-26 | 2015-01-21 | 中国直升机设计研究所 | Drive design method of automatic test equipment instrument |
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