CN105094976A - Interrupt control method and interrupt controller - Google Patents
Interrupt control method and interrupt controller Download PDFInfo
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Abstract
The invention provides an interrupt control method and an interrupt controller. Interrupt with the highest priority in an interrupt request is arbitrated out through a priority arbitration module, the priority of the interrupt is compared with the priority of current interrupt, if the priority output by the priority arbitration module is higher than the priority of the current interrupt, the interrupt request is output to a CPU, an interrupt vector generating module stores an interrupt vector to an interrupt cognition register in a software mode and outputs the interrupt vector and interrupt enable to the CPU in a hardware mode, and a nested interrupt priority saving module stores nested priority. The interrupt control method and the interrupt controller, provided by the invention, are compatible with the software mode and the hardware mode, an interrupt nesting mechanism is simple, relatively low time delay is realized, and the interrupt controller only requires three periods from receiving the interrupt to sending the interrupt request to a processor.
Description
Technical field
The invention belongs to the electronic circuit field of interruptable controller, especially relate to a kind of programmable interrupt controller comprising software pattern, hardware mode.
Background technology
Comprise numerous hardware module in SOC design, a lot of hardware module all can export one or several interrupt request, and only has one or two interrupt request singal to input in processor, so the process interrupting having to pass through interruptable controller just can enter processor.
Interruption is divided into hardware mode and software pattern, and software pattern needs CPU access interrupt controller to obtain interrupt number, and then inquiry interrupt vector table, obtains break in service function address; Hardware mode, sends interrupt vector while interruptable controller sends interrupt request, and CPU according to interrupt vector, can perform corresponding break in service function.
Interruptable controller of the present invention, compatible software pattern and hardware mode, and also interrupt nesting mechanism is simple, has and comparatively has low time delay, and interruptable controller accepts to interrupt sending interrupt request to interruptable controller to processor only needs 3 cycles.
Summary of the invention
In view of this, the present invention is intended to propose a kind of interrupt control method and interruptable controller, utilizes priority comparison module when realizing software pattern and hardware mode compatibility, reduces time delay, and what realization was interrupted can Response to selection.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of interrupt control method, comprises the following steps:
The selected mode of operation of control register and the Current interrupt priority of Current interrupt priority register in (a) setting interruptable controller;
B configurable interruption that () exterior interrupt and/or interruptable controller inside produce enters priority arbitration module after configuration preference level, priority arbitration module arbitrate goes out optimum interruption, enter step (c), if priority arbitration module does not receive any interrupt request, then enter step (d);
C priority input priority comparison module that optimum interrupts by () priority arbitration module, the interrupt number input interrupt vector generation module interrupted by optimum, enters step (e);
D interrupt number that () priority arbitration module exports to interrupt vector generation module is 0, enters step (e);
E Current interrupt priority in priority in priority comparison module and Current interrupt priority register compares by (), if the priority in priority comparison module is not more than the Current interrupt priority in Current interrupt register, then repeat step (b) to step (e), if the priority in priority comparison module is greater than the Current interrupt priority in Current interrupt priority register, then priority comparison module exports interrupt request to CPU;
If f software pattern selected by () this control register, then enter step (g), if hardware mode selected by this control register, then enter step (h);
G (), while priority comparison module exports interrupt request to CPU, the interrupt number that priority arbitration module exports is saved in and interrupts in cognitive register by interrupt vector generation module,
Then CPU is read by register read-write interface and interrupts cognitive register,
This read operation makes the Current interrupt priority in Current interrupt priority register be saved to nested interrupt priority and preserves module, and priority arbitration module is kept in Current interrupt priority register to the priority that priority comparison module exports,
CPU obtains the side-play amount of interrupt function address corresponding to interrupt vector simultaneously, performs the break in service function of response,
At the end of CPU interrupt response, CPU writes End of Interrupt register, and Current interrupt priority reverts in Current interrupt priority register by nested interrupt priority preservation module simultaneously;
H (), while priority comparison module exports interrupt request to CPU, interrupt vector generation module exports interrupt vector and interrupt vector enable signal to CPU,
When receiving the cognitive signal of hardware interrupts that CPU provides and being effective, Current interrupt priority in Current interrupt priority register is saved to nested interrupt priority and preserves module, the priority that priority arbitration module exports to priority comparison module is kept in Current interrupt priority register
At the end of CPU interrupt response, CPU writes End of Interrupt register,
Current interrupt priority reverts in Current interrupt priority register by nested interrupt priority preservation module simultaneously.
Further, the configurable interruption in described step (b) is produced by the software design patterns in interruptable controller/removing register, and the priority configuration scope in described priority configuration register is 0 to 15, totally 16.
Further, the priority arbitration module arbitrate in described step (b) goes out optimum method of interrupting and comprises the following steps:
(b1) priority of more all interruptions, selects the interruption that priority is the highest;
(b2) count the number of the highest interruption of priority, if number is 1, then the interruption that this priority is the highest is optimum interruption, if number is greater than 1, then selects the interruption that wherein interrupt number is minimum and is optimum interruption.
Further, before CPU interrupt response in described step (g) or step (h) terminates, if there is the interruption of higher priority to enter priority arbitration module, then according to step (b) to (h) flow performing, if the execute phase of last interruption enter interrupt function after CPU to open external interrupt enable, to ensure interrupt nesting, then interruptable controller has twice interrupt request to occur, and has two priority preservations in nested interrupt priority preservation module.
Further, it be " last in, first out " structure that the nested priority in described step (g) or step (h) preserves module, and the degree of depth of this nested priority preservation module is 15.
Further, the interrupt vector in described step (h) is word alignment, and the bit wide of interrupt vector depends on the output external interrupt quantity of interruptable controller and the quantity of the configurable interruption of software.
Further, the calculation expression of the figure place H of the interrupt vector in described step (h) is H=log2 (M1+M2), wherein M1+M2=2
n+, M1 is external interrupt number, and M2 is configurable interrupt number, and N+ is positive integer;
Or H=[log2 (M1+M2)]+1, wherein M1+M2 ≠ 2
n+, M1 is external interrupt number, and M2 is configurable interrupt number, and N+ is positive integer, and [] expression rounds downwards.
A kind of interruptable controller, comprises communication interface, priority arbitration module, interrupt vector generation module, priority comparison module, nested interrupt priority preservation module and register module;
The external interrupt source of described communication interface, interrupt source inputs look-at-me through communication interface;
Described priority arbitration module, for selecting optimum interruption;
Described interrupt vector generation module, the enable and interrupt vector for generation of interrupt vector;
Described priority comparison module, for comparing the priority and the size of Current interrupt priority that priority arbitration module exports;
Described nested interrupt priority preserves module, owing to preserving by the priority of nested interrupt;
The look-at-me of described communication interface input and/or the interior configurable look-at-me input priority arbitration modules after register module configuration preference level produced of register module;
Priority arbitration module is selected in optimum and is had no progeny, and exports the optimum interrupt number interrupted to interrupt vector generation module, exports optimum priority of interrupting to priority comparison module;
Priority comparison module and register module communicate to connect, and the priority that the optimum in this priority comparison module interrupts and the interior Current interrupt priority set of register module compare, and comparative result controls the transmission of interrupt request in priority comparison module;
Register module and nested interrupt priority are preserved module communication and are connected;
Interrupt vector generation module coordinates register module and CPU to communicate to connect.
Further, described register module comprises part and arranges/remove register, priority configuration register, control register, Current interrupt priority register, interrupts cognitive register, End of Interrupt register and register read-write interface;
Described software design patterns/removing register, for arranging, removing the configurable interruption of software;
Described priority configuration register, for configuring the priority that each interrupts;
Described control register, for configure interrupt controller mode of operation: software pattern or hardware mode;
Described Current interrupt priority register, for preserving the current priority performing interruption, after reset, the Current interrupt priority in Current interrupt priority register is maximal value;
The cognitive register of described interruption, for preserving interrupt vector;
Described End of Interrupt register, is write by CPU, for representing that interrupt response terminates to interruptable controller;
Register read-write interface is for accessing all registers;
Further, the look-at-me of described communication interface input and/or configurable look-at-me input priority arbitration modules after priority configuration register configuration preference level of the interior generation of software design patterns/removing register.
Further, described priority comparison module and Current interrupt priority register communicate to connect, the priority that Current interrupt priority relatively in Current interrupt priority register and the optimum in priority comparison module interrupt, and the priority in priority comparison module is stored into Current interrupt priority register.
Further, described Current interrupt priority register and described nested interrupt priority preserve the communication connection of module, Current interrupt priority in Current interrupt priority register is saved in nested interrupt priority and preserves module, and realize preserving the reset of the Current interrupt priority in module to Current interrupt priority register by nested interrupt priority.
Further, described control register is connected with interrupt vector generation module communication, the output side signal controlling interrupt vector generation module to.
Further, described interrupt vector generation module can be selected to communicate to connect with the cognitive register of interruption and CPU.
Further, the cognitive register of described interruption is preserved module by signal with described priority comparison module, Current interrupt priority register and nested priority and is connected, and End of Interrupt register is preserved module by signal with Current interrupt priority register and nested priority and is connected.
Further, described interrupt source is level triggers.
Relative to prior art, interrupt control method of the present invention and interruptable controller have following advantage:
(1) interrupt control method of the present invention and interruptable controller, compatible software pattern and hardware mode, and also interrupt nesting mechanism is simple, has and comparatively has low time delay.
Accompanying drawing explanation
The accompanying drawing forming a part of the present invention is used to provide a further understanding of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the interruptable controller theory diagram described in the embodiment of the present invention;
Fig. 2 is the cognitive buffer status figure of the interruption described in the embodiment of the present invention.
Description of reference numerals:
1-communication interface, 2-priority arbitration module, 3-interrupt vector generation module, 4-priority comparison module, 5-nested interrupt priority preserves module, 61-software design patterns/removing register, 62-priority configuration register, 63-control register, 64-Current interrupt priority register, 65-interrupts cognitive register, 66-End of Interrupt register, 67-register read-write interface.
Embodiment
It should be noted that, when not conflicting, the embodiment in the present invention and the feature in embodiment can combine mutually.
Below with reference to the accompanying drawings and describe the present invention in detail in conjunction with the embodiments.
As illustrated in fig. 1 and 2, the interrupt control method in the present invention, comprises the following steps:
The selected mode of operation of control register 63 and the Current interrupt priority of Current interrupt priority register 64 in (a) setting interruptable controller;
B configurable interruption that () exterior interrupt and/or interruptable controller inside produce enters priority arbitration module 2 after configuration preference level, priority arbitration module 2 arbitrates out optimum interruption, enter step (c), if priority arbitration module 2 does not receive any interrupt request, then enter step (d), wherein configurable interruption is produced by the software design patterns in interruptable controller/removing register 61, priority configuration scope in priority configuration register 62 is 0 to 15, totally 16, priority arbitration module 2 is in all interruptions initiating interrupt request, arbitrate out the interruption that priority is the highest, if it is identical to there is most interrupt priority level value, then choose the interruption that wherein interrupt number is minimum,
C priority input priority comparison module 4 that optimum interrupts by () priority arbitration module 2, the interrupt number input interrupt vector generation module 3 interrupted by optimum, enters step (e);
D interrupt number that () priority arbitration module 2 exports to interrupt vector generation module 3 is 0, enters step (e);
E Current interrupt priority in priority in priority comparison module 4 and Current interrupt priority register 64 compares by (), if the priority in priority comparison module 4 is not more than the Current interrupt priority in Current interrupt register 64, then repeat step (b) to step (e), if the priority in priority comparison module 4 is greater than the Current interrupt priority in Current interrupt priority register 64, then priority comparison module 4 exports interrupt request to CPU, this step medium priority comparison module 4 compares the value of arbitrating priority and Current interrupt priority register 64 medium priority drawn, in order to determine whether to export interrupt request to CPU, therefore the setting of Current interrupt priority can shield the interruption of certain priority in this place's Current interrupt priority register 64,
If f software pattern selected by () this control register 63, then enter step (g), if hardware mode selected by this control register 63, then enter step (h);
G (), while priority comparison module 4 exports interrupt request to CPU, the interrupt number that priority arbitration module 2 exports is saved in and interrupts in cognitive register 65 by interrupt vector generation module 3,
Then CPU is read by register read-write interface 67 and interrupts cognitive register 65,
This read operation makes the Current interrupt priority in Current interrupt priority register 64 be saved to nested interrupt priority and preserves module 5, and priority arbitration module 2 is kept in Current interrupt priority register 64 to the priority that priority comparison module 4 exports,
CPU obtains the side-play amount of interrupt function address corresponding to interrupt vector simultaneously, performs the break in service function of response,
At the end of CPU interrupt response, CPU writes End of Interrupt register 66, and Current interrupt priority reverts in Current interrupt priority register 64 by nested interrupt priority preservation module 5 simultaneously;
H (), while priority comparison module 4 exports interrupt request to CPU, interrupt vector generation module 3 exports interrupt vector and interrupt vector enable signal to CPU,
When receiving the cognitive signal of hardware interrupts that CPU provides and being effective, Current interrupt priority in Current interrupt priority register 64 is saved to nested interrupt priority and preserves module 5, the priority that priority arbitration module 2 exports to priority comparison module 4 is kept in Current interrupt priority register 64
At the end of CPU interrupt response, CPU writes End of Interrupt register 66,
Current interrupt priority reverts in Current interrupt priority register 64 by nested interrupt priority preservation module 5 simultaneously.
Interrupt vector generation module 3 in step (g) or step (h), under software pattern, needs this interrupt vector to be kept at and interrupts in cognitive register 65; Under hardware mode, interrupt vector is synchronous with giving the interrupt request of CPU, and informs at CPU and remain unchanged before interruptable controller receives interrupt request.
Nested priority preserves module 5 for preserving by the priority of nested interrupt.
When CPU informs that interruptable controller receives interrupt request, priority in Current interrupt priority register 64 is saved to nested interrupt priority and preserves module 5, when CPU informs that interruptable controller has interrupted, nested interrupt priority is preserved module 5 and priority is reverted in Current interrupt priority register 64.
For software interruption pattern, by reading to interrupt cognitive register 65 in interruptable controller, CPU informs that interruptable controller receives interrupt request; For hardware interrupts pattern, special signal is had to inform that interruptable controller receives interrupt request between CPU and interruptable controller, because CPU and interruptable controller may be present in different clock-domains, so inform that interruptable controller receives interrupt request singal and needs to carry out two sampling processing to CPU.
Priority arbitration module 2 in step (b) is arbitrated out optimum method of interrupting and is comprised the following steps:
(b1) priority of more all interruptions, selects the interruption that priority is the highest;
(b2) count the number of the highest interruption of priority, if number is 1, then the interruption that this priority is the highest is optimum interruption, if number is greater than 1, then selects the interruption that wherein interrupt number is minimum and is optimum interruption.
Before CPU interrupt response in step (g) or step (h) terminates, if there is the interruption of higher priority to enter priority arbitration module 2, then according to step (b) to (h) flow performing, if the execute phase of last interruption enter interrupt function after CPU to open external interrupt enable, to ensure interrupt nesting, then interruptable controller has twice interrupt request to occur, and has two priority preservations in nested interrupt priority preservation module 5.
It is " last in, first out " structure that nested priority in step (g) or step (h) preserves module 5, owing to only needing the value of preserving priority, and priority only has 0 to 15, priority be 15 interruption can not be nested, so nested priority preserves module only need preserve 0 to 14, the degree of depth that this nested priority preserves module 5 is 15.
Interrupt vector in step (h) is word alignment, and the bit wide of interrupt vector depends on the output external interrupt quantity of interruptable controller and the quantity of the configurable interruption of software.
The calculation expression of the figure place H of the interrupt vector in step (h) is H=log2 (M1+M2), wherein M1+M2=2
n+, M1 is external interrupt number, and M2 is configurable interrupt number, and N+ is positive integer;
Or H=[log2 (M1+M2)]+1, wherein M1+M2 ≠ 2
n+, M1 is external interrupt number, and M2 is configurable interrupt number, and N+ is positive integer, and [] expression rounds downwards.
According to the interruptable controller of this interrupt control method gained, comprise communication interface 1, priority arbitration module 2, interrupt vector generation module 3, priority comparison module 4, nested interrupt priority preservation module 5 and register module;
The external interrupt source of communication interface 1, interrupt source inputs look-at-me through communication interface 1;
Priority arbitration module 2, for selecting optimum interruption;
Interrupt vector generation module 3, the enable and interrupt vector for generation of interrupt vector;
Priority comparison module 4, for comparing the priority and the size of Current interrupt priority that priority arbitration module 2 exports;
Nested interrupt priority preserves module 5, for preserving by the priority of nested interrupt;
The look-at-me that communication interface 1 inputs and/or the interior configurable look-at-me input priority arbitration modules 2 after register module configuration preference level produced of register module;
Priority arbitration module 2 is selected in optimum and is had no progeny, and exports the optimum interrupt number interrupted to interrupt vector generation module 3, exports optimum priority of interrupting to priority comparison module 4;
Priority comparison module 4 and register module communicate to connect, the priority that optimum in this priority comparison module 4 interrupts and the interior Current interrupt priority set of register module compare, and comparative result controls the transmission of interrupt request in priority comparison module 4;
Register module and nested interrupt priority are preserved module 5 and are communicated to connect;
Interrupt vector generation module 3 coordinates register module and CPU to communicate to connect.
Register module comprises part to arrange/removes register 61, priority configuration register 62, control register 63, Current interrupt priority register 64, interrupt cognitive register 65, End of Interrupt register 66 and register read-write interface 67;
Software design patterns/removing register 61, for arranging, removing the configurable interruption of software;
Priority configuration register 62, for configuring the priority that each interrupts;
Control register 63, for configure interrupt controller mode of operation: software pattern or hardware mode;
Current interrupt priority register 64, for preserving the current priority performing interruption, when the priority after priority arbitration module 2 is greater than the priority in Current interrupt priority register 64, interrupt just producing, after reset, Current interrupt priority in Current interrupt priority register 64 is maximal value, ensures that all interruptions all can not produce;
Interrupt cognitive register 65, for preserving interrupt vector, under software pattern, CPU reads to interrupt cognitive register 65, inform that interruptable controller obtains interrupt vector number while receiving interrupt request, after CPU reads to interrupt cognitive register 65, the priority in Current interrupt priority register 64 can be kept at nested priority and preserve in module 5, and the priority that priority arbitration module 2 exports is kept in Current interrupt priority register 64;
End of Interrupt register 66, is write by CPU, and for representing that interrupt response terminates to interruptable controller, meanwhile, nested interrupt priority is preserved module 5 and priority reverted in Current interrupt priority register 64;
Register read-write interface 67, for accessing all registers;
The look-at-me that communication interface 1 inputs and/or the interior configurable look-at-me input priority arbitration modules 2 after priority configuration register 62 configuration preference level produced of software design patterns/removing register 61.
Priority comparison module 4 and Current interrupt priority register 64 communicate to connect, the priority that Current interrupt priority relatively in Current interrupt priority register 64 and the optimum in priority comparison module 4 interrupt, and the priority in priority comparison module 4 is stored into Current interrupt priority register 64.
Current interrupt priority register 64 and nested interrupt priority preserve the communication connection of module 5, Current interrupt priority in Current interrupt priority register 64 is saved in nested interrupt priority and preserves module 5, and realize preserving the reset of the Current interrupt priority in module 5 to Current interrupt priority register 64 by nested interrupt priority.
Control register 63 and interrupt vector generation module 3 communicate to connect, the output side signal controlling interrupt vector generation module 3 to.
Interrupt vector generation module 3 can be selected to communicate to connect with the cognitive register 65 of interruption and CPU, under software pattern, needs this interrupt vector to be kept at and interrupts in cognitive register 65; Under hardware mode, interrupt vector is synchronous with giving the interrupt request of CPU, and before CPU informs that interruptable controller receives interrupt request, the interrupt vector of output remains unchanged.Under hardware interrupts pattern, the base address of interrupt vector table is defined by CPU internal register, and the interrupt vector that side-play amount exports from interruptable controller, so interrupt vector is word alignment, the bit wide of interrupt vector depends on the output external interrupt quantity of interruptable controller and the quantity of the configurable interruption of software.
Interrupt cognitive register 65 to preserve module 5 signal with priority comparison module 4, Current interrupt priority register 64 and nested priority and be connected, End of Interrupt register 66 and Current interrupt priority register 64 and nested priority are preserved module 5 signal and are connected.
Interrupt source is level triggers.
With outside number of interruptions 128, the configurable number of interruptions of software be 8 situation be example, the course of work of the present invention is:
Exterior interrupt, configurable interruption and priority enter priority arbitration module 2, the configurable range of priority values of each interruption is 0 to 15, priority arbitration module 2 is in the interruption initiating interrupt request, arbitrate out the interruption that priority is the highest, if it is the same to there is most interrupt priority level value, choose the interruption that wherein interrupt number is minimum, the content of the interruption that priority stamping-out module 2 exports comprises priority and interrupt number, the priority exported enters priority comparison module 4, the interrupt number exported enters interrupt vector generation module 3, if without any interrupt request, the interrupt number exported is 0.
Priority priority arbitration module 2 exported in priority comparison module 4 and Current interrupt priority compare, if the priority that priority arbitration module 2 exports is greater than Current interrupt priority, priority comparison module 4 makes interruptable controller produce interrupt request to CPU.
Interrupt vector generation module 3 obtains the interrupt number that priority arbitration module 2 exports, be saved in and interrupted in cognitive register 65, as shown in Figure 2, interrupting preserving interrupt vector in cognitive register 65 is word alignment, so in software under disconnected pattern, CPU directly obtains the offset address (base address is determined by processor) of interrupt function while reading to interrupt cognitive register 65; Within hardware under disconnected pattern, while priority comparison module 4 produces interrupt request, interrupt vector generation module 3 produces interrupt vector and interrupt vector is enable, synchronously inputs CPU, the figure place H of interrupt vector:
If M1+M2=2N+, H=log2 (M1+M2), (M1 is external interrupt number, and M2 is configurable interrupt number, and N+ is positive integer);
Otherwise, H=[log2 (M1+M2)]+1, (M1 is external interrupt number, and M2 is configurable interrupt number, and N+ is positive integer, and [] expression rounds downwards).
Be 128 for external interrupt quantity, the configurable number of interruptions of software is the situation of 8, and interrupt vector is 8 bits.
CPU responds interruption, read to interrupt cognitive register 65 and inform that interrupting control CPU responds interruption, this read operation makes the priority in Current interrupt priority register 64 be saved to nested interrupt priority and preserves module 5, and the priority that priority arbitration module 2 exports is kept in Current interrupt priority register 64; CPU obtains the side-play amount of interrupt function address corresponding to interrupt vector simultaneously, performs the break in service function of response.
After interrupt function terminates, when CPU writes End of Interrupt register 66, represent that break in service function performs end, meanwhile, nested interrupt priority is preserved module 5 and priority is reverted in Current interrupt priority register 64.
If before interruption execution terminates, the interruption of higher priority arrives, according to above flow performing, after supposing to enter interrupt function, CPU can open external interrupt enable (guarantee interrupt nesting), have twice interrupt request to occur, and high-priority interrupt can nested low priority interrupt, nested interrupt priority is preserved module 5 and is had two priority and preserve.
Interrupt nesting mechanism of the present invention is simple, has and comparatively has low time delay, and interruptable controller accepts to interrupt sending interrupt request to interruptable controller to processor only needs 3 cycles.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. an interruptable controller, is characterized in that: comprise communication interface (1), priority arbitration module (2), interrupt vector generation module (3), priority comparison module (4), nested interrupt priority preservation module (5) and register module;
Described communication interface (1) external interrupt source, interrupt source is through communication interface (1) input look-at-me;
Described priority arbitration module (2), for selecting optimum interruption;
Described interrupt vector generation module (3), the enable and interrupt vector for generation of interrupt vector;
Described priority comparison module (4), for comparing the size of priority that priority arbitration module (2) exports and Current interrupt priority;
Described nested interrupt priority preserves module (5), for preserving by the priority of nested interrupt;
The look-at-me that described communication interface (1) inputs and/or the interior configurable look-at-me input priority arbitration modules (2) after register module configuration preference level produced of register module;
Priority arbitration module (2) is selected in optimum and is had no progeny, and exports the optimum interrupt number interrupted to interrupt vector generation module (3), exports optimum priority of interrupting to priority comparison module (4);
Priority comparison module (4) and register module communicate to connect, the priority that optimum in this priority comparison module (4) interrupts and the interior Current interrupt priority set of register module compare, and comparative result controls the transmission of interrupt request in priority comparison module (4);
Register module and nested interrupt priority are preserved module (5) and are communicated to connect;
Interrupt vector generation module (3) coordinates register module and CPU to communicate to connect.
2. interruptable controller according to claim 1, is characterized in that: described register module comprises part to arrange/remove register (61), priority configuration register (62), control register (63), Current interrupt priority register (64), interrupt cognitive register (65), End of Interrupt register (66) and register read-write interface (67);
Described software design patterns/removing register (61), for arranging, removing the configurable interruption of software;
Described priority configuration register (62), for configuring the priority that each interrupts;
Described control register (63), for configure interrupt controller mode of operation: software pattern or hardware mode;
Described Current interrupt priority register (64), for preserving the current priority performing interruption, after reset, the Current interrupt priority in Current interrupt priority register (64) is maximal value;
The cognitive register of described interruption (65), for preserving interrupt vector;
Described End of Interrupt register (66), is write by CPU, for representing that interrupt response terminates to interruptable controller;
Register read-write interface (67), for accessing all registers.
3. interruptable controller according to claim 2, is characterized in that: the look-at-me that described communication interface (1) inputs and/or the interior configurable look-at-me input priority arbitration modules (2) after priority configuration register (62) configuration preference level produced of software design patterns/removing register (61);
Described priority comparison module (4) and Current interrupt priority register (64) communicate to connect, the priority that Current interrupt priority relatively in Current interrupt priority register (64) and the optimum in priority comparison module (4) interrupt, and the priority in priority comparison module (4) is stored into Current interrupt priority register (64);
Described Current interrupt priority register (64) and described nested interrupt priority are preserved module (5) and are communicated to connect, Current interrupt priority in Current interrupt priority register (64) is saved in nested interrupt priority and preserves module (5), and realize preserving the reset of the Current interrupt priority in module (5) to Current interrupt priority register (64) by nested interrupt priority;
Described control register (63) and interrupt vector generation module (3) communicate to connects, the output side signal of control interrupt vector generation module (3) to;
Described interrupt vector generation module (3) can be selected to communicate to connect with the cognitive register of interruption (65) and CPU;
The cognitive register of described interruption (65) is preserved module (5) signal with described priority comparison module (4), Current interrupt priority register (64) and nested priority and is connected, and End of Interrupt register (66) and Current interrupt priority register (64) and nested priority are preserved module (5) signal and is connected.
4. interruptable controller according to claim 1, is characterized in that: described interrupt source is level triggers.
5. an interrupt control method, is characterized in that: comprise the following steps:
The selected mode of operation of control register (63) and the Current interrupt priority of Current interrupt priority register (64) in (a) setting interruptable controller;
B configurable interruption that () exterior interrupt and/or interruptable controller inside produce enters priority arbitration module (2) after configuration preference level, priority arbitration module (2) arbitrates out optimum interruption, enter step (c), if priority arbitration module (2) does not receive any interrupt request, then enter step (d);
C priority input priority comparison module (4) that optimum interrupts by () priority arbitration module (2), interrupt number input interrupt vector generation module (3) interrupted by optimum, enters step (e);
D interrupt number that () priority arbitration module (2) exports to interrupt vector generation module (3) is 0, enters step (e);
E Current interrupt priority in priority in priority comparison module (4) and Current interrupt priority register (64) compares by (), if the priority in priority comparison module (4) is not more than the Current interrupt priority in Current interrupt register (64), then repeat step (b) to step (e), if the priority in priority comparison module (4) is greater than the Current interrupt priority in Current interrupt priority register (64), then priority comparison module (4) exports interrupt request to CPU;
If f software pattern selected by () this control register (63), then enter step (g), if the selected hardware mode of this control register (63), then enter step (h);
G () is while priority comparison module (4) exports interrupt request to CPU, the interrupt number that priority arbitration module (2) exports is saved in and interrupts in cognitive register (65) by interrupt vector generation module (3)
Then CPU is read by register read-write interface (67) and interrupts cognitive register (65),
This read operation makes the Current interrupt priority in Current interrupt priority register (64) be saved to nested interrupt priority and preserves module (5), priority arbitration module (2) is kept in Current interrupt priority register (64) to the priority that priority comparison module (4) exports
CPU obtains the side-play amount of interrupt function address corresponding to interrupt vector simultaneously, performs the break in service function of response,
At the end of CPU interrupt response, CPU writes End of Interrupt register (66), and Current interrupt priority reverts in Current interrupt priority register (64) by nested interrupt priority preservation module (5) simultaneously;
H (), while priority comparison module (4) exports interrupt request to CPU, interrupt vector generation module (3) exports interrupt vector and interrupt vector enable signal to CPU,
When receiving the cognitive signal of hardware interrupts that CPU provides and being effective, Current interrupt priority in Current interrupt priority register (64) is saved to nested interrupt priority and preserves module (5), priority arbitration module (2) is kept in Current interrupt priority register (64) to the priority that priority comparison module (4) exports
At the end of CPU interrupt response, CPU writes End of Interrupt register (66),
Current interrupt priority reverts in Current interrupt priority register (64) by nested interrupt priority preservation module (5) simultaneously.
6. interrupt control method according to claim 5, it is characterized in that: the configurable interruption in described step (b) is produced by the software design patterns in interruptable controller/removing register (61), priority configuration scope in described priority configuration register (62) is 0 to 15, totally 16.
7. interrupt control method according to claim 5, is characterized in that: the priority arbitration module (2) in described step (b) is arbitrated out optimum method of interrupting and comprised the following steps:
(b1) priority of more all interruptions, selects the interruption that priority is the highest;
(b2) count the number of the highest interruption of priority, if number is 1, then the interruption that this priority is the highest is optimum interruption, if number is greater than 1, then selects the interruption that wherein interrupt number is minimum and is optimum interruption.
8. interrupt control method according to claim 5, it is characterized in that: before the CPU interrupt response in described step (g) or step (h) terminates, if there is the interruption of higher priority to enter priority arbitration module (2), then according to step (b) to (h) flow performing, if the execute phase of last interruption enter interrupt function after CPU to open external interrupt enable, to ensure interrupt nesting, then interruptable controller has twice interrupt request to occur, and has two priority preservations in nested interrupt priority preservation module (5).
9. interrupt control method according to claim 6, it is characterized in that: the nested priority in described step (g) or step (h) preserves module (5) for " last in, first out " structure, the degree of depth that this nested priority preserves module (5) is 15.
10. interrupt control method according to claim 5, it is characterized in that: the interrupt vector in described step (h) is word alignment, the bit wide of interrupt vector depends on the output external interrupt quantity of interruptable controller and the quantity of the configurable interruption of software, the calculation expression of the figure place H of described interrupt vector is H=log2 (M1+M2), wherein M1+M2=2
n+, M1 is external interrupt number, and M2 is configurable interrupt number, and N+ is positive integer;
Or H=[log2 (M1+M2)]+1, wherein M1+M2 ≠ 2
n+, M1 is external interrupt number, and M2 is configurable interrupt number, and N+ is positive integer, and [] expression rounds downwards.
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