CN105025241B

CN105025241B - A kind of image de-interlacing apparatus and method

Info

Publication number: CN105025241B
Application number: CN201410183142.6A
Authority: CN
Inventors: 高峰
Original assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Current assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Priority date: 2014-04-30
Filing date: 2014-04-30
Publication date: 2018-08-24
Anticipated expiration: 2034-04-30
Also published as: CN105025241A; WO2015165214A1

Abstract

The invention discloses a kind of image de-interlacing apparatus and method, the method includes：According to the de interlacing mode instruction of reception, determine the de interlacing pattern of pending image data, de interlacing processing is carried out to the pending image data using the determining corresponding de interlacing logic of de interlacing pattern, and closes other de interlacing logics in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination.

Description

A kind of image de-interlacing apparatus and method

Technical field

The present invention relates to technical field of image processing more particularly to a kind of image de-interlacing apparatus and methods.

Background technology

In technical field of image processing, interlaced picture video sequence can be converted to progressive image video by deinterlacing technique Sequence improves the clarity of picture to eliminate the defect of interlaced video sequence.Currently, widely used interlace-removing method includes： Linear de interlacing algorithm (Linear Deinterlacing Algorithm), non-linear de interlacing algorithm (Nonlinear Deinterlaeing Algorithm), Motion-adaptive De-interlacing Method (Motion Adaptive Deinterlacing ) and movement compensating algorithm Algorithm.Wherein, linear de interlacing algorithm and non-linear de interlacing algorithm are relatively simple, but It is, it is not satisfactory for the de interlacing treatment effect of strenuous exercise's video image；And Motion-adaptive De-interlacing Method and movement Backoff algorithm is relative complex, and hardware consumption is more, and the de interlacing treatment effect of strenuous exercise's video image is better than linearly De interlacing algorithm and non-linear de interlacing algorithm.

Currently, de-interlacing apparatus is only applicable to fixed moving scene, to be unfavorable for being widely used for de-interlacing apparatus.

Invention content

In view of the problems of the existing technology, a kind of image de-interlacing apparatus of offer of the embodiment of the present invention and method.

An embodiment of the present invention provides a kind of image de-interlacing apparatus, described device includes：Configuration module and de interlacing mould Block；Wherein,

The configuration module determines the de interlacing of pending image data for the de interlacing mode instruction according to reception Pattern；

The de interlacing module, the corresponding de interlacing logic of de interlacing pattern for being determined using configuration module is to described Pending image data carries out de interlacing processing, and closes in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination Other de interlacing logics.

In said program, the configuration module is specifically used for：According to the de interlacing mode instruction of reception, de interlacing is posted Storage carries out the instruction configuration of corresponding de interlacing pattern；

Correspondingly, the de interlacing module is gone for being configured according to the instruction of the de interlacing register using corresponding Interlacing logic carries out de interlacing processing to the pending image data, and closes except the de interlacing pattern of the determination is corresponding Other de interlacing logics outside de interlacing logic.

In said program, the configuration module is additionally operable to：

According to the length and width of pending image data, in resolution register to the resolution ratio of pending image data into Row configuration；And it is configured to enable the first enable signal of the de interlacing module in enabled register.

In said program, the configuration module is additionally operable to when the determining corresponding de interlacing logic of de interlacing pattern be band When there are four de interlacing logics of motion detection, it is configured to enable the first of the de interlacing module in enabled register to make Before energy signal, first threshold and second threshold are configured in threshold register；The first threshold and second threshold are used In judging that pixel is to be kept in motion or stationary state.

In said program, the configuration module is additionally operable to be disposed when a frame image data, and subsequently also has picture number When according to needing processing, it is configured to remove the second enable signal of interrupt signal in interrupt register, and again to resolution ratio Register is configured, or is configured again to resolution register and threshold register.

In said program, described device further includes：Top-level module and synchronization module；Wherein,

The top-level module, the input/output interface for providing described device and external connection；

The synchronization module, the parameter synchronization of each register for configuring the configuration module to the de interlacing mould Block.

In said program, the synchronization module is specifically used for：The clock of each register is synchronized by handshake as institute State the work clock of de interlacing module.

In said program, the de interlacing module is additionally operable to use random access memory (ram, random access Memory) the mode being multiplexed carries out de interlacing processing to the pending image data.

It is described by the way of ram multiplexings in said program, de interlacing processing is carried out to the pending image data, Including：

Under not enabled de interlacing pattern, ram is for storing pending data, so that the data of asynchronous input carry out together Step output；

Inside under de interlacing pattern or four de interlacing patterns with motion detection, the ram waits locating for storing Manage image data in Nth row image data and the N-1 row image datas in pending image data so that go inside every The corresponding de interlacing logic of row pattern or the corresponding de interlacing logic of four de interlacing patterns with motion detection are waited for described It handles image data and carries out corresponding de interlacing processing.

The embodiment of the present invention additionally provides a kind of image interlace-removing method, the method includes：

According to the de interlacing mode instruction of reception, the de interlacing pattern of pending image data is determined；

The pending image data is carried out at de interlacing using the determining corresponding de interlacing logic of de interlacing pattern Reason, and close other de interlacing logics in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination.

In said program, the de interlacing mode instruction according to reception determines the de interlacing mould of pending image data Formula, including：

According to the de interlacing mode instruction of reception, the instruction that de interlacing register is carried out to corresponding de interlacing pattern configures, Determine the de interlacing pattern of pending image data；

Correspondingly, it is configured according to the instruction of the de interlacing register, waits locating to described using corresponding de interlacing logic It manages image data and carries out de interlacing processing, and close other in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination De interlacing logic.

In said program, in the corresponding de interlacing logic of the de interlacing pattern of the determination to the pending image data De interlacing processing is carried out, and closes other de interlacing logics in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination Before, the method further includes：

In said program, when the determining corresponding de interlacing logic of de interlacing pattern be four with motion detection go every When row logic, before being configured to the first enable signal for enabling the de interlacing module in enabled register, the method Further include：

First threshold and second threshold are configured in threshold register；The first threshold and second threshold are for sentencing Disconnected pixel is to be kept in motion or stationary state.

In said program, when a frame image data is disposed, and subsequently also has image data to need processing, the side Method further includes：

It is configured to remove the second enable signal of interrupt signal in interrupt register, and again to resolution register It is configured, or resolution register and threshold register is configured again.

In said program, each register is configured, and in the corresponding de interlacing logic pair of the de interlacing pattern of the determination The pending image data carries out de interlacing processing, and closes the corresponding de interlacing logic of de interlacing pattern except the determination Before outer other de interlacing logics, the method further includes：

By the de interlacing module of the parameter synchronization of each register of configuration to image de-interlacing apparatus.

In said program, the de interlacing mould for the device that parameter synchronization to the de interlacing of each register by configuration is handled Block is：

By the clock of each register by handshake synchronize be the de interlacing module work clock.

In said program, when carrying out de interlacing processing to the pending image, the method further includes：Using ram The mode of multiplexing carries out de interlacing processing to the pending image data.

Image de-interlacing apparatus provided in an embodiment of the present invention and method are determined according to the de interlacing mode instruction of reception The de interlacing pattern of pending image data, using the determining corresponding de interlacing logic of de interlacing pattern to the pending figure As data carry out de interlacing processing, and close other in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination go every Row logic；In this way, user can voluntarily be configured to interlaced mode under different moving scenes, to make the device be suitable for more More scenes.

Description of the drawings

Fig. 1 is a kind of image de-interlacing apparatus structural schematic diagram that the embodiment of the present invention one provides；

Fig. 2 is another image de-interlacing apparatus structural schematic diagram that the embodiment of the present invention one provides；

Fig. 3 is the structural schematic diagram for the de interlacing module that the embodiment of the present invention one provides；

Fig. 4 is data flow when no data inputs under the not enabled de interlacing pattern that the embodiment of the present invention one, two provides Schematic diagram；

Fig. 5 is that a unit is inputted into channel 1 under the not enabled de interlacing pattern that the embodiment of the present invention one, two provides Image data when data flow schematic diagram；

Fig. 6 is that two units are inputted into channel 1 under the not enabled de interlacing pattern that the embodiment of the present invention one, two provides Image data, into channel 2 input a unit image data when data flow schematic diagram；

It is synchronized by channel 1 and channel 2 under the not enabled de interlacing pattern that Fig. 7 provides for the embodiment of the present invention one, two defeated Go out data flow schematic diagram when data；

Fig. 8 is the data flow schematic diagram when de interlacing logical schema that the embodiment of the present invention one, two provides is opened；

Fig. 9 is the row average interpolation method schematic diagram that the embodiment of the present invention one, two provides；

Figure 10 is four with the motion detection interlace-removing method schematic diagram that the embodiment of the present invention one, two provides；

Figure 11 is the de-interlaced method flow schematic diagram of image provided by Embodiment 2 of the present invention.

Specific implementation mode

In various embodiments of the present invention, according to the de interlacing mode instruction of reception, pending image data is determined De interlacing pattern carries out de interlacing using the determining corresponding de interlacing logic of de interlacing pattern to the pending image data Processing, and close other de interlacing logics in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination.

Technical scheme of the present invention is described in further detail below by drawings and the specific embodiments.

Embodiment one

The present embodiment provides a kind of image de-interlacing apparatus, as shown in Figure 1, described device includes：Configuration module 11, go every Row module 12；Wherein；

The configuration module 11, for according to the de interlacing mode instruction of reception, determine pending image data go every Row pattern；

The de interlacing module 12, the corresponding de interlacing logic pair of de interlacing pattern for being determined using configuration module 11 The pending image data carries out de interlacing processing, and closes the corresponding de interlacing logic of de interlacing pattern except the determination Outer other de interlacing logics.

Here, the configuration module 11, is specifically used for according to the de interlacing mode instruction of reception, by de interlacing register into The instruction configuration of the corresponding de interlacing pattern of row；

Correspondingly, the de interlacing module 12, for being configured according to the instruction of the de interlacing register, use is corresponding De interlacing logic carries out de interlacing processing to the pending image data, and closes except the de interlacing pattern of the determination corresponds to De interlacing logic outside other de interlacing logics.

When practical application, built-in it can be patrolled there are three de interlacing in image de-interlacing apparatus provided in an embodiment of the present invention Volume, respectively：Not enabled de interlacing logic, in-field deinterlacing logic and four de interlacing logics with motion detection；Its In, the function of not enabled de interlacing logic is：The pending image data of asynchronous input is synchronized into output；In go every The function of row logic is：The Y-component to the pending image data of input and UV components carry out at in-field deinterlacing logic respectively Reason；The function of four de interlacing logics with motion detection is：Respectively to the Y-component and UV of the pending image data of input Component carries out four de interlacing logical process.

Correspondingly, when the de interlacing mode instruction of reception is not enabled de interlacing pattern instruction, the configuration module 11 The state bit instruction of the de interlacing mode register can be configured to 00 according to the de interlacing mode instruction of reception, to Realize that the instruction to the de interlacing pattern of the de interlacing register configures, it is pending to show to the de interlacing module 12 The de interlacing pattern of image data is not enabled de interlacing pattern；When the de interlacing mode instruction of reception is in-field deinterlacing pattern When instruction, the configuration module 11 can be according to the de interlacing mode instruction of reception, by the shape of the de interlacing mode register State bit instruction is configured to 01, to realize that the instruction to the de interlacing pattern of the de interlacing register configures, so as to described De interlacing module 12 shows that the de interlacing pattern of pending image data is in-field deinterlacing pattern；When the de interlacing pattern of reception When instruction indicates for four de interlacing patterns with motion detection, the configuration module 11 can be according to the de interlacing mould of reception Formula instructs, and the state bit instruction of the de interlacing mode register is configured to 10, to realize to the de interlacing register De interlacing pattern instruction configuration, to show that the de interlacing pattern of pending image data is to the de interlacing module 12 Four de interlacing patterns；Wherein, the de interlacing mode register can also reserve a state bit instruction 11, subsequently to expand Exhibition application.

Here, the de interlacing module 12 is patrolled using the corresponding de interlacing of de interlacing pattern that the configuration module 11 determines It collects and de interlacing processing is carried out to the pending image data, and close the corresponding de interlacing of de interlacing pattern except the determination Before other de interlacing logics outside logic, the configuration module 11 also needs to configure the relevant information of each register, So that the de interlacing module 12 can use corresponding de interlacing logic to carry out de interlacing processing to the pending data；It is described The relevant information for each register that configuration module 11 needs to configure, can specifically include：

The configuration module 11 is according to the length and width of pending image data, to pending image in resolution register The resolution ratio of data is configured, so that de interlacing module 12 can handle the image data of different resolution；Wherein, it actually answers Used time, the resolution of general in-field deinterlacing logic and four pending image datas of de interlacing logical requirements with motion detection Rate is 1920*1080；

When determining de interlacing pattern is four de interlacing patterns with motion detection, the configuration module 11 is in threshold First threshold T1 and second threshold T2 is configured in value register；Wherein, under four de interlacing patterns with motion detection, The first threshold T1 and second threshold T2 is kept in motion or stationary state for judging pixel.

After the completion of the configuration module 11 is by above-mentioned each register configuration, the configuration module 11 is finally enabled (enable) it is configured to enable the first enable signal of the de interlacing module 12 in register；Specifically, work as described device When needing to handle image data, the configuration module 22 configures the first enable signal of the enable registers to high electricity It is flat, in other words start the de interlacing module 12 to enable the de interlacing module 12；When frame image data processing When finishing, and subsequently needing processing without image data, the configuration module 22 configures low level in the enable registers, In other words the de interlacing module 12 is closed to go to enable the de interlacing module 12.

When practical application, after a frame image data is disposed, and subsequently also have image data need processing when, it is described Configuration module 11 also needs to the second enable signal for being configured to remove interrupt signal in interrupt register, and again to differentiating Rate register and threshold register are configured, to carry out the processing of next frame image data；Here, when a frame image procossing is complete After finishing, described device will produce interrupt signal, it is therefore desirable to configure the second enable signal of the interrupt register to height Level, to remove interrupt signal, to carry out the processing of subsequent image data.

As shown in Fig. 2, described device further includes：Top-level module 21 and synchronization module 22；Wherein,

The top-level module 21, the input/output interface for providing described device and external connection；

The synchronization module 22, the parameter synchronization of each register for configuring the configuration module 11 to it is described go every Row module 12.

Specifically, it is the de interlacing module that the synchronization module 22, which synchronizes the clock of each register by handshake, 12 work clock.

More specifically, after the completion of the configuration module 11 is to above-mentioned each register configuration, the synchronization module 22 will be each The clock synchronization request of register is sent to the de interlacing module 12, and by the clock synchronization request of the de interlacing module 12 Response is sent to the synchronization module 22, to be responded each register by clock synchronization request and clock synchronization request In configurable clock generator synchronize be the de interlacing module 12 work clock.

Wherein, before inputting the first frame image data, each register, therefore can be to first frame figure all in effective status As data are handled accordingly；Each register includes：Resolution register, de interlacing register, interrupt register, with And enable registers；Here, described each when determining de interlacing pattern is four de interlacing patterns with motion detection Register further includes：Threshold register.

Here, when carrying out first frame image real time transfer, when the second enable signal of enable registers is in high electricity When level state, after receiving the pending image data of first frame by the top-level module 21, the de interlacing module 12 is according to pre- The resolution ratio of the resolution register first configured determines the resolution ratio of the first frame image data, according to not enabled de interlacing pattern pair The de interlacing logic answered carries out de interlacing processing to the pending image data, and closes that in-field deinterlacing pattern is corresponding to go Interlacing logic and the corresponding logic of four de interlacing patterns with motion detection；Alternatively, being corresponded to according to in-field deinterlacing pattern De interlacing logic de interlacing processing is carried out to the pending image data, and close that not enabled de interlacing pattern is corresponding to go Interlacing logic and the corresponding de interlacing logic of four de interlacing patterns with motion detection；Alternatively, according to motion detection De interlacing pattern corresponding de interlacing logic de interlacing processing is carried out to the pending image data, and close not enabled go The corresponding de interlacing logic of interlaced mode and the corresponding de interlacing logic of in-field deinterlacing pattern.

Wherein, the de interlacing module 12 goes the pending image data using corresponding de interlacing logic It when interlacing is handled, is additionally operable in such a way that ram is multiplexed, de interlacing processing is carried out to the pending image data.Wherein, institute Stating ram includes：First ram, the 2nd ram, the 3rd ram, the 4th ram；First ram, the 2nd ram, the 3rd ram and the 4th Ram capacity is all 120*128；Described 120 represent the maximum memory space of ram, and described 128 indicate the bit wide of ram.

Here, described to refer to by the way of ram multiplexings：Under not enabled de interlacing pattern, the first ram, second Ram, the 3rd ram and the 4th ram, for storing pending data, the data of asynchronous input to be synchronized output； Inside under de interlacing pattern or four de interlacing patterns with motion detection, the first ram, the 2nd ram, the 3rd ram And the 4th ram, for storing the Nth row image data in pending image data and the N-1 rows in pending image data Image data, so as to can the corresponding de interlacing logic of de interlacing pattern or four de interlacing patterns with motion detection inside Under corresponding de interlacing logic, corresponding de interlacing processing is carried out to pending image data.

As shown in figure 3, the de interlacing module 12 includes：Data input submodule 121, read data submodule 122 and De interlacing logic sub-modules 123；Wherein,

The data input submodule 121, for storing the pending image data of input to all de interlacing logics In shared ram；

The reading data submodule 122, for reading the pending image data in ram；

The de interlacing logic sub-modules 123 are used for according to determining de interlacing pattern to the pending picture number of reading According to progress de interlacing processing.

Specifically, when the configuration module 11 is according to the de interlacing mode instruction of reception, by the de interlacing Mode register The state bit instruction of device is configured to 00, that is, when determining the de interlacing pattern of pending image data not enable de interlacing pattern, In-field deinterlacing pattern and the corresponding de interlacing logic of four de interlacing patterns with motion detection can then be automatically closed；This In, the image data currently inputted can be interlaced video sequence, can also be progressive scanning sequence；The device may include four A input channel, when the image data of input is interlaced video sequence, data input submodule 121 will be in interlaced video sequence It, will be in the image data input channel 2 of even field in the image data input channel 1 of odd field；When the image data of input is When progressive scanning sequence, the data input submodule 121 is by the image data input channel 1 of odd field in progressive scanning sequence In, it will be in the image data input channel 2 of even field；Wherein, the input address in the channel 1 is addr_in_1, output address For addr_out_1；The input address in channel 2 is addr_in_2, output address addr_out_2；As shown in figure 4, initial Under the conditions of, described addr_in_1, addr_in_2, addr_out_1 and addr_out_2 are 0.

Here, the output sub-module 125 can be by channel 1 and the channel 2 by the Y of the image data of asynchronous input Component synchronism output is to display device；By the UV component synchronism output display devices of the image data of asynchronous input；When described After the Y-component and UV component synchronism outputs to display device of image data, you can see in a display device through it is not enabled go every Image after row logical process；Wherein, the display device can be mobile phone, computer etc..

Here, by taking Y-component as an example, as shown in figure 5, when the data input submodule 121 inputs a list by channel 1 After the pending image data of position, the Y-component of the pending image data of one unit is stored into the first ram, institute The address for stating addr_in_1 just adds 1, and output addr_out_1 is constant, when the data input submodule 121 there is not directed walk 2 When the pending image data of middle input, the address of the addr_in_2 is constant, and the addr_out_2 is also constant；Wherein, described The image data of one unit includes 16 pixels.

As shown in fig. 6, when the data input submodule 121 inputs the image data of a unit again by channel 1, Also the Y-component of the image data is stored into the first ram, the address of the addr_in_1 is 2, and output addr_out_1 is not Become；When the data input submodule 121 inputs the image data of a unit into channel 2, by the Y of the image data points In amount storage to the 3rd ram, the address of the addr_in_2 is 1, and the addr_out_2 is also constant；It can be seen that channel 1 Input address be not equal to the output address in channel 1, the input address in channel 2 is also not equal to the output address in channel 2, that is, meets (addr_in_1！=addr_out_1) ＆＆ (addr_in_2！=addr_out_2), at this moment, as shown in fig. 7, when described defeated Go out submodule 125 by channel 1 and channel 2 while exporting the unit data of a Y-component, the addr_out_1 and addr_ Out_2 adds 1 simultaneously, in this way, completing synchronism output to the image data of asynchronous input；Wherein, the first ram and third The bit wide and memory space of ram is identical, when input address addr_in_1, addr_in_2 reaches the upper limit of ram, Addr_in_1 and addr_in_2 back within 0.

Here, the process flow that output is synchronized to the UV components of asynchronous input is similar with the process flow of Y-component, Difference is that the UV components of the pending image data in input channel 1 are stored in second by the data input submodule 121 In ram, the UV components of pending image data in input channel 2 are stored in the 4th ram.

When the configuration module 11 is according to the de interlacing mode instruction of reception, by the state of the de interlacing mode register Bit instruction is configured to 01, that is, when determining that the de interlacing pattern of pending image data is in-field deinterlacing pattern, then can close automatically De interlacing pattern and the corresponding de interlacing logic of four de interlacing patterns with motion detection cannot not be closed enabledly；Here, current defeated The image data entered is interlaced video sequence, and by taking the Y-component y_1_in in vedio data as an example, the data input submodule Block 121, will be in the y_1_in input channels 1 of Nth row image data in the fields t of interpolation；Wherein, the N is more than or equal to 1 Integer, when N be equal to 1 when, indicate the data input submodule 121 by the y_1_ of the 1st row image data in the fields t of interpolation In in input channels 1.

Here, as shown in figure 8, the data input submodule 121 is Nth row image data in the fields t by interpolation Two pixels of y_1_in are one group and are inputted, and are temporarily stored in the first preparation register datain_r081, described first Prepare register datain_r081 to splice the pixel of the y_1_in of the first ram in channel 1, until y_1_in is spliced Full 16 pixels, and the data datain of full 16 pixels of splicing is transmitted to the second preparation register datain_r182 In；When the bit wide of datain reaches 128, the first preparation register datain_r081 will read ram signals read_out It draws high, i.e. read_out=1, the data submodule 122 of reading reads it in the first ram according to the format that two pixels are one group First group of datain of the Y-component of the N-1 row image datas of preceding storage, and by the first of the Y-component of N-1 row image datas Group datain is exported to the first output register data_out83；Wherein, the Y-component of the N-1 row image datas is Nth row The initial address addr_ram of the lastrow image data of Y-component, the first ram is 0；One group of datain includes 16 A pixel.

When the reading data submodule 122 exports first group of datain of the Y-component of N-1 row image datas to first After output register data_out83, the first preparation register datain_r081 drags down read_out, i.e. read_out =0；Ram signals write_into will be write to draw high, i.e. write_into=1, described second prepares storage datain_r182 by the First group of datain of the y_1_in of N row image datas is written in the first ram, and the addr_ram adds 1 automatically；

Prepare register datain_r182 by first group of datain of the y_1_in of Nth row image data when described second After being written in the first ram, the data input submodule 21 is additionally operable to second group of the y_1_in of input Nth row image data datain；Identical method is used with first group of datain of the y_1_in of input Nth row image data, when first preparation After register datain_r081 completes splicing to second group of datain of the y_1_in of Nth row image data, by Nth row image Second group of datain of the y_1_in of data is transmitted to described second and prepares register datain_r182, then read_out is drawn Height, first group of datain for reading data submodule 122 and reading the y_1_in of Nth row image data, and the first output is posted First group of datain of the Y-component of N-1 row image datas is exported to the second output register data_ in storage data_out83 out r85；Second group of datain of the Y-component of N-1 row image datas in the first ram is exported to the first output deposit Device data_out83；First group of datain of the y_1_in of the Nth row image data is exported to the first delay time register In datain_dly84；

The reading data submodule 122 exports first group of datain of the y_1_in of N row image datas to the first delay After register datain_dly84, the first preparation register datain_r081 drags down read_out；By write_into It draws high, described second prepares register datain_r182 by second group of datain of the y_1_in of Nth row image data write-in the In one ram, the addr_ram adds 1 automatically；

Prepare register datain_r182 by second group of datain of the y_1_in of Nth row image data when described second After being written in the first ram, the data input submodule 121 is additionally operable to the third group of the y_1_in of input Nth row image data datain；Identical method is used with first group of y_1_in of input Nth row image data, second group of datain, when described First prepares after register datain_r081 completes splicing to the third group datain of the y_1_in of Nth row image data, by the The third group datain of the y_1_in of N row image datas is transmitted to described second and prepares register datain_r182, then will Read_out is drawn high, second group of datain for reading data submodule 122 and reading the y_1_in of Nth row image data, by the Second group of datain of the Y-component of N-1 row image datas is exported to the second output and is posted in one output register data_out83 Storage data_out r85；The third group datain of the Y-component of N-1 row image datas in first ram is exported to One output register data_out83；Second group of datain of the y_1_in of the Nth row image data is exported to first and is prolonged It delays in the dispatch of in storage datain_dly84；

The reading data submodule 122 exports second group of datain of the y_1_in of N row image datas to the first delay After register datain_dly84, the first preparation register datain_r081 drags down read_out；By write_into It draws high, described second prepares register datain_r182 by the third group datain write-in of the y_1_in of Nth row image data the In one ram, the addr_ram adds 1 automatically；Wherein,

In order to ensure the Nth row image data not Jing Guo de interlacing calculation process Y-component can with through de interlacing at The Y-component energy synchronism output of Nth row image data after reason, each group of datain are also needed to by the second delay time register The delay of datain_dly086 and third delay time register datain_dly187；The first delay time register datain_ The delay time of dly84, the second delay time register datain_dly086 and third delay time register datain_dly187 can be certainly Row configuration.

When the reading data submodule 122 reads the third group of the Y-component of N-1 row image datas in the first ram After datain, first group datain of the de interlacing logic sub-modules 123 to the Y-component of the N-1 row image datas of output In-field deinterlacing logical operation process is carried out with first group of datain of the Y-component of the Nth row image data of input；Specifically, As shown in figure 9, use row average interpolation method based on edge first, near interpolation point to t in Nth row image data The pixel of first group of datain of Y-component carries out edge detection, is secondly averaging two pixels on the edge, will be averaged It is worth as interpolation result to the Y-component of Nth row image data into row interpolation；Here it is possible to carry out edge to the matrix of i rows j row To obtain interpolation result, the coordinate of the i-th row jth row is P (i, j) for detection；For example, parameter P value is taken as 1, i.e., to 3 rows 3 row Matrix does edge detection and obtains interpolation result, can will be in t-1 if the pixel of Nth row is needed into row interpolation in t The color component of nth row of pixels copies in the corresponding pixel of Nth row in interpolation t；For example, if in t most The pixel of a line is needed into row interpolation afterwards, then can the color component of last column pixel in t-1 be copied to interpolation t In the corresponding pixel of last column in；Here it is possible to take same method to the interpolation points of each row into row interpolation.

Wherein, provided in this embodiment based on edge compared with the method for being simply averaging upper and lower two rows pixel Row average interpolation method can more clearly from show the edge of image；The edge is that diagonally adjacent two pixels are exhausted When being minimum to the difference of value, the line segment that is connected by the two pixels；The β is the size of picture element matrix.

When the data input submodule 121 uses the 4th of the y_1_in of identical method input Nth row image data When group datain, the reading data submodule 122 is read out corresponding data, is written using above-mentioned processing method；It is described De interlacing logic sub-modules 123 are using above-mentioned interlace-removing method to second group of the Y-components of the N-1 row image datas of output Second group of datain of the Y-component of datain and the Nth row image data of input carries out in-field deinterlacing logical operation process, directly It is completed to frame image data processing；

Here, it after the de interlacing logic sub-modules 123 carry out de interlacing logical operation process to image data, is additionally operable to The pixel of de interlacing treated image data is combined；And export the de interlacing image data after combination.

The de interlacing logic sub-modules 123 are by first group of the Y-component of the N-1 row image datas after de interlacing First group of datain of the Y-component of datain and Nth row image data carries out recombination logical operation process, until having handled a frame Image data；Wherein, first group of datain of the Y-component of the N-1 row image datas after the de interlacing and Nth row picture number According to first group of datain of Y-component be also with two pixels be that one group of format is exported, so de interlacing is needed to patrol Submodule 123 is collected to recombinate datain；

It, will be without passing through de interlacing operation after the de interlacing logic sub-modules 123 recombinate one group of datain The Y-component of the Nth row image data of processing is exported from channel 2, by the Y of the Nth row image data after recombination logical operation process Component is output to from channel 1 in temporary register temp_data88 so that the image data exported by channel 1 with by logical The image data that road 2 exports can synchronize output, until having exported a frame image data.

Here, the present embodiment can take alternate line eliminating process method pair N same as the Y-component of Nth row image data The UV components of row image data carry out de interlacing processing；The main distinction is：The UV components of N-1 row image datas are by Two ram storages.

In this way, inside under de interlacing pattern, with continually entering for image data, constantly to Nth row image data Y-component, UV components be respectively completed in-field deinterlacing processing, you can obtain a final frame image data.

When the configuration module 11 is according to the de interlacing mode instruction of reception, by the state of the de interlacing mode register Bit instruction is configured to 10, that is, determines that the de interlacing pattern of pending image data is four de interlacing patterns with motion detection When, then de interlacing pattern and the corresponding de interlacing logic of in-field deinterlacing pattern cannot can not be automatically closed enabledly；Wherein, with fortune Under four de interlacing patterns of dynamic detection, Motion Adaptive method is to judge whether pixel moves by motion detection, due to fortune Dynamic detection cannot accurately detect out whether pixel is movement, so, in general, testing result is divided into three kinds of situations：It is aobvious Write movement, static and do not move significantly.When testing result is significantly movement, the de interlacing logic sub-modules 123 are then adopted Use interpolation algorithm carries out de interlacing processing to image data；When testing result is static, the de interlacing logic submodule Block 123 then uses occasion and algorithm carries out de interlacing processing to image data；It is described to go when testing result is not move significantly The movement of notable motion and standstill is then merged and is gone to image data by interlacing logic sub-modules 123 according to a certain percentage Interlacing is handled.

As shown in Figure 10, the value of Delta_1 be color component R, G of three pixels of interpolation point lastrow in t, B, the sum of the absolute value of each difference of color component of A three pixels corresponding with t-2；The value of Delta_2 is t-1 In with the color component of three pixels in the row corresponding to the row residing for interpolation point in t with t+1 in correspond in row three The sum of the absolute value of each difference of color component of pixel；Three pixels of interpolation point lastrow in value t of Delta_3 Point color component R, G, B, A three pixels corresponding with t-2 color component interpolation absolute value and；Wherein, In t described interpolation point be Figure 10 in ater point, described Delta_1, Delta_2, Delta_3 and be Delta_ The value of sum；I.e.：

Delta_sum=Delta_1+Delta_2+Delta_3；

The interpolation result u can be obtained using formula (1)：

Delta_sum >=the T2 indicates significantly movement；Delta_sum≤the T1 indicates static；The T1<Delta_ sum<T2 expressions do not move significantly；The value of the f (T1, T2) is obtained by formula (2)；

Wherein, u is interpolation result；X1 is the value of corresponding pixel points in t-1；X2 is obtained according to field interpolation algorithm Interpolation result；First threshold T1 in the threshold register and second threshold T2, can configure according to actual conditions.

Here, when the data input submodule 121 is by the pending image data, pending in t-1 in t-2 Pending image data in image data, t and the pending image data in t+1 respectively by channel 1,3,2,4 points Not Shu Ru after, the Y-component of the pending image data of Nth row in t-2 is stored in the first ram, by the N in t-2 The UV components of the pending image data of row are stored in the 2nd ram, and the Y-component of the pending image data of Nth row in t is stored up There are in the 3rd ram, the UV components of the pending image data of Nth row in t are stored in the 4th ram, according to it is above-mentioned After data processing method under in-field deinterlacing pattern is handled image data；The de interlacing logic sub-modules 123 According to above-mentioned formula (1) (2) respectively to first group of datain and t-2 of the Y-component of the N-1 row image datas in t-2 and t And t in Nth row image data Y-component first group of datain progress de interlacing logical operation process, until a frame Image real time transfer is completed；Here, because need to only handle the pending image data of Nth row in t-1 and the N in t+1 The pending image data of row, need not handle the pending image data of N-1 rows in t-1 and the N-1 rows in t+1 wait for Image data is handled, so pending image data in t-1 and the pending figure in t+1 need not be stored in ram As data；When in t-1 pending image data and t+1 in pending image data respectively from channel 3,4 inputs Afterwards, directly the pending image data of the Nth row of pending image is handled according to above-mentioned formula (1) (2).

Specifically, the de interlacing logic sub-modules 123 are by the of the Y-component of the N-1 row image datas after de interlacing First group of datain of the Y-component of one group of datain and Nth row image data carries out recombination logical operation process, until having handled One frame image data；Wherein, the first group of datain Yu Nth row figure of the Y-component of the N-1 row image datas after the de interlacing It is that one group of format is exported as first group of datain of the Y-component of data is also with two pixels, so described in needing De interlacing logic sub-modules 123 recombinate datain.

After de interlacing logic sub-modules 123 recombinate one group of datain, by the N after recombination logical operation process The Y-component of row image data is exported from channel 2, will recombinate the Y-component of the Nth row image data after logical operation process from channel 1 is output in temporary register temp_data88, so that the image data exported from channel 1 and the picture number exported from channel 2 According to output is synchronized, until having exported a frame image data.

When practical application, the top-level module 21, the configuration module 11, the de interlacing module 12 and the synchronization Module 22 can be by the central processing unit (CPU, Central Processing Unit) in image de-interlacing apparatus, digital signal Processor (DSP, Digital Signal Processor) or programmable logic array (FPGA, Field-Programmable Gate Array) it realizes.

Image de-interlacing apparatus provided in this embodiment, cannot not be built-in with enabledly de interlacing logic, in-field deinterlacing logic with And four de interlacing logics, three kinds of logics with motion detection, user can be facilitated voluntarily to select de interlacing according to different scenes Pattern, makes that it is suitable for more scenes.

The device using the method for ram multiplexings, saves the spaces ram simultaneously.

Embodiment two

Corresponding to embodiment one, the present embodiment additionally provides a kind of image interlace-removing method；As shown in figure 11, this method packet Include following steps：

Step 1100, according to the de interlacing mode instruction of reception, the de interlacing pattern of pending image data is determined；

In this step, according to the de interlacing mode instruction of reception, de interlacing register is subjected to corresponding de interlacing pattern Instruction configuration.

When practical application, use for convenience, can in image de-interlacing apparatus built-in three de interlacing logics, respectively For：Not enabled de interlacing logic, in-field deinterlacing logic and four de interlacing logics with motion detection；Wherein, do not make Can the function of de interlacing logic be：The pending image data of asynchronous input is synchronized into output；In-field deinterlacing logic Function be：The Y-component to the pending image data of input and UV components carry out in-field deinterlacing logical process respectively；It carries The function of four de interlacing logics of motion detection is：Respectively the Y-component to the pending image data of input and UV components into Four de interlacing logical process of row.

Correspondingly, when the de interlacing mode instruction of reception is not enabled de interlacing pattern instruction, it can be according to reception The state bit instruction of the de interlacing mode register is configured to 00 by de interlacing mode instruction, to realize to it is described go every The instruction of the de interlacing pattern of row register configures, so as to determine the de interlacing pattern of pending image data be it is not enabled go every Row pattern；It, can be according to the de interlacing pattern of reception when the de interlacing mode instruction of reception is that in-field deinterlacing pattern indicates Instruction, 01 is configured to by the state bit instruction of the de interlacing mode register, to realize to the de interlacing register The instruction of de interlacing pattern configures, to determine that the de interlacing pattern of pending image data is in-field deinterlacing pattern；When connecing When the de interlacing mode instruction of receipts is four de interlacing patterns instruction with motion detection, referred to according to the de interlacing pattern of reception It enables, the state bit instruction of the de interlacing mode register is configured to 10, the de interlacing register is gone to realize The instruction of interlaced mode configures, to determine that the de interlacing pattern of pending image data is four de interlacing patterns；Wherein, institute A state bit instruction 11 can also be reserved by stating de interlacing mode register, so as to subsequent expansion application.

Step 1101, the pending image data is carried out using the determining corresponding de interlacing logic of de interlacing pattern De interlacing processing, and close other de interlacing logics in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination.

Here, the de interlacing logic using determining de interlacing pattern pair goes the pending image data Interlacing is handled, and is closed before other de interlacing logics in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination, It also needs to configure the relevant information of each register, corresponding de interlacing logic to be used to the pending data Carry out de interlacing processing；Wherein, the relevant information of each register needed to configure, can specifically include：

According to the length of pending image data and width in resolution register, to the resolution ratio formula of pending image data It is configured, so as to handle the image data of different resolution；Wherein, when practical application, general in-field deinterlacing logic Resolution ratio with four pending image datas of de interlacing logical requirements with motion detection is 1920*1080；

When determining de interlacing pattern is four de interlacing patterns with motion detection, it is also necessary to configure threshold value deposit The first threshold T1 and second threshold T2 of device；Wherein, under four de interlacing patterns with motion detection, the first threshold T1 and second threshold T2 is kept in motion or stationary state for judging pixel.

After the completion of incited somebody to action above-mentioned each register configuration, it is also necessary to be finally configured in enabled (enable) register The first enabled enable signal；Specifically, when described device needs to handle image data, by the of the enable registers One enable signal is configured to high level, in other words the de interlacing module of enabled image de-interlacing apparatus is gone described in startup Interlacing module；When a frame image data is disposed, and subsequently needs processing without image data, in the enable registers In other words middle configuration low level closes the de interlacing module to go to enable the de interlacing module.

When practical application, after a frame image data is disposed, and subsequently also have image data need processing when, also need It to be configured to remove the second enable signal of interrupt signal in interrupt register, and again to resolution register and threshold value Register is configured, to carry out the processing of next frame image data；Here, after a frame image procossing finishes, the dress It sets and will produce interrupt signal, it is therefore desirable to the second enable signal of the interrupt register is configured to high level, in removing Break signal, to carry out the processing of subsequent image data.

Here, it is after being completed to resolution register, de interlacing register, threshold register, interrupt register configuration Just enable registers are configured；Each register includes：Resolution register, interrupts deposit at de interlacing register Device and enable registers；Wherein, when determining de interlacing pattern is four de interlacing patterns with motion detection, institute Stating each register further includes：Threshold register.

After the completion of to above-mentioned each register configuration, by the parameter synchronization of each register of configuration to image de-interlacing apparatus De interlacing module, so as to the de interlacing module can to the pending data carry out de interlacing processing.

Specifically, when the clock in each register being synchronized the work for the de interlacing processing module by handshake Clock.

Gone more specifically, the clock synchronization request of each register is sent to the de interlacing module, and described in receiving every The clock synchronization request of row module responds, to be responded each register by clock synchronization request and clock synchronization request In configurable clock generator synchronize be the de interlacing module work clock.

In this step, when carrying out first frame image real time transfer, when the second enable signal of enable registers is in When high level state, after receiving the first frame image data, first is determined according to the resolution ratio of preconfigured resolution register The resolution ratio of frame image data, according to the corresponding de interlacing logic of not enabled de interlacing pattern to the pending image data into The processing of row de interlacing, and close the corresponding de interlacing logic of in-field deinterlacing pattern and four de interlacing moulds with motion detection The corresponding logic of formula；Alternatively, being carried out to the pending image data according to the corresponding de interlacing logic of in-field deinterlacing pattern De interlacing processing, and close the corresponding de interlacing logic of not enabled de interlacing pattern and four de interlacing moulds with motion detection The corresponding de interlacing logic of formula；Alternatively, being waited for described according to the corresponding de interlacing logic of de interlacing pattern with motion detection It handles image data and carries out de interlacing processing, and close the corresponding de interlacing logic of not enabled de interlacing pattern and in-field deinterlacing The corresponding de interlacing logic of pattern.

Wherein, it when carrying out de interlacing processing to the pending image data using corresponding de interlacing logic, also uses In by the way of ram multiplexings, de interlacing processing is carried out to the pending image data；Wherein, the ram includes：First Ram, the 2nd ram, the 3rd ram, the 4th ram；First ram, the 2nd ram, the 3rd ram and the 4th ram capacity are all 120*128；Described 120 represent the maximum memory space of ram, and described 128 indicate the bit wide of ram.

Specifically, when the de interlacing mode instruction according to reception, by the state bit instruction of the de interlacing mode register Be 00, determine the de interlacing pattern of pending image data be not enabled de interlacing pattern when, then can be automatically closed in field go every Row pattern and the corresponding de interlacing logic of four de interlacing patterns with motion detection；Here, when the image data of input is When interlaced video sequence, by the image data input channel 1 of odd field in interlaced video sequence, by the image data of even field In input channel 2；

When the image data of input is progressive scanning sequence, the image data of odd field in progressive scanning sequence is inputted It, will be in the image data input channel 2 of even field in channel 1；Wherein, the input address in the channel 1 is addr_in_1, defeated It is addr_out_1 to go out address；The input address in channel 2 is addr_in_2, output address addr_out_2；As shown in figure 4, In an initial condition, described addr_in_1, addr_in_2, addr_out_1 and addr_out_2 are 0.

Can by channel 1 and the channel 2 by the Y-component synchronism output of the image data of asynchronous input to showing dress It sets；By the UV components synchronism output of the image data of asynchronous input to display device；Wherein, when the Y of described image data points After amount and UV component synchronism outputs to display device, you can see in a display device after not enabled de interlacing logical process Image；The display device can be mobile phone, computer etc..

Here, by taking Y-component as an example, as shown in figure 5, after inputting the pending image data of a unit by channel 1, As soon as by the Y-component storage to ram of the image data of one unit, the address of the addr_in_1 adds 1, output Addr_out_1 is constant, and when not having 2 input image data of directed walk, the address of the addr_in_2 is constant, the addr_ Out_2 is also constant；Wherein, the image data of one unit includes 16 pixels.

As shown in fig. 6, when inputting the image data of a unit again by channel 1, also by the Y-component of the image data It stores into the first ram, the address of the addr_in_1 is 2, and output addr_out_1 is constant；When pass through channel 2 input one When the image data of unit, by the Y-component storage to the 3rd ram of the image data, the address of the addr_in_2 is 1, institute It is also constant to state addr_out_2；As can be seen that the input address in channel 1 is not equal to the output address in channel 1, the input in channel 2 Address is also not equal to the output address in channel 2, that is, meets (addr_in_1！=addr_out_1) ＆＆ (addr_in_2！= Addr_out_2), at this moment, described as shown in fig. 7, exporting the unit data of a Y-component simultaneously by channel 1 and channel 2 Addr_out_1 and addr_out_2 adds 1 simultaneously, in this way, completing synchronism output to the image data of asynchronous input；Wherein, The bit wide and memory space of first ram and the 3rd ram is identical, when input address addr_in_1, addr_in_2 reaches To ram the upper limit when, addr_in_1 and addr_in_2 return to 0 again.

Here, the process flow that output is synchronized to the UV components of asynchronous input is similar with the process flow of Y-component, Difference is that the UV components of pending image data in input channel 1 are stored in the 2nd ram, will be pending in input channel 2 The UV components of image data are stored in the 4th ram.

When the de interlacing mode instruction according to reception, configure the state bit instruction of the de interlacing mode register to 01, that is, determine pending image data de interlacing pattern be in-field deinterlacing pattern when, then cannot can not be automatically closed enabledly go every Row pattern and the corresponding de interlacing logic of four de interlacing patterns with motion detection；Here, the image data currently inputted For interlaced video sequence, by taking the Y-component y_1_in in vedio data as an example, by Nth row image data in the fields t of interpolation Y_1_in input channels 1 in；Wherein, the N is the integer more than or equal to 1, when N is equal to 1, is indicated the t of interpolation In in the y_1_in input channels 1 of the 1st row image data.

Here, as shown in figure 8, being one group by two pixels of the y_1_in of Nth row image data in the fields t of interpolation What format was inputted, and be temporarily stored in the first preparation register datain_r0, described first prepares register datain_r0 The pixel of y_1_in in channel 1 is spliced, until y_1_in is spliced into full 16 pixels, and splicing is 16 full The data datain of pixel is transmitted in the second preparation register datain_r1；When the bit wide of datain reaches 128, institute It states the first preparation register datain_r0 and is drawn high ram signals read_out is read, is i.e. read_out=1 is according to two pixels First group of datain of the Y-component for the N-1 row image datas that one group of format stores before reading in the first ram, and by the First group of datain of the Y-component of N-1 row image datas is exported to the first output register data_out；Wherein, the N-1 The Y-component of row image data is the lastrow image data of Nth row Y-component, and the initial address addr_ram of the first ram is 0；One group of datain includes 16 pixels.

First group of datain of the Y-component of N-1 row image datas is exported to the first output register data_out, The first preparation register datain_r0 drags down read_out, i.e. read_out=0；Ram signals write_into will be write It draws high, i.e. write_into=1, described second prepares register datain_r1 by the first of the y_1_in of Nth row image data Group datain is written in the first ram, and the addr_ram adds 1 automatically；

When the second preparation register datain_r1 writes first group of datain of the y_1_in of Nth row image data After entering in the first ram, it is also necessary to input second group of datain of the y_1_in of Nth row image data；With input Nth row picture number According to y_1_in first group of datain use identical method, when it is described first prepare register datain_r0 to Nth row figure After completing splicing as second group of datain of the y_1_in of data, by second group of datain of the y_1_in of Nth row image data It is transmitted to described second and prepares register datain_r1, then read_out is drawn high, read the y_1_in of Nth row image data First group of datain, and by first group of the Y-component of N-1 row image datas in the first output register data_out Datain is exported to the second output register data_out r；By the Y-component of N-1 row image datas in the first ram Second group of datain is exported to the first output register data_out；By first group of the y_1_in of the Nth row image data Datain is exported into the first delay time register datain_dly；

First group of datain of the y_1_in of Nth row image data is exported to the first delay time register datain_dly Afterwards, the first preparation register datain_r0 drags down read_out；Write_into is drawn high, described second prepares to post Second group of datain of the y_1_in of Nth row image data is written in the first ram storage datain_r1, the addr_ram It is automatic to add 1；

After second group of datain of the y_1_in of Nth row image data is written in the first ram, Nth row picture number is inputted According to y_1_in third group datain；With first group, the second group of datain use of the y_1_in of input Nth row image data Identical method, when the first preparation register datain_r0 is to the third group datain of the y_1_in of Nth row image data After completing splicing, the third group datain of the y_1_in of Nth row image data is transmitted to described second and prepares register Datain_r1, then read_out is drawn high, second group of datain of the y_1_in of Nth row image data is read, by N-1 rows Second group of datain of the Y-component of image data is exported to the second output register data_out r；By in the first ram The third group datain of the Y-component of N-1 row image datas is exported to the first output register data_out；By the Nth row figure As second group of datain of the y_1_in of data is exported into the first delay time register datain_dly；

Second group of datain of the y_1_in of Nth row image data is exported to the first delay time register datain_dly Afterwards, the first preparation register datain_r0 drags down read_out；Write_into is drawn high, described second prepares to post The third group datain of the y_1_in of Nth row image data is written in the first ram storage datain_r1, the addr_ram It is automatic to add 1；Wherein,

In order to ensure the Nth row image data not Jing Guo de interlacing calculation process Y-component can with through de interlacing at The Y-component energy synchronism output of Nth row image data after reason, each group of datain are also needed to by the second delay time register The delay of datain_dly0 and third delay time register datain_dly1；The first delay time register datain_dly, The delay time of two delay time register datain_dly0 and third delay time register datain_dly1 can voluntarily configure.

After reading the third group datain of the Y-component of N-1 row image datas in the first ram, to the N-1 rows of output First group of datain of the Y-component of first group of datain of the Y-component of image data and the Nth row image data of input carries out field Interior de interlacing logical operation process；Specifically, as shown in figure 9, the row average interpolation method based on edge is used first, in interpolation Point nearby carries out edge detection to the pixel of first group of datain of Y-component of Nth row image data in t, secondly by the side Two pixels on edge are averaging, using average value as interpolation result to the Y-component of Nth row image data into row interpolation；This In, edge detection can be carried out to obtain interpolation result to the matrix of the i-th row j row, the coordinate of the i-th row jth row is P (i, j)；Than Such as, parameter P value is taken as 1, i.e., doing edge detection to the matrix of 3 rows 3 row obtains interpolation result, if in t Nth row pixel Point is needed into row interpolation, then the Nth row that can be copied to the color component of nth row of pixels in t-1 in interpolation t is corresponding Pixel in；For example, if the pixel of last column in t is needed into row interpolation, it can be by last in t-1 The color component of row pixel copies in the corresponding pixel of last column in interpolation t；Here it is possible to take same Method is to the interpolation points of each row into row interpolation.

When inputting the 4th group of datain of y_1_in of Nth row image data using identical method, using above-mentioned place Reason method is read out corresponding data, is written；And using above-mentioned interlace-removing method to the N-1 row image datas of output Second group of datain of the Y-component of second group of datain of Y-component and the Nth row image data of input carries out in-field deinterlacing and patrols Calculation process is collected, until frame image data processing is completed；

After carrying out de interlacing logical operation process to image data, it is additionally operable to the picture to de interlacing treated image data Element is combined；And export the de interlacing image data after combination.

Specifically, to the first group of datain and Nth row picture number of the Y-component of the N-1 row image datas after de interlacing According to first group of datain of Y-component carry out recombination logical operation process, until having handled a frame image data；Wherein, described First group of first group of datain of the Y-component of the N-1 row image datas after de interlacing and the Y-component of Nth row image data Datain is also to be exported with the format that two pixels are one group, so needing to recombinate datain；

After completing the recombination of one group of datain, by the Y of the Nth row image data not Jing Guo de interlacing calculation process points Amount is exported from channel 2, the Y-component of the Nth row image data after recombinating logical operation process is output to from channel 1 temporary In register temp_data, so that the image data exported by channel 1 and the image data that is exported by channel 2 can be into Row synchronism output, until having exported a frame image data.

When the de interlacing mode instruction according to reception, configure the state bit instruction of the de interlacing mode register to 10, that is, it, then can be automatic when determining that the de interlacing pattern of pending image data is four de interlacing patterns with motion detection Close not enabled de interlacing pattern and the corresponding de interlacing logic of in-field deinterlacing pattern；Wherein, in four with motion detection Under the de interlacing pattern of field, Motion Adaptive method is to judge whether pixel moves by motion detection, since motion detection cannot Accurately detect out whether pixel is movement, so, in general, testing result is divided into three kinds of situations：It significantly moves, is static And it does not move significantly.When testing result is significantly movement, then field interpolation algorithm is used to carry out de interlacing to image data Processing；When testing result is static, then uses occasion and algorithm carries out de interlacing processing to image data；When testing result is When not moving significantly, then the movement of notable motion and standstill is merged according to a certain percentage and de interlacing is carried out to image data Processing.

Delta_sum=Delta_1+Delta_2+Delta_3；

The interpolation result u can be obtained using formula (1)；First threshold T1 in the threshold register and second threshold T2 can be configured according to actual conditions.

It here, will be pending in the pending image data in t-2, the pending image data in t-1, t It, will be in t-2 after pending image data in image data and t+1 is inputted by channel 1,3,2,4 respectively respectively The Y-component of the pending image data of Nth row is stored in the first ram, by the UV of the pending image data of Nth row in t-2 Component is stored in the 2nd ram, the Y-component of the pending image data of Nth row in t is stored in the 3rd ram, by t In the UV components of the pending image data of Nth row be stored in the 4th ram, according to the number under above-mentioned in-field deinterlacing pattern Image data is handled according to processing method；According to above-mentioned formula (1) (2) respectively to the N-1 row figures in t-2 and t As the Nth row image data in first group datain and t-2 and t of the Y-component of data Y-component first group of datain into Row de interlacing logical operation process, until frame image data processing is completed；Here, because need to only handle the Nth row in t-1 The pending image data of Nth row in pending image data and t+1, the N-1 rows that need not be handled in t-1 are pending The pending image data of N-1 rows in image data and t+1, so need not be stored in ram pending in t-1 Pending image data in image data and t+1；When in t-1 pending image data and t+1 in it is pending It is directly pending to the Nth row of pending image according to above-mentioned formula (1) (2) after image data is inputted from channel 3,4 respectively Image data is handled.

Specifically, by first group of datain of the Y-component of the N-1 row image datas after de interlacing and Nth row picture number According to first group of datain of Y-component be also with two pixels be that one group of format is exported, so needing to datain It is recombinated.

The Y-component of Nth row image data not Jing Guo de interlacing calculation process is exported from channel 2, logic will be recombinated The Y-component of Nth row image data after calculation process is output to from channel 1 in temporary register temp_data, so that by logical The image data that the image data that road 1 exports is exported with channel 2 can synchronize output, until having exported a frame picture number According to.

Therefore image interlace-removing method provided in an embodiment of the present invention built-in can facilitate there are many de interlacing logic User voluntarily selects de interlacing pattern according to different scenes, makes that it is suitable for more scenes.

In addition, when carrying out de interlacing processing, the method being multiplexed using ram saves the spaces ram.

It should be understood by those skilled in the art that, the embodiment of the present invention can be provided as method, system or computer program Product.Therefore, the shape of hardware embodiment, software implementation or embodiment combining software and hardware aspects can be used in the present invention Formula.Moreover, the present invention can be used can use storage in the computer that one or more wherein includes computer usable program code The form for the computer program product implemented on medium (including but not limited to magnetic disk storage and optical memory etc.).

The present invention be with reference to according to the method for the embodiment of the present invention, the flow of equipment (system) and computer program product Figure and/or block diagram describe.It should be understood that can be realized by computer program instructions every first-class in flowchart and/or the block diagram The combination of flow and/or box in journey and/or box and flowchart and/or the block diagram.These computer programs can be provided Instruct the processor of all-purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce A raw machine so that the instruction executed by computer or the processor of other programmable data processing devices is generated for real The device for the function of being specified in present one flow of flow chart or one box of multiple flows and/or block diagram or multiple boxes.

These computer program instructions, which may also be stored in, can guide computer or other programmable data processing devices with spy Determine in the computer-readable memory that mode works so that instruction generation stored in the computer readable memory includes referring to Enable the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one box of block diagram or The function of being specified in multiple boxes.

These computer program instructions also can be loaded onto a computer or other programmable data processing device so that count Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, in computer or The instruction executed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one The step of function of being specified in a box or multiple boxes.

The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention, it is all All any modification, equivalent and improvement made by within the spirit and principles in the present invention etc. should be included in the protection of the present invention Within the scope of.

Claims

1. a kind of image de-interlacing apparatus, which is characterized in that described device includes：Configuration module and de interlacing module；Wherein,

The configuration module determines the de interlacing pattern of pending image data for the de interlacing mode instruction according to reception；

The configuration module is additionally operable to length and width according to pending image data, to pending figure in resolution register As the resolution ratio of data is configured；And it is configured to enable the first enabled letter of the de interlacing module in enabled register Number；

The de interlacing module, the corresponding de interlacing logic of de interlacing pattern for being determined using configuration module wait locating to described It manages image data and carries out de interlacing processing, and close other in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination De interlacing logic.

2. the apparatus according to claim 1, which is characterized in that the configuration module is specifically used for：According to reception go every Row mode instruction, the instruction that de interlacing register is carried out to corresponding de interlacing pattern configure；

Correspondingly, the de interlacing module, for being configured according to the instruction of the de interlacing register, using corresponding de interlacing Logic carries out de interlacing processing to the pending image data, and close gone except the de interlacing pattern of the determination is corresponding every Other de interlacing logics outside row logic.

3. the apparatus according to claim 1, which is characterized in that the configuration module is additionally operable to when determining de interlacing mould When the corresponding de interlacing logic of formula is four de interlacing logics with motion detection, it is configured to enable in enabled register Before first enable signal of the de interlacing module, first threshold and second threshold are configured in threshold register；It is described First threshold and second threshold are for judging that pixel is to be kept in motion or stationary state.

4. device according to claim 1 or 3, which is characterized in that the configuration module is additionally operable to when a frame image data When being disposed, and subsequently also having image data to need processing, it is configured to remove the of interrupt signal in interrupt register Two enable signals, and resolution register being configured again, or again to resolution register and threshold register into Row configuration.

5. device according to claim 4, which is characterized in that described device further includes：Top-level module and synchronization module； Wherein,

The synchronization module, the parameter synchronization of each register for configuring the configuration module to the de interlacing module.

6. device according to claim 5, which is characterized in that the synchronization module is specifically used for：By each register when Clock synchronizes the work clock for the de interlacing module by handshake.

7. the apparatus according to claim 1, which is characterized in that the de interlacing module is additionally operable to the side using ram multiplexings Formula carries out de interlacing processing to the pending image data.

8. device according to claim 7, which is characterized in that it is described by the way of ram multiplexings, to the pending figure As data progress de interlacing processing, including：

Under not enabled de interlacing pattern, ram for storing pending data so that the data of asynchronous input synchronize it is defeated Go out；

Inside under de interlacing pattern or four de interlacing patterns with motion detection, the ram, for storing pending figure As the Nth row image data in data and the N-1 row image datas in pending image data, so that de interlacing mould inside The corresponding de interlacing logic of formula or the corresponding de interlacing logic of four de interlacing patterns with motion detection are to described pending Image data carries out corresponding de interlacing processing.

9. a kind of image interlace-removing method, which is characterized in that the method includes：

According to the length and width of pending image data, the resolution ratio of pending image data is matched in resolution register It sets；And it is configured to enable the first enable signal of the de interlacing module in enabled register

De interlacing processing is carried out to the pending image data using the determining corresponding de interlacing logic of de interlacing pattern, and Close other de interlacing logics in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination.

10. according to the method described in claim 9, it is characterized in that, the de interlacing mode instruction according to reception, determination wait for The de interlacing pattern of image data is handled, including：

According to the de interlacing mode instruction of reception, the instruction that de interlacing register is carried out to corresponding de interlacing pattern is configured, is determined The de interlacing pattern of pending image data；

Correspondingly, it is configured according to the instruction of the de interlacing register, using corresponding de interlacing logic to the pending figure As data carry out de interlacing processing, and close other in addition to the corresponding de interlacing logic of the de interlacing pattern of the determination go every Row logic.

11. according to the method described in claim 9, it is characterized in that, when the determining corresponding de interlacing logic of de interlacing pattern For four de interlacing logics with motion detection when, be configured to enable the of the de interlacing module in enabled register Before one enable signal, the method further includes：

First threshold and second threshold are configured in threshold register；The first threshold and second threshold are for judging picture Element is to be kept in motion or stationary state.

12. the method according to claim 9 or 11, which is characterized in that when a frame image data is disposed, and it is follow-up also When having image data to need processing, the method further includes：

It is configured to remove the second enable signal of interrupt signal in interrupt register, and resolution register is carried out again Configuration, or resolution register and threshold register are configured again.

13. according to the method for claim 12, which is characterized in that configure each register, and the determination go every The corresponding de interlacing logic of row pattern carries out de interlacing processing to the pending image data, and closes and gone except the determination Before other de interlacing logics outside the corresponding de interlacing logic of interlaced mode, the method further includes：

14. according to the method for claim 13, which is characterized in that the parameter synchronization of each register by configuration is to going Interlacing processing device de interlacing module, be：

15. according to the method described in claim 9, it is characterized in that, when carrying out de interlacing processing to the pending image, The method further includes：By the way of ram multiplexings, de interlacing processing is carried out to the pending image data.

16. according to the method for claim 15, which is characterized in that it is described by the way of ram multiplexings, to described pending Image data carries out de interlacing processing, including：