CN104956489B - Semiconductor device, integrated circuit and the method for forming semiconductor device - Google Patents

Semiconductor device, integrated circuit and the method for forming semiconductor device Download PDF

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Publication number
CN104956489B
CN104956489B CN201380072129.7A CN201380072129A CN104956489B CN 104956489 B CN104956489 B CN 104956489B CN 201380072129 A CN201380072129 A CN 201380072129A CN 104956489 B CN104956489 B CN 104956489B
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Prior art keywords
main surface
source
contact
region
drain
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CN201380072129.7A
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CN104956489A (en
Inventor
A.迈泽
R.魏斯
F.希尔勒
M.韦莱迈尔
M.聪德尔
P.伊尔西格勒
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Infineon Technologies AG
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Infineon Technologies AG
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Priority claimed from US13/692,059 external-priority patent/US9799762B2/en
Priority claimed from US14/082,491 external-priority patent/US9735243B2/en
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Publication of CN104956489A publication Critical patent/CN104956489A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention relates to semiconductor device, integrated circuit and the method for forming semiconductor device.A kind of semiconductor device includes the transistor formed in the semiconductor body with the first main surface.The transistor includes：Source region；Drain region；Channel region；Drift region；Source contact, electronically it is connected to source region；Drain contact, electronically it is connected to drain region；And gate electrode, positioned at channel region.Channel region and drift region are arranged between source region and drain region along a first direction, and first direction is parallel to the first main surface.Channel region has the shape of the first ridge extended along a first direction.One of source contact and drain contact are adjacent with the first main surface, and another in source contact and drain contact is adjacent with the second main surface, and the second main surface is relative with the first main surface.

Description

Semiconductor device, integrated circuit and the method for forming semiconductor device
Background technology
The power transistor usually used in automobile and industrial electronic needs low on-state resistance (Ron), ensure simultaneously High pressure blocking ability.For example, according to application requirement, MOS (" metal-oxide semiconductor (MOS) ") power transistor should be able to block The drain electrode of tens to hundreds of or several kilovolts is to source voltage Vds.The MOS power transistors generally very big electric current of conduction, the electricity Stream can be up to hundreds of amperes in about 2 to 20 V typical gates-source voltage.
The lateral direction power device that electric current is predominantly parallel to the main surface of semiconductor base and occurred, which helps to integrate, such as to be opened The integrated circuit of the other part of pass, bridge and control circuit.
For example, power transistor can be used for DC/DC or AC/DC converters with by inductor switching electric current.At these In converter, using from the frequency in scopes of several kHz up to several MHz.In order to reduce switch cost, it is try to make power brilliant Electric capacity in body pipe minimizes.This allows for the switching capability accelerated.
In higher electric current, when source region and drain region will be from the first major surface contacts, due to contacting source electrode Region and the limited possibility of drain region, in fact it could happen that problem.For these reasons, it is try to provide a kind of accurate vertical half Conductor device.
It is an object of the invention to provide a kind of quasi- vertical semiconductor device with increased performance.Another object is A kind of method for manufacturing this device is provided.
The content of the invention
According to embodiment, a kind of semiconductor device includes the crystal being located in the semiconductor body with the first main surface Pipe.The transistor includes：Source region；Drain region；Channel region；Drift region；Source contact, electronically it is connected to source Polar region domain；Drain contact, electronically it is connected to drain region；Gate electrode, positioned at channel region, channel region and drift region It is arranged on along a first direction between source region and drain region, first direction is parallel to the first main surface, channel region Shape with the first ridge extended along a first direction.One of source contact and drain contact are adjacent with the first main surface, source Another in pole contact and drain contact is adjacent with the second main surface, and the second main surface is relative with the first main surface.
According to another embodiment, a kind of integrated circuit includes respectively being located in the semiconductor body with the first main surface First and second transistors.Each in first and second transistors includes：Source region；Drain region；Channel region；Drift Move area；Source contact, electronically it is connected to source region；Drain contact, electronically it is connected to drain region；Grid electricity Pole, positioned at channel region.Channel region and drift region are arranged between source region and drain region along a first direction.The One is oriented parallel to the first main surface.Channel region has the shape of the first ridge extended along a first direction.The first transistor Source contact and one of drain contact it is adjacent with the first main surface, it is another in the source contact and drain contact of the first transistor One adjacent with the second main surface, and the second main surface is relative with the first main surface.
According to embodiment, a kind of method for manufacturing semiconductor device includes：In the semiconductor body with the first main surface Middle formation transistor.This method includes：Form the source region and drain region adjacent with the first main surface；Formed and the first master The adjacent channel region in surface and drift region；Form gate electrode between source electrode and drain region, form gate electrode and be included in the Gate trench is formed in one main surface；And the contact openings that the second main surface is extended to from the first main surface are formed, the second master Surface is relative with the first main surface.
Those skilled in the art will recognize other when reading following detailed description and when watching accompanying drawing Feature and advantage.
Brief description of the drawings
Embodiments of the invention are further understood with providing including accompanying drawing, and accompanying drawing is comprised in this specification And form the part of this specification.Accompanying drawing illustrates embodiments of the invention and is used to explain principle together with the description.Will Other embodiments of the invention and many expected advantages are would readily recognize that, because they become by referring to following detailed description It must be best understood from.The element of accompanying drawing may not be drawn to scale relative to each other.Same reference numerals specify corresponding similar portions.
Figure 1A shows the plan of the semiconductor device according to embodiment；
Figure 1B shows the sectional view of the semiconductor device according to embodiment；
Fig. 1 C show the sectional view of the semiconductor device according to another embodiment；
Fig. 1 D show the sectional view vertically obtained respectively about the sectional view shown in Figure 1B or 1C；With
Fig. 1 E show the different sectional views vertically obtained respectively about the sectional view shown in Figure 1B and 1C.
Fig. 2A shows the embodiment of the integrated circuit according to embodiment；
Fig. 2 B show the sectional view of the integrated circuit according to another embodiment；
Fig. 2 C show the sectional view of the integrated circuit according to embodiment；
Fig. 3 A show the sectional view of the semiconductor device according to embodiment；
Fig. 3 B show the sectional view of the semiconductor device according to embodiment；
Fig. 3 C show the sectional view of the semiconductor device according to embodiment；
Fig. 4 illustrates the flow chart of the method for the formation semiconductor device according to embodiment.
Fig. 5 A show the sectional view of the semiconductor device according to embodiment；
Fig. 5 B show the sectional view of the semiconductor device according to another embodiment；
Fig. 5 C are the flow charts according to the method for the formation semiconductor device of embodiment.
Fig. 6 A to 6C show the plan of the semiconductor device according to embodiment；
Fig. 7 A to 7D show cuing open for the semiconductor device when performing the method according to the manufacture semiconductor device of embodiment View；With
Semiconductor device of Fig. 8 A to 8D diagrams when performing the method according to the manufacture semiconductor device of embodiment cuts open View.
Embodiment
In the following detailed description, referring to the drawings, accompanying drawing forms a part for the detailed description and made in the accompanying drawings To illustrate that diagram can implement the particular embodiment of the present invention.In terms of this, with reference to the orientation user of the accompanying drawing described To term, " top ", " bottom ", "front", "rear", " leading ", " backwardness " etc..Because the part of embodiments of the invention being capable of position In many different azimuths, so direction term is used for the purpose of explanation and is by no means limitative.It should be understood that do not departing from In the case of the scope being defined by the claims, other embodiments can be used and structure or logical changes can be realized.
Description to embodiment is not restricted.Especially, the element of embodiment described below can by from different realities Apply the element combination of example.
The term " chip ", " substrate " or " semiconductor base " used in the following description can include it is any have partly lead Body surface face based on semiconductor structure.Chip and structure should be understood that comprising silicon, silicon-on-insulator (SOI), sapphire Upper silicon (SOS), the epitaxial layer of doping and the silicon supported undoped with semiconductor, by base semiconductor foundation and other semiconductor junctions Structure.Semiconductor is not needed upon silicon.Semiconductor also can be SiGe, germanium or GaAs.According to other embodiments, carborundum (SiC) or gallium nitride (GaN) can form semiconductor base materials.
Term " semiconductor body " can include any example in the above-mentioned example of substrate.Specifically, this term can Semiconductor layer is represented, especially, single-crystal semiconductor layer can be represented, in single-crystal semiconductor layer, the portion of semiconductor device can be manufactured Part.For example, term " semiconductor body " can represent a part for hierarchy or a part for SOI substrate.
Term " transverse direction " as used in this description and " level " are intended to description and led parallel to semiconductor base or partly The orientation of the first surface of phosphor bodies.This can be the surface of such as chip or tube core.
Term " vertical " as used in this description is intended to description and is arranged perpendicularly to semiconductor base or semiconductor The orientation of the first surface of main body.
As used herein, term " having ", " containing ", "comprising", " comprising " etc. are open-ended terms, described open The element of term instruction statement or the presence of feature, but it is not excluded for other element or feature.Article " one ", "one" and "the" It is intended to include plural number and odd number, unless the context clearly dictates otherwise.
As employed in this specification, term " coupling " and/or " electronically coupling " are not intended to mean that element must Must be directly coupled together-intermediary element may be provided between the element of " coupling " or " electronically couple ".Term " with Electrically connect " it is intended to the low ohm electrical connection between the element that description electronically links together.
Accompanying drawing and description after doping type " n " or " p " by indicating that "-" or "+" illustrate relative doping concentration. For example, " n-" the expression doping concentration lower than the doping concentration of " n " doped region, and " n+" doped region have than " n " doped region The high doping concentration in domain.The doped region of identical relative doping concentration may not have identical absolute doping concentration.For example, two not There can be identical or different absolute doping concentration with " n " doped region.In the accompanying drawings and the description, for the sake of being better understood from, Doped portion is through being often specified to " p " or " n " doping.It is clearly understood that, this specified be never intended to is restricted.Mix Miscellany type can be arbitrary, as long as realizing the function of description.In addition, in all embodiments, doping type can run .
This specification mentions " first " and " second " conductivity type for the dopant that semiconductor portions are doped.First conductivity type Can be p-type, and the second conductivity type can be n-type, and vice versa.As is generally known, mixing according to source electrode and drain region Miscellany type or polarity, MOSFET can be n-channel or p-channel MOSFET.For example, in n-channel MOSFET, source electrode and drain region Domain is doped with n-type dopant, and the sense of current is from drain region to source region.In p-channel MOSFET, source electrode and leakage Polar region domain is doped with p-type dopant, and the sense of current is from source region to drain region.It is clearly understood that, at this In the context of specification, doping type can overturn.If use direction language describes specific currents path, this description should This is considered only as the polarity for indicating path rather than electric current, i.e. transistor is p-channel or n-channel transistor.Accompanying drawing can include Polar sensitive part, such as diode.It is clearly understood that, provides the described specific of these polar sensitive parts as an example Arrangement, and the specific arrangements of these polar sensitive parts can be represented according to the first conductivity type n-type or represent p-type and Inverted to realize the function of description.
Figure 1A shows the plan of the semiconductor device according to embodiment, and Figure 1B and 1C are shown between I and I' and obtained The sectional view of the semiconductor device obtained.
The semiconductor device shown in Fig. 1 includes multiple transistor primitives, and transistor primitive includes source region 201, leakage Polar region domain 205, channel region 220 and drift region 260.Transistor primitive is connected in parallel, to cause source region 201 and leakage Polar region domain 205 can form a single region.Source region 201, drain region 205 and drift region 260 can have the first conduction Type, and can be doped with the dopant of the first conductivity type, for example, n-type dopant.Source electrode and the doping of drain region 201,205 Concentration can be higher than the doping concentration of drift region 260.Channel region 220 is disposed between source region 201 and drift region 260. Channel region 220 has the second conductivity type, and doped with the dopant of the second conductivity type, for example, p-type dopant.Drift region 260 can be disposed between channel region 220 and drain region 205.Source region 201, channel region 220, the and of drift region 260 Drain region 205 is set along a first direction.First direction prolongs parallel to the first main surface of semiconductor body or substrate from I Reach I'.
When suitable voltage is applied to gate electrode 210, the electrical conductivity of the raceway groove formed in channel region 220 will be by Grid voltage controls.Gate electrode 210 is insulated by the insulated gate electrode dielectric material 201 of such as silica with channel region 220. The electrical conductivity of the raceway groove formed by controlling in channel region, it can control the raceway groove through being formed in channel region 220 and drift region 260 electric current from source region 201 to drain region 205.Transistor 200 may also include field plate 250, and field plate 250 is arranged to It is adjacent with drift region 260.Field plate 250 is insulated by the insulation field dielectric layer 251 of such as field oxide with drift region 260.
Source region 201 is connected to source electrode 202.Drain region 205 is connected to drain electrode 206.
When on, inversion layer is formed on the border between channel region 220 and insulated gate electrode dielectric material 211.Cause This, transistor is in through conduction state of the drift region 260 from source region 201 to drain region 205.When the transistor turns off, There is no the border that conducting channel is formed between channel region 220 and insulated gate electrode dielectric material 211, to cause no electric current Flowing.In addition, suitable voltage can be applied to field plate 250 in the off state.In the off state, field plate is exhausted from drift The electric charge carrier in area is moved, to improve the breakdown voltage characteristics of transistor 200.Compared with the device of no field plate, wrapping In the semiconductor device for including field plate, the doping concentration of drift region can be increased without reducing breakdown voltage characteristics.Due to drift region Higher doping concentration, further reduce and connect resistance Rdson, cause the equipment energy characteristic improved.
The example of the sectional view of graphic semiconductor device in Figure 1A between Figure 1B and 1C displays I and I'.Between I and I' Direction correspond to first direction.As shown in FIG., depth direction of the source region 201 along main body 100 is (that is, relative to first Main surface 110 is vertical) extend from the first main surface 110.Channel region 220 and drift region 260 are arranged on along a first direction Between source region 201 and drain region 205, first direction is parallel to the first main surface 110.
Drain region 205 similarly extends along the depth direction of main body from the first main surface 110.Drain region 205 can be by The conductive layer for forming drain electrode 206 is implemented.Alternatively, drain region 205 may include the doped region of the first conductivity type.Such as dotted line Indicated, in the plane before and after the plane of the accompanying drawing of description, gate trench 212 is arranged to and channel region 220 It is adjacent.With corresponded manner, field-plate trench 252 can be arranged to adjacent with drift region 260.Gate trench 212 and field-plate trench 252 Extend along the depth direction of main body from the first main surface 110.Therefore, channel region 220 has the shape of the first ridge.Due to field plate The presence of groove 252, drift region 260 also have the shape of the second ridge.
Figure 1B and 1C semiconductor device also includes front side metallization 270, and front side metallization 270 passes through front side dielectric 265 insulate with the first main surface 110.The semiconductor device also includes back-side metallization 275, and back-side metallization 275 passes through the back of the body Side dielectric 280 insulate with the second main surface 120.
Figure 1B also shows body contact region 225, body contact region 225 be arranged on the lower section of body region 220 and It is arranged on the part lower section of drift region 260.Channel region is connected to source by main contact section 225 through contact portion 226 To avoid parasitic bipolar transistor, parasitic bipolar transistor can be formed in this part originally for pole contact.Alternatively, main body connects Contact portion point 225 can extend below drift region 260, and to cause under the off-state of transistor, drift region 260 can be easier Ground exhausts.
As being further illustrated in Figure 1B, source region 201 and source electrode 202 can be through conductive plugs 208 and source contact 267 It is connected to front side metallization 720.In addition, the drain region 205 comprising drain electrode 206 can be led through conductive plug 207 and with second The adjacent drain contact 277 in surface 120 is connected to back-side metallization 275, and the second main surface 120 is relative with the first main surface 110.
According to Fig. 1 C embodiment, source region 201 and source electrode 202 can through conductive plug 208 and with the second main surface Adjacent source contact 267 is connected to back-side metallization 275.Drain region 205 comprising drain electrode 206 can be through conductive plug 207 and the drain contact 277 adjacent with the first main surface 110 of semiconductor body be connected with frontside metal 270.
Therefore, Figure 1A semiconductor devices as graphic semiconductor device implementation into 1C：The semiconductor device includes Form the transistor 200 in the semiconductor body 100 with the first main surface 110.The transistor include source region 201, Drain region 206, channel region 220, drift region 260, the source contact 267 for being connected to source region, it is connected to drain region 206 drain contact 277 and the gate electrode 210 positioned at channel region 220.Channel region 220 and drift region 260 are by along first Direction is arranged between source region 201 and drain region 206.First direction is parallel to the first main surface 110, and channel region Domain 220 has the shape of the ridge extended along a first direction.One of source contact and drain contact and the first main phase of surface 110 Neighbour, another, second main surface 120 and first adjacent with the second main surface 120 in source contact 267 and drain contact 277 Main surface 110 is relative.
The semiconductor device implements quasi- Vertical power transistors, in the quasi- Vertical power transistors, by applied to grid The voltage of electrode flows (that is, parallel to the first main surface of semiconductor body) in transverse direction come the electric current controlled.In addition, source Pole contacts and one of drain contact is arranged on the first main surface, and another in source contact and drain contact is set On the second main surface.Therefore, the electric current obtained vertically flows.
The substrate or the section view of main body obtained between the II and II' and III and III' of Fig. 1 D and 1E diagram in figure ia Figure.Direction between II and II' and between III and III' is perpendicular to first direction.As shown in Figure 1 D, channel region 220 Shape with ridge, the ridge have width d1With depth or height t1.For example, the ridge can have top side 220a and two side walls 220b.Side wall 220b can vertically extend relative to the first main surface 110 or extend according to the angle more than 75 °.Gate electrode 210 It can be arranged to adjacent with least both sides of the ridge.
In addition, in sectional view between III and III', drift region 260 can also have the shape of the second ridge, the second ridge tool There is width d2With depth or height t2.For example, the second ridge can have top side 260a and two side wall 260b.Side wall 260b can be relative Vertically extend in the first main surface 110 or extend according to the angle more than 75 °.Field plate 260 can be arranged to and top side 260a Adjacent or with the ridge at least both sides are adjacent.
Below channel region and alternatively below drift region, deep main contact section 225 can be set, such as above institute Explain.
According to embodiment, the width d of channel region 2201It is d1 ≤ 2·ld, wherein ldRepresent to be formed in gate dielectric The length of the depletion region at the interface between 211 and channel region 220.For example, the width of depletion region can be confirmed as：
Wherein εSRepresent the dielectric constant of semi-conducting material (for silicon, 11.9 x ε0, ε0 = 8.85 x 10-14 F/ Cm), k represents Boltzmann constant (1.38066 x 10-23J/K), T represents temperature, and ln represents natural logrithm, NAExpression is partly led The impurity concentration of phosphor bodies, niRepresent intrinsic carrier concentration (at 27 DEG C, for silicon, 1.45 x 1010 cm-3), and q is represented Elementary charge (1.6 x 10-19 C)。
In general it is assumed that：In the transistor, consumption is corresponded in the length of the depletion region of grid voltage corresponding with threshold voltage The Breadth Maximum in area to the greatest extent.For example, along the first main surface 110 of semiconductor body 100, the width of first groove can be about 20 to 130 nm, such as 40 to 120 nm.
In addition, the ratio between length and width can meet lower relation of plane：s1/d1>2.0, wherein S1Represent along a first direction The length of the ridge of measurement, also as illustrated in fig. 1A.According to further embodiment, s1/d1> 2.5.As shown in figures 1D and 1E, The width d of channel region 2201It may differ from the width d of drift region 2602.According to another embodiment, drift region 260 may include to put down Smooth surface, the flat surfaces are not patterned to form ridge, as shown in Figure 1 D.
According to width d1 ≤ 2·ldEmbodiment, transistor 200 is so-called " fully- depleted " transistor, brilliant in fully- depleted In body pipe, when gate electrode is arranged to connect potential, channel region 220 is by fully- depleted.In such a transistor, can realize Optimal sub- threshold voltage, and can effectively suppress short-channel effect, cause the equipment energy characteristic improved.
On the other hand, in the transistor including field plate, it is desirable to use there is width d2Drift region 260, width d2Than wide Spend d1It is much bigger.Due to drift region d2Larger width, the resistance Rds of drift regiononAnd therefore the resistance Rdson of transistor can Further reduce, cause the equipment energy characteristic further improved.In order to improve the characteristic of the semiconductor device in channel region and The equipment energy characteristic in drift region is further improved, implements the patterning of gate electrode and field plate to provide the difference of the first and second ridges Width.
As reference picture 1B and 1C are discussed further, the depth direction extension of source electrode and drain region 201,205 along main body. Therefore, by suitably setting the depth of source electrode and drain region 201,205, the electrical resistance of transistor can be set as requested Matter.Due to special other feature, i.e. gate electrode 210 and field plate 250 is adjacent to edge with channel region 220 and drift region 260 Depth direction extends, and can pass through the full depth t along channel region 2201Gate electrode to be formed to control in channel region 220 In raceway groove electrical conductivity.With corresponded manner, field plate 250 influences the depth t along the second ridge2Drift region behavior.Therefore, The depth of source region and drain region determines the effective width of transistor., can by setting the depth of source electrode and drain region Determine the width of the device and it is thus determined that the characteristic of the device.For example, the depth of source electrode and drain region can be more than 1 μm.
Fig. 2A, 2B and 2C illustrate the example of the integrated circuit according to embodiment.According to these embodiments, integrated circuit can wrap Include multiple semiconductor devices as defined above.For example, Fig. 2A diagrams include the first transistor 3001 and second transistor 3002 integrated circuit.Each in first and second transistors 3001,3002 consists essentially of graphic part in Fig. 1. Transistor 3001,3002 includes source region 301, drain region 305, channel region 320 and drift region 360.With in such as Fig. 1 The gate electrode 310 of the special construction discussed is arranged on channel region 320.The transistor may also include field plate 350, field plate 350 may be disposed at drift region 360.Gate electrode 310 is insulated by gate-dielectric 311 with channel region 320, and field plate 350 are insulated by field dielectric layer 351 with drift region 360.It is coupled to the first conductive plug through source electrode 302 in source region 301 308.Drain region 305 can be implemented as being formed the conductive layer of drain electrode 306.Alternatively, drain region 305 may include that first leads The doped region of electric type.
As illustrated in Fig. 2A, the first transistor 3001 may include the first source contact 3671, the first source contact 3671 It is adjacent with the second main surface 120 of semiconductor body 100.In addition, the first transistor 3001 includes the first drain contact 3771, the One drain contact 3771 is arranged on the first main surface 110.First source contact 3671 is connected to the source of the first transistor 3001 Polar region domain 301, and the first drain contact is connected to the drain region 305 of the first transistor 3001.
Second transistor 3002 is included substantially with the identical part of the first transistor 3001, is retouched in detail so as to omit it State.Second transistor 3002 be formed on in the identical semiconductor body 100 of the first transistor 3001.Second transistor 3002 Insulated by isolation structure 390 with the first transistor 3001.For example, isolation structure 390 may include insulating materials and optional Ground includes conductive filler 391, conductive filler 391 and adjacent semiconductor insulated with material.For example, shape in the semiconductor body can be passed through Each insulation and conductive material are formed into groove and in this groove to form isolation structure 390.For example, define isolation structure 390 groove can be formed simultaneously by the groove with defining field-plate trench 352 or gate electrode groove 312.
Second source contact 3672 is electronically connected to the source region 302 of second transistor 3002.For example, second Source contact 3672 may be disposed at the first main surface 110 of semiconductor body 100.In addition, the second drain contact 3772 connects To the drain region 305 of second transistor 3002.Second drain contact 3772 may be disposed at the second master of semiconductor body 100 Surface 120.The integrated circuit shown in Fig. 2A also includes front side dielectric material 365 and front side metallization.For example, front side metallization It may include front side drain metallization 3701 and front side source metallization 3702.In addition, the integrated circuit may include back-side metallization 375, back-side metallization 375 connects with the source region 301 of the first transistor 3001 and the drain region 306 of second transistor 3002 Connect.Back-side metallization 375 can by dorsal part dielectric layer 380 come with the second of semiconductor body 100 the main surface insulation.
For example, front side metallization layer 3701 can be connected with VS (" supply voltage ") potential.In addition, front side metallization layer 3702 It can be connected with ground voltage.In addition, back-side metallization 375 can be connected with phase terminal.For example, bipolar load (such as, motor) can connect It is connected to the phase.In this configuration, the motor can be provided that forward and reverse electric current.Therefore, the integrated circuit shown in Fig. 2A Realize the half-bridge switch being integrally formed that can be used for such as buck converter.
Fig. 2A specific interconnected scheme is provided as an example.According to further embodiment, the first source contact 3671 and Two source contacts 3672 can be adjacent with the first main surface 110 of semiconductor body, and the first drain contact 3771 and the second leakage Pole contact 3772 can be adjacent with the second main surface 120 of semiconductor body, and vice versa.First and second source contacts 3671, 3672 can be electrically connected to public metallization, and can therefore be connected to each other.First drain contact 3771 and the second leakage Pole contact 3772 can be electrically connected to different terminals.Alternatively, the first drain contact 3771 and the second drain contact 3772 can be electrically connected to public metallization, and can therefore be connected to each other.In this case, the first source contact 3671 and second source contact 3672 can be electrically connected to different terminals.According to these embodiments, the integrated circuit can Implement reverse blocking switch.
Fig. 2 B show the modification of Fig. 2A embodiment.Fig. 2 B integrated circuit includes the portion similar with Fig. 2A embodiment Part.Different from Fig. 2A embodiment, each in the first and second transistors 3002 includes extending to from the first main surface 110 The contact openings 304 on the second main surface 120.The contact openings are filled with conductive material to form the first source contact 3671 and the Two drain contacts 3772.The is formed by using the contact openings 304 that the second main surface 120 is extended to from the first main surface 110 One source contact 3671 and/or the second drain contact 3772, the manufacture method can be further simplified.Insulating barrier 380 is set To be adjacent with the second main surface 120, and the part of the integrated circuit is set to be electrically insulated from each other.Contact openings 304 are also formed at In insulating barrier 380.The integrated circuit may also include doping semiconductor layer 135, and doping semiconductor layer 135 is arranged on insulating barrier Between 380 and back-side metallization layer 375.According to embodiment, the doping semiconductor layer can have the first conductivity type.For example, half Conductor main body 100, insulating barrier 380 and doping semiconductor layer 135 can form a part for SOI substrate.
Fig. 2 C show the sectional view of the integrated circuit according to another embodiment.According to the embodiment shown in Fig. 2 C, first It is formed on second transistor 3001,3002 in single semiconductor body 100.The first transistor 3001 includes the first source area Domain 3010, the first drain region 3050, first gate electrode 3100, and alternatively include the first field plate 3500.Transistor 3001 Also include the first channel region 3201 and the first drift region 3601.
Fig. 2 C are the conceptual illustrations of integrated circuit, wherein schematically illustrating each part without indicating the accurate of these parts Position.In the integrated circuit shown in fig. 2 c, the first source contact 3671 is arranged on the first main surface of semiconductor body 110, and the first drain contact 3771 is arranged on the second main surface 120 of semiconductor body 100.Similarly, the second crystal Pipe 3002 includes the first source region 3010, the second drain region 3050, second gate electrode 3100 adjacent with the second gate electrode With the second drift region 3602 that can be adjacent with field plate 3500.First source contact 3672 is arranged on the first master of semiconductor body Surface 110, and the second drain contact 3772 is arranged on the second main surface 120 of semiconductor body 100.It is it will be clear that geographical Solution, the integrated circuit may include multiple other transistors with same configuration.Frontside metal 370 is arranged on semiconductor master The part on the first main surface 110 of body 100.Frontside metal 370 is by front side dielectric layer 365 come exhausted with semiconductor body 100 Edge.In addition, the heavy doping main part 130 of the second conductivity type can be arranged to the second main surface 120 with semiconductor body 100 It is adjacent.The main part of first and second transistors 3001,3002 can be insulated by insulation system 390.First back side metal Part 3751 may be disposed at a part for the first transistor 3001, and the second back side metal part 3752 may be disposed at A part for two-transistor 3002.In addition, the first lead frame 395 can be arranged to adjacent with the first back side metal 3751, and And second lead frame 3096 can be arranged to adjacent with the second back side metal 3752.For example, the first and second lead frames can It is connected to different potentials.For example, the second lead frame 396 may be connected to earth potential, and the first lead frame 395 is connected to VbbOr Vs.Using the structure, several half-bridges can integrally be integrated with formed half-bridge, full-bridge, for different types of motor (such as, Such as BLDC (" brushless DC ") motor or stepper motor) drive circuit.
Another embodiment is related to a kind of half-bridge circuit, and the half-bridge circuit includes integrated circuit, and the integrated circuit includes difference Form the first and second transistors in the semiconductor body with the first main surface, it is each in the first and second transistors It is individual including：Source region；Drain region；Channel region；Drift region；Source contact, electronically it is connected to source region；Leakage Pole contacts, and is electronically connected to drain region；Gate electrode, positioned at channel region, channel region and drift region are by along One direction is arranged between source region and drain region, first direction parallel to the first main surface, channel region have along The shape of first ridge of first direction extension, one of the source contact of the first transistor and drain contact and the first main surface phase Neighbour, another, second main surface and first adjacent with the second main surface in the source contact and drain contact of the first transistor Main surface is relative.The source contact of the first transistor and the drain contact of second transistor are adjacent with the first main surface, and the The drain contact of one transistor and the source contact of second transistor are adjacent with the second main surface, and vice versa.According to embodiment, The source contact of the first transistor and the drain contact of second transistor are electronically connected with a terminal.According to this reality Example is applied, the drain contact of the first transistor and the source contact of second transistor are connected to different terminals.
Another embodiment is related to a kind of bridge circuit, the bridge circuit include it is several connect in a suitable manner as described above half Bridge circuit.
There is another embodiment to be related to a kind of reverse blocking circuit again, the reverse blocking circuit includes integrated circuit, and this is integrated Circuit includes the first and second transistors being respectively formed in the semiconductor body with the first main surface, and first and second is brilliant Each in body pipe includes：Source region；Drain region；Channel region；Drift region；Source contact, electronically connect To source region；Drain contact, electronically it is connected to drain region；Gate electrode, positioned at channel region, channel region and drift Move area to be arranged between source region and drain region along a first direction, first direction is parallel to the first main surface, raceway groove Region has the shape of the first ridge extended along a first direction, one of the source contact of the first transistor and drain contact and the One main surface is adjacent, and another in the source contact and drain contact of the first transistor is adjacent with the second main surface, the second master Surface is relative with the first main surface.The source contact of the first transistor and the source contact of second transistor and the first main surface phase Neighbour, and the drain contact of the first transistor and the drain contact of second transistor are adjacent with the second main surface, and vice versa.Root According to embodiment, the source contact of the first transistor and the source contact of second transistor electronically connect with a terminal Connect.According to this embodiment, the drain contact of the first transistor and the drain contact of second transistor are connected to different terminals. According to another embodiment, the drain contact of the first transistor and the drain contact of second transistor are electronically held with one Son connection.According to this embodiment, the source contact of the first transistor and the source contact of second transistor are connected to difference Terminal.
Generally, SOI (" silicon-on-insulator ") substrates can be used to be formed as starting material to be filled according to the semiconductor of embodiment Put.It after forming the part of the transistor in the first main surface, can make the substrate thinning from dorsal part, thus expose embedment insulation Body layer.Therefore, a part for base material can be removed from dorsal part.Thereafter, source contact or drain contact can be formed with half Second main surface of conductor substrate is adjacent.Alternatively, it can could be used without being embedded to the substrate or main body of oxide skin(coating).In such case Under, after making chip thinning, the dorsal part of chip can be oxidized to form dorsal part dielectric layer.Then, with main body can be formed The adjacent source contact in two main surfaces or drain contact.Alternatively, groove as being formed before making chip thinning：At this In groove, the source contact adjacent with the second main surface or drain contact will be being formed later.For example, plasma can be used to cut Piece method forms groove to realize high the ratio of width to height.According to there is another embodiment again, the thinning feelings of semiconductor body can not made The semiconductor device is formed under condition.For example, it can be formed from the first master for forming the opening of source contact or drain contact Surface extends to the second main surface.
Below, it will the example of structure is shown, while mentions the different disposal of the backside contact for forming transistor. Backside contact is usually mentioned, and not yet explicitly determines source contact or drain contact and implements the backside contact.Will be clear Understand to Chu, each method can be used in the same manner in form source contact.
According to embodiment illustrated in Fig. 3 A, the part of formation transistor in the first main surface 110 of semiconductor body Afterwards, it can perform skiving processing.Thereafter, the contact trench for contacting drain region 405 can be formed from the second main surface 120 490.For example, this point can be performed by etching.After each groove is etched, executable oxidation processes are isolated with forming dorsal part Layer 480 and is additionally formed isolation structure 495, and dorsal part separation layer 480 and isolation structure 495 will make leading for contact trench 490 Electric material insulate with semiconductor body 100.Thereafter, conductive material can be filled in contact trench 490.The structure bag obtained Containing the drain contact adjacent with the second of semiconductor body 100 the main surface 120.
The semiconductor device shown in Fig. 3 A includes transistor 400.Transistor 400 includes the source region with source contact 401 and the drain region 405 that is contacted with drain electrode 406.Source region 401 and drain region 405 are set along a first direction, First direction is parallel to the first main surface 110.Channel region 420 and drift region 460 are arranged on source area along a first direction Between domain 401 and drain region 405.Gate electrode 410 is arranged to adjacent with channel region 420, and gate-dielectric 411 is set Between gate electrode 410 and channel region 420.In addition, field plate 450 is arranged to adjacent with drift region 460, field dielectric layer 451 It is arranged between field plate and drift region 460.Body contact region 425 is arranged to adjacent and optional with channel region 420 Ground is adjacent with drift region 460.Backside contact groove 490 is formed in the second main surface 120 of semiconductor body.Such as above institute Explain, contact trench 490 can be etched after making chip thinning., can due to etching contact trench 490 from the second main surface 120 Reduce etching period.According to embodiment, back-side metallization can be formed and in backside contact to perform by common processing step Conductive material is formed in groove.
According to another embodiment, contact openings 491 can be etched from the first surface 110 of semiconductor body.Fig. 3 B are shown can Make the example of semiconductor device manufactured in this way.The semiconductor device shown in Fig. 3 B includes half with being shown in Fig. 3 A The similar part of conductor device.By contrast, contact openings 491 are etched from the first main main surface 120 in surface 110 to the second.By In from the first main surface etching contact openings 491, only chip is patterned from side.Therefore, can avoid when adjustment first Main surface and carrying problem during the second main surface and adjustment problem.From the first main surface 110 formed contact openings 491 it Afterwards, oxide skin(coating) 480 can be formed on the dorsal part of semiconductor body.In addition, metal layer can be formed to form back-side metallization 475 while form the conductive material for defining drain contact 477.
As the modification of this method, contact openings 491 can be formed not reach the second master in the first main surface 110 Surface 120.In this case, contact doping 497 can be formed under the semiconductor body of the lower section of contact openings 491 Portion is to realize the contact with the second main surface 120.Fig. 3 C show the example for the semiconductor device that this method manufacture can be used.Such as Shown in figure, contact openings 491 are formed in the first main surface 110 of semiconductor body.In addition, contact doping 497 is set Put below contact openings 491, and extend to the second main surface 120 of semiconductor body.Alternatively, another doped body portion Divide and may be disposed at the lower section of doped portion 130.For example, another doped portion can have the first conductivity type, and can be according to Dopant of the doping concentration higher than part 130 doped with the first conductivity type.Thereafter, other processing step is can perform to define Drain contact.
According to the embodiment of description, one of source contact and drain contact are adjacent with the first main surface, source contact and leakage Another in the contact of pole is adjacent with the second main surface, and the second main surface is relative with the first main surface.However, understand from accompanying drawing can See, even if corresponding contact is arranged to adjacent with the second main surface, source electrode and drain region also can be adjacent with the first main surface.When When source electrode and drain region are adjacent with the first main surface, the semiconductor device implements lateral semiconductor devices, is partly led in the transverse direction In body device, electric current is realized in the main direction along parallel to the first main surface.
The method that Fig. 4 summarizes the formation semiconductor device according to embodiment.The method of manufacture semiconductor device includes：Having Have in the semiconductor body on the first main surface and form transistor.Forming the transistor includes：Source region is formed, forms drain region Domain, channel region is formed, is formed drift region (S10), form the source contact (S20) for being electronically connected to source region, And form the drain contact (S30) for being electronically connected to drain region.This method also includes：Grid are formed in channel region Electrode (S40).Channel region and drift region are formed to be arranged on along a first direction between source region and drain region, the One is oriented parallel to the first main surface, and channel region is formed with the shape of the first ridge extended along a first direction Shape.One of source contact and drain contact be formed it is adjacent with the first main surface, it is another in source contact and drain contact Individual to be formed adjacent with the second main surface, the second main surface is relative with the first main surface.
This method may also include：Make semiconductor body thinning (S50), and alternatively on the second main surface of the main body It is square into insulating barrier (S60).In addition, this method may include：Form the back of the body that (S70) extends to the second main surface from the first main surface Side contacts opening.This method may also include：Gate trench is formed in the first main surface.According to embodiment, this method includes： Field-plate trench is formed in first main surface.
For example, forming the part of the transistor may include：The part is formed in the first main surface of semiconductor body.Should Method may also include：A part for semiconductor body is removed so that semiconductor body is thinning from the second main surface.Semiconductor master Body can be silicon-on-insulator substrate, and the part of semiconductor base is removed to expose and is embedded in semiconductor base In insulator layer.This method may also include：It is square into insulator layer on the second major surface.Formed adjacent with the second main surface Source contact or drain contact may include：Contact trench is etched in the second main surface.Alternatively, can be in the first main surface Etch contact trench.This method may also include：Form the backside contact opening that the second main surface is extended to from the first main surface.Should Method may also include：Gate trench or field-plate trench are formed in the first main surface.Shape can be performed by combination treatment method Into gate trench or form field-plate trench.According to embodiment, backside contact opening has wider than gate trench or field-plate trench Degree and the big width of depth and depth.
The various embodiments of following accompanying drawing diagram semiconductor device, for example, semiconductor device discussed above, this is partly led Body device also includes interconnection element 633 to realize the interconnection between the first main 110 and second main surface 120 of surface.Interconnection element 633 can be differently arranged.The semiconductor device shown in Fig. 5 A includes transistor 500, transistor 500 have with above The similar structure of the semiconductor device that is shown in accompanying drawing.The semiconductor device includes transistor 500, and transistor 500 includes source electrode Region 501, source electrode 502, channel region 520, drift region 560 and it is connected to drain electrode 506 or includes the drain electrode of drain electrode 506 Region 505.Source region and drain region are arranged to adjacent with the first main surface.Channel region and drift region be arranged to First main surface is adjacent.Gate electrode 510 is arranged between source electrode and drain region.The semiconductor device is also included from the first master Surface extends to the contact openings on the second main surface, and the second main surface is relative with the first main surface.According to embodiment, gate electrode 510 are illustrated as being arranged in various gate trench 512.It should be noted that gate trench 512 cuts open along relative to what is shown The vertical direction extension of view.The structure comprising groove 512 is only illustrated to indicate：Gate electrode can be disposed in parallel to showing Accompanying drawing plane extension these grooves 512 in.More particularly, gate electrode can be as illustrated in Figure 1A, 1B, 1C and 1D. In a similar manner, field-plate trench 552 can extend along the direction of the plane of the accompanying drawing parallel to description.Field-plate trench comprising field plate Can be respectively as illustrated in Figure 1A, 1B, 1C and 1E.
Gate electrode 510 is electronically connected to gate metalized 530 through gate contact 568.Gate metalized 530 can quilt It is arranged on the side on the first main surface 110.Gate metalized 530 can by front side dielectric layer 565 come with the first main surface insulation. The semiconductor device also includes field plate 550, and field plate 550 is arranged in field-plate trench 552.Field plate 550 includes conductive material, should Conductive material is electronically connected to the back-side metallization 575 for being maintained at source potential through field plate contact 536.
In addition, drain region 505 can be connected by drain contact 577 with drain metallization 532.Drain metallization 532 It may be disposed at the side on the first main surface 110 of semiconductor body.Drain metallization 532 and gate metalized 530 are exhausted each other Edge, and can extend in relative to the vertical plane of the plane of the accompanying drawing of description.Back side metal 575 is arranged on semiconductor master The side on the second main surface 120 of body.Back-side metallization 575 can be by dorsal part dielectric layer 580 come exhausted with the second main surface 120 Edge.Source region 502 can be connected by source contact 567 with back-side metallization 575.According to Fig. 5 A embodiment, this is partly led Body device also includes interconnection element 633, and interconnection element 633 provides the connection between back-side metallization 575 and frontside contacts 531. For example, frontside contacts 531 can implement source electrode sensing contact.According to Fig. 5 A embodiment, interconnection element 633 can be disposed in dorsal part In contact openings 553, backside contact opening 553 has the shape similar with field-plate trench 552.
According to this embodiment, backside contact opening 553 can be formed simultaneously with field-plate trench 552.Insulating materials is (all Such as, form the insulating materials of field plate dielectric 551) can be formed it is adjacent with the side wall of backside contact opening 553.In addition, lead Electric material (conductive material for such as, forming field plate) can be filled in backside contact opening 553.Interconnection element 633 is through dorsal part Metal contact 535 is connected to back-side metallization layer 575.In addition, interconnection element 633 connects through contact portion 534 and frontside contacts 531 Connect.
According to the embodiment shown, some grooves 552,553 for being arranged to adjacent with drift region 560 can implement field-plate trench 552 and only can be connected with back-side metallization 575, and other grooves 553 implement interconnection structure 633 and with frontside contacts 531 Connected with back-side metallization 575.Frontside contacts 531 implement source electrode sensing contact.In fig. 5 in embodiment illustrated, source area Domain and drain region are formed adjacent with the first main surface, and the first main surface is located at the side of the top side of semiconductor device.Separately Outside, gate electrode 510 is adjacent with the first main surface, and the first main surface is located at the side of the front side of semiconductor device.
According to another embodiment, semiconductor device may be reversed, to cause the first of semiconductor body the main surface 110 and with The adjacent each part in one main surface 110 is arranged on the dorsal part of semiconductor device.
Fig. 5 B show counter structure.As shown in FIG., after each part of transistor is formed, main body upset, so that It is adjacent with the dorsal part of semiconductor device to obtain the first main surface 110.Therefore, the semiconductor device shown in Fig. 5 B includes being connected to source The source region 501 of electrode 502, channel region 520, drift region 560 and it is connected to drain electrode 506 or comprising drain electrode 506 Drain region 505.Drain electrode 506 is connected to frontside metal part 532, frontside metal through metallic plug 507 and drain contact 577 Part 532 is arranged on the front side of semiconductor device.
In addition, source electrode 502 is electronically connected to through metallic plug 508 and source contact 567 is maintained at source electrode electricity The back-side metallization 575 of gesture.According to the structure shown, the interconnected element 633 of gate electrode 510 and before being arranged in semiconductor device The gate electrode pad 530 of side connects, and interconnection element 633 extends to the second main table across semiconductor device from the first main surface 110 Face 120.The semiconductor device shown in Fig. 5 B also includes gate contacting structure, gate contacting structure connection gate electrode 510 with Interconnection element 633.By with it is graphic in Fig. 5 A in a manner of similar mode, interconnection element 633 may be disposed at and field plate ditch In the backside contact opening 553 of the similar shape of groove 552.Backside contact opening 553 is filled with insulating materials and conductive material.
According to the embodiment shown in Fig. 5 B, some grooves 552,553 are filled with the conduction material for being used for forming field plate 550 Material, the conductive material is connected only to back-side metallization 575, and the conductive material in other grooves 553 connects with gate contact 530 Connect, gate contact 530 is arranged on the front side of semiconductor device.
Therefore, graphic semiconductor device includes being formed in the semiconductor master with the first main surface 110 in Fig. 5 A and 5B Transistor 500 in body 100.The transistor includes source region 501,502, drain region 505,506, channel region 520, drift Move area 560 and the gate electrode 510 positioned at channel region 520.Channel region 520 and drift region 560 are set along a first direction Between source region 501,502 and drain region 505,506, first direction is parallel to the first main surface 110.Channel region 520 have the shape of the first ridge extended along a first direction.The semiconductor device is also included and extended to from the first main surface 110 The backside contact opening 553 on the second main surface 120, the second main surface 120 are relative with the first main surface 110.For example, the semiconductor Device may also include the conductive filler in backside contact opening 553, and the conductive filler and neighboring semiconductor bodies material are exhausted Edge.
The method of Fig. 5 C diagram manufacture semiconductor devices.This method includes：In the semiconductor body with the first main surface Middle formation transistor.Forming the transistor includes：Form the source region adjacent with the first main surface and drain region S100, shape Into the channel region and drift region S200 adjacent with the first main surface, and gate electrode is formed between source electrode and drain region S300.Forming gate electrode includes：Gate trench is formed in the first main surface.This method also includes：Formed from the first main surface Extend to the contact openings on the second main surface, the second main surface S400 relative with the first main surface.
This method may also include：Gate trench or field-plate trench are formed in the first main surface.For example, grid ditch can be formed Groove 512 is with the channel region of shape of the implementation with ridge.Alternatively, the drift for the shape that field-plate trench can be formed to implement there is ridge Move area.Gate trench or field-plate trench and formation contact openings can be formed to perform by combination treatment method.Contact openings can The big width of width and depth with than gate trench or field-plate trench and depth.For example, contact openings can have than grid The big width of the width and depth of groove or field-plate trench and depth.According to embodiment, form gate trench or form field plate ditch Groove is included with the engraving method of the etch rate etch contact openings higher than gate trench and field-plate trench., should according to embodiment Method may also include：A part for semiconductor body is removed so that semiconductor body is thinning from the second main surface.
For example, contact openings can have the width and depth bigger than the width and depth of gate trench or field-plate trench.Root According to embodiment, forming gate trench or forming field-plate trench is included with the etch rate etch higher than gate trench and field-plate trench The engraving method of contact openings.According to embodiment, this method may also include：One of semiconductor body is removed from the second main surface Divide so that semiconductor body is thinning.
The optional position that interconnection element 633 may be disposed in semiconductor device or integrated circuit.For example, as described above, Some field-plate trench 552 can be formed to form interconnection element 633.
According to another embodiment, the semiconductor device for including multiple single-transistor primitives of each gate electrode 610 can quilt The contact openings for forming interconnection element 633 surround.The corresponding semiconductor device of Fig. 6 A displays.The semiconductor device bag shown in Fig. 6 A Include the source region 601 for being connected to source electrode 602, channel region 620, drift region 660 and the drain region for being connected to drain electrode 606 Domain 605.Gate electrode 610 is arranged on channel region 620.Gate electrode 610 by gate dielectric 611 come with channel region 620 Insulation.In addition, field plate 650 is disposed in field-plate trench 652.Field plate 650 is by field dielectric 651 come exhausted with drift region 660 Edge.Field plate 650 can be omitted, or can be implemented in various ways.Include the semiconductor device quilt of multiple single-transistor primitives Contact openings 630 surround.Conductive filler 632 is arranged in contact openings 630, conductive filler 632 by dielectric material 631 come With adjacent semiconductor insulated with material.Contact openings can extend to semiconductor device from the first main surface 110 of semiconductor device Second main surface 120.Contact openings 630 and field-plate trench 652 can be formed by common or processing step simultaneously.
Fig. 6 B show another semiconductor device including field-plate trench 642 and combination contact openings 640.Field plate 650 by with It is arranged on the mode similar mode described in such as Fig. 1 in field-plate trench 652.The semiconductor device also includes combination contact Opening 640, combination contact openings 640 have the conductive filler 642 for being maintained at grid potential.Leading in combination contact openings 640 Electric filler 642 is insulated by dielectric material 641 with drift region 660.Another part of conductive filler with the phase of channel region 620 Implement gate electrode 610 in adjacent region.Combination contact openings 640 do not extend to the in the region adjacent with channel region 620 Two main surfaces 120.In the region adjacent with drift region 660, combination contact openings can for example implement graphic interconnection in Fig. 5 B Element 633.In this region, combination contact openings 640 can extend to the second main surface 120 from the first main surface 110.It is different The larger depth of contact openings 640 in region can be caused by the different in width of trench region.The semiconductor shown in Fig. 6 B The other part of device is similar to the part shown in Fig. 6 A.
According to another embodiment, the semiconductor device may include second groove 643, and second groove 643 is by along first party To being arranged between field-plate trench 652 and drain region 605.Second groove 643 is filled with conductive material 662, conductive material 662 By the second dielectric material 661 come with adjacent semiconductor insulated with material.For example, the conductive material 662 in second groove 643 can be protected Hold in grid potential, and therefore implement graphic interconnection element in Fig. 5 B.Graphic semiconductor device is other in Fig. 6 C Each part of semiconductor device of the part with being shown in Fig. 1 or 6A is identical.
Fig. 7 and 8 illustrates the element for being used to be formed the method for semiconductor device according to embodiment.
Fig. 7 A show semiconductor body or substrate 100 with embedment oxide skin(coating) 105.The ditch of first groove 710 and second Groove 720 is formed in the first main surface 110 of semiconductor body 100.Can be as traditional approach with photolithographicallpatterned definition the One groove 710 and second groove 720.For example, first groove 710 can have than second groove d8Small width d7, along parallel to attached The orientation measurement of the plane of the figure width.Thereafter, as traditional approach, etching step is performed.Due to the increasing of second groove 720 The width d added8, can be according to higher than first groove 710 etch rate etch groove.For example, such as RIE (" reactions can be used Ion(ic) etching ") anisotropic etch method of method etches the groove.Therefore, second groove 720 has than first groove 710 Deep depth.Second groove 720 extends to embedment oxide skin(coating) 105.Fig. 7 B show the example of obtained structure.
Thereafter, dielectric layer 730 is formed in each trench, then forms conductive layer 740.Perform planarization steps.Figure 7C shows the example of obtained structure.
Thereafter, skiving processing is can perform to remove the base part being located at below embedment oxide skin(coating) 105.For example, it can lead to Overetch, grinding or CMP (chemically mechanical polishing) methods realize this point.After this processing, embedment oxide is kept A part for layer 105.Then, another metal layer 750 can be formed on above the dorsal part of semiconductor body.As a result, can Obtain the structure shown in Fig. 7 D.As shown in FIG., second groove 720 may extend into back-side metallization layer 750, and first groove 710 do not extend to embedment oxide skin(coating) 105.For example, first groove 710 implements the gate trench being explained further herein, Second groove 720 can implement field-plate trench.Second groove 720 can be used as contact openings simultaneously.Using above-mentioned processing step, can make With it is common while processing step formed the first and second grooves 710,720.It is clearly understood that, according to alternative Method, different disposal can be used to form the first and second grooves.
It can be formed in the semiconductor body according to graphic another embodiment, the 3rd groove 725 in Fig. 8.In addition, can shape Into the first and second grooves 710,720, to cause first groove 710 and second groove 720 all not to extend to embedment oxide skin(coating) 105.Using this processing, special contact openings 725 can be formed, and form gate trench and field-plate trench simultaneously.For example, as schemed Can be SOI substrate for performing according to the starting point of the method for this embodiment shown in 8A.SOI substrate 100 includes embedment Oxide skin(coating) 105.Thereafter, first groove 710, the groove 725 of second groove 720 and the 3rd are formed on the first of semiconductor base In main surface 110.
Although not showing clearly in the fig. 8b, plane of the 3rd groove 725 along the accompanying drawing relative to description is vertical Direction has width d9, width d9Width than field-plate trench 720 and first groove 710 is much bigger.For example, the 3rd groove 725 can Implement loop configuration, also as depicted in figure 6b.Therefore, ratio can be etched to using a single engraving method, the 3rd groove 725 First groove 710 and second groove 720 firmly get more depth.For example, the 3rd groove 725 can be etched away to extend to embedment oxidation Nitride layer 105.Thereafter, dielectric layer 730, conductive layer 740 is then formed.
Fig. 8 C show the example of obtained structure.Thereafter, perform skiving method and be located at embedment oxide skin(coating) 105 to remove A part for the base material of lower section and embedment oxide skin(coating) 105 is to expose the bottom of the conductive material 740 in the 3rd groove 725 Part.Then, back-side metallization layer 750 can be formed to be embedded to the bottom side of oxide skin(coating) 105.Fig. 8 D show obtained structure Example.As shown in FIG., connecting element is implemented by the 3rd groove 725, and the 3rd groove 725 includes contact back-side metallization layer 750 conductive filler 740.
While embodiments of the invention have been described above, but further embodiment can be implemented.For example, further embodiment can Including any sub-portfolio of feature enumerated in the claims or any son of the element described in examples given above Combination.Therefore, this spirit and scope of appended claims should not be limited to the description of the embodiment contained here.

Claims (21)

1. a kind of semiconductor device, including the transistor in the semiconductor body with the first main surface, the transistor Including：
Source region；
Drain region；
Channel region；
Drift region；
Source conductive plug, is contacted with source region；
Source contact, electronically it is connected to source region, the source contact and the source conductive plug direct neighbor；
Drain contact, electronically it is connected to drain region；
Gate electrode, positioned at channel region, channel region and drift region are arranged on source region and drain region along a first direction Between domain, first direction is parallel to the first main surface, and channel region by extending along a first direction in the semiconductor substrate Adjacent gate trench is patterned into the first ridge extended along a first direction,
Wherein described source conductive plug include in the semiconductor body and along source region extend source contact opening, The source contact opening extends also along the second horizontal direction vertical with first direction, and the source contact opening is filled with Conductive material,
One of source contact and drain contact are adjacent with the first main surface, and another in source contact and drain contact is with second Main surface is adjacent, and the second main surface is relative with the first main surface.
2. semiconductor device according to claim 1, in addition to：Back-side metallization, positioned at the second main surface, back side metal Change is connected to the source contact adjacent with the second main surface or drain contact.
3. semiconductor device according to claim 2, in addition to：Sensing contact, positioned at the first main surface, sensing contact is through dorsal part Contact is connected with back-side metallization.
4. semiconductor device according to claim 3, wherein the backside contact, which is arranged on from the first main surface, extends to In the backside contact opening on two main surfaces.
5. according to the semiconductor device of any one of foregoing Claims, wherein source electrode and drain region is arranged to and the first master Surface is adjacent.
6. semiconductor device according to claim 1, in addition to：Field-plate trench, it is arranged in the first main surface and along One direction extends, and field plate is partially disposed within field-plate trench.
7. semiconductor device according to claim 1, in addition to：Insulating barrier, with the second major surface contacts.
8. semiconductor device according to claim 7, in addition to：Another semiconductor layer, the backside contact with insulating barrier.
9. semiconductor device according to claim 1, wherein one of the source contact adjacent with the second main surface and drain contact Not on the first main surface.
10. a kind of integrated circuit, including the first and second crystal being located at respectively in the semiconductor body with the first main surface Manage, each in the first and second transistors includes：
Source region；
Drain region；
Channel region；
Drift region；
Source conductive plug, is contacted with source region；
Source contact, source region is electronically connected to through source conductive plug；
Drain contact, electronically it is connected to drain region；
Gate electrode, positioned at channel region, channel region and drift region are arranged on source region and drain region along a first direction Between domain, first direction is parallel to the first main surface, and channel region by extending along a first direction in the semiconductor substrate Adjacent gate trench is patterned into the first ridge extended along a first direction,
Wherein described source conductive plug include in the semiconductor body and along source region extend source contact opening, The source contact opening extends also along the second horizontal direction vertical with first direction, and the source contact opening is filled with Conductive material,
One of the source contact of the first transistor and drain contact are adjacent with the first main surface, the source contact of the first transistor and Another in drain contact is adjacent with the second main surface, and the second main surface is relative with the first main surface.
11. integrated circuit according to claim 10, wherein the leakage of the source contact of the first transistor and second transistor Pole contact is adjacent with one of the first and second main surfaces, and the drain contact of the first transistor and the source electrode of second transistor connect Touch with the first and second main surfaces another is adjacent.
12. integrated circuit according to claim 11, in addition to：Metal layer, electronically connect the source of the first transistor Pole contacts and the drain contact of second transistor.
13. according to the integrated circuit of any one of claim 10 to 12, in addition to：Isolated groove, make the first transistor and Two-transistor is insulated, and isolated groove is arranged between the first and second transistors.
14. according to the integrated circuit of any one of claim 10 to 12, wherein：The source contact of first and second transistors with One of first and second main surfaces are adjacent, and in the drain contact of the first and second transistors and the first and second main surfaces Another is adjacent.
15. a kind of method for manufacturing semiconductor device, is included in the semiconductor body with the first main surface and forms transistor, Methods described includes：
Form the source region and drain region adjacent with the first main surface；
Form the channel region adjacent with the first main surface and drift region；
Formed in the semiconductor body and along source region extend source contact opening, the source contact opening also edge The second horizontal direction extension vertical with first direction, and the source contact opening is filled with conductive material；
Gate electrode is formed between source electrode and drain region, gate electrode is formed and forms gate trench included in the first main surface； And
The contact openings that the second main surface is extended to from the first main surface are formed, the second main surface is relative with the first main surface.
16. method according to claim 15, in addition to：Field-plate trench is formed in the first main surface, by Combined Treatment side Method to form field-plate trench and formation contact openings to perform.
17. method according to claim 16, wherein the contact openings have it is bigger than the width and depth of field-plate trench wide Degree and depth.
18. according to the method for any one of claim 15 to 17, in addition to：The one of semiconductor body is removed from the second main surface Part is so that semiconductor body is thinning.
19. according to the method for any one of claim 15 to 17, in addition to：The one of semiconductor body is removed from the second main surface Partly so that semiconductor body is thinning, the base section of contact openings is thus removed.
20. according to the method for any one of claim 15 to 17, in addition to：Form the insulating barrier adjacent with the second main surface.
21. according to the method for any one of claim 15 to 17, wherein the semiconductor body is silicon-on-insulator substrate, half Second main surface of conductor main body is adjacent with embedment insulator layer.
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