CN104937920A - Expanded-field-of-view image and video capture - Google Patents

Abstract

In various example embodiments, an imaging system and method are provided. In an embodiment, the system comprises a first image sensor array, a first optical system to project a first image on the first image sensor array, the first optical system having a first zoom level. A second optical system is to project a second image on a second image sensor array, the second optical system having a second zoom level. The second image sensor array and the second optical system are pointed in the same direction as the first image sensor array and the first optical system. The second zoom level is greater than the first zoom level such that the second image projected onto the second image sensor array is a zoomed in on portion of the first image projected on the first image sensor array. The first image sensor array includes at least four megapixels and the second image sensor array includes one-half or less than the number of pixels in the first image sensor array.

Description

Extended field of view image and Video Capture

This application claims the benefit of priority of the U.S. Provisional Patent Application sequence number 61/720,889 that on October 31st, 2012 submits to, this application is incorporated in this by reference in full.

Technical field

Subject content of the present invention relates generally to the optics and electronic device, system and method that comprise optical sensitive material (such as nanocrystal or other optical sensitive materials), and makes and use the method for described device and system.

Background technology

Imageing sensor is converted into recorded impression the space carried in area of light and space time information.Digital image sensor provides such impression recorded in electron region.

Wish that image sensor system provides certain field range, this field range allows user to gather within the scope of interested special angle to have the image of special high fidelity (features desired by other in such as resolution or signal to noise ratio or image).Wish wide angular range or visual field in some cases.

Accompanying drawing explanation

System and method as described herein is appreciated that by referring to accompanying drawing:

Fig. 1 shows general structure according to an embodiment and regional;

Fig. 2 is the block diagram that the example system that can combinationally use with embodiment as described herein configures;

Fig. 3 A-18B illustrates " overall situation " pixel shutter and arranges;

Figure 19 shows the vertically profiling of an embodiment, and the image element circuit on the metal interconnecting layer shielding semiconductor substrate of wherein integrated circuit avoids incident light impact;

Figure 20 shows the layout (top view) of an embodiment, and the image element circuit on the metal interconnecting layer shielding semiconductor substrate of wherein integrated circuit avoids incident light impact;

Figure 21 is the flow chart of the exemplary operation of each array;

Figure 22 shows an exemplary embodiment of the imaging system comprising two imaging arrays, wherein distinct, partly overlapping, the non-overlapping visual field of part of each array viewing;

Figure 23 shows an exemplary embodiment of the imaging system comprising two imaging arrays, wherein distinct, partly overlapping, the non-overlapping visual field of part of each array viewing;

Figure 24 shows an exemplary embodiment of the imaging system comprising single IC for both, and described single IC for both comprises at least two imaging array sections; Wherein distinct, partly overlapping, the non-overlapping visual field of part of each imaging array section viewing;

Figure 25-31 shows each embodiment of imaging system;

Figure 32 and 33 shows imaging array section and the visual field of various imaging system;

Figure 34 and 35 shows a series of imaging array section and the visual field of various imaging system;

Figure 36 shows an example of quantum dot (quantum dot);

The aspect that the closed simple geometry that Figure 37 A shows pixel is arranged;

The aspect that the open simple geometry that Figure 37 B shows pixel is arranged;

Two row that Figure 37 C shows in the usually larger array of top surface electrode take advantage of three row sub-segments;

Figure 38 A shows Bayer filter style;

Figure 38 B-38F shows the example of some replacement pixel layouts;

Figure 38 G-38L shows the pixel of the different size be used in pixel layout, layout and type;

Figure 38 M shows has difform pixel layout, such as hexagon;

Figure 38 N shows has difform pixel layout, such as triangle;

Figure 38 O shows the quantum dot pixel provided explicitly with optical element, such as multispectral quantum dot pixel or other pixels;

Figure 38 P shows an example of pixel layout;

Figure 39 A shows the cmos image sensor pixel of frontlighting, and wherein optical sensitive material has been integrated into and silicon diode close contact;

Figure 39 B shows the cmos image sensor pixel of frontlighting, and wherein optical sensitive material has been integrated into and silicon diode close contact;

Figure 39 C shows the cmos image sensor pixel of frontlighting, and wherein optical sensitive material has been integrated into and silicon diode close contact;

Figure 40 A shows the section of the cmos image sensor pixel of back lighting, and wherein optical sensitive material has been integrated into and silicon photoelectric diode close contact;

Figure 40 B shows the section of the cmos image sensor pixel of back lighting, and wherein optical sensitive material has been integrated into and silicon photoelectric diode close contact;

Figure 41 shows the circuit diagram of the imageing sensor corresponding to back lighting, and wherein optical sensitive material is integrated into silicon from the back side;

Figure 42 shows the flow chart of the operation of image element circuit;

Figure 43 and 44 shows the exemplary embodiment of multiple aperture convergent-divergent (zoom) from the visual angle of the scene of imaging;

Figure 45-48 is flow charts of the exemplary operation for image;

Figure 49-58 shows the exemplary embodiment of multiple aperture convergent-divergent from the visual angle of the scene of imaging;

Figure 59 depicts by light blocking layer being incorporated in the section reducing a kind of mode of the optical crosstalk between pixel in color filter array or its passivation or encapsulation or some combination;

Figure 60 depicts by being incorporated in by light blocking layer in color filter array or its passivation or encapsulation or some combination and being merged in optical sensitive material a kind of section of mode of the crosstalk reduced between pixel; And

Figure 61 A-61F depicts the section that making such optical crosstalk as shown in Figure 59 reduces a kind of mode of structure.

Only as an example some embodiments are described with reference to accompanying drawing.Accompanying drawing is not necessarily pro rata.For clarity and conciseness, some feature of embodiment can be exaggerated and be illustrated by schematic form.

Embodiment

Some embodiments comprise a kind of imaging system, and it has: the first image sensor array; Be configured to first optical system of the first image projection on the first image sensor array, described first optical system provides the first visual field; Second image sensor array; Be configured to second optical system of the second image projection on the second image sensor array, described second optical system has the second visual field; Wherein said first visual field and the second visual field comprise some laps in the angular range of imaging; And wherein said first visual field and the second visual field comprise some zero lap parts in the angular range of imaging.

Some embodiments comprise a kind of imaging system, and it has: the first image sensor array; Be configured to first optical system of the first image projection on the first image sensor array, described first optical system carries out imaging to the Part I of scene; Second image sensor array; Be configured to second optical system of the second image projection on the second image sensor array, described second optical system carries out imaging to the Part II of scene; The Part I of wherein said scene and the Part II of described scene comprise some laps in the scene of imaging; And the Part II of the Part I of wherein said scene and described scene comprises some zero lap parts in the scene of imaging.

Some embodiments comprise a kind of imaging system, and it comprises: the integrated circuit at least comprising the first imaging array section and the second imaging array section; Be configured to by the first image projection to the first optical system on described first imaging array section, described first optical system provides the first visual field; And be configured to by the second image projection to the second optical system on described second imaging array section, described second optical system has the second visual field; Wherein said first visual field and the second visual field comprise some laps in the angular range of imaging; And wherein said first visual field and the second visual field comprise some zero lap parts in the angular range of imaging.

Some embodiments comprise a kind of imaging system, and it comprises: the integrated circuit at least comprising the first imaging array section and the second imaging array section; Be configured to first optical system of the first image projection on the first imaging array section, described first optical system carries out imaging to the Part I of scene; And be configured to by the second image projection to the second optical system on described second imaging array section, described second optical system carries out imaging to the Part II of scene; The Part I of wherein said scene and the Part II of described scene comprise some laps in the scene of imaging; And the Part II of the Part I of wherein said scene and described scene comprises some zero lap parts in the scene of imaging.

Some embodiments comprise a kind of imaging system, and wherein the first image sensor array comprises at least one mega pixel.

Some embodiments comprise a kind of imaging system, and wherein the first imaging array section comprises at least one mega pixel.

Some embodiments comprise a kind of imaging system, and wherein the first imaging array section and the second imaging array section are formed on the same substrate.

Some embodiments comprise a kind of imaging system, and the angular relationship between the direction of gaze of wherein the first imaging section and the second imaging section can be changed.

Some embodiments comprise a kind of imaging system, and the angular relationship between the direction of gaze wherein changing the first imaging array section and the second imaging array section allows the visual field changing imaging system.

Some embodiments comprise a kind of imaging system, wherein form the digital picture that combination gathers the information from the first imaging array section and the second imaging array section.

Some embodiments comprise a kind of imaging system, and it comprises: for the first image element circuit from the first imaging array section reads image data; And for the second image element circuit from described imaging array section reads image data; Wherein said image element circuit is configured to the image being collected in substantially the same time interval collection from two imaging array sections.

Some embodiments comprise a kind of imaging system, and it comprises: for the first image element circuit from the first imaging array section reads image data; And for the second image element circuit from described imaging array section reads image data; Wherein said image element circuit is configured to the global electronic shutter image being collected in substantially the same time interval collection from two imaging array sections.

Some embodiments comprise a kind of imaging system, wherein said imaging system is a part for camera device, it also comprises control circuit, this control circuit is configured at least one sub-segments of combination image, export the image with super-resolution, and this has at least partially generation of image from least partially with the second imaging array section of the first imaging array section of super-resolution.

Some embodiments comprise a kind of imaging system, and wherein said control circuit is configured in the almost identical time, the switching device of each image element circuit is switched to the second state from the first state for each image element circuit an integration (integration) after the time period.

Some embodiments comprise a kind of imaging system, and wherein each image element circuit also comprises reset circuit, and reset circuit is configured to the voltage difference resetting optical sensitive material two ends when described switching device is in the second state.

Some embodiments comprise a kind of imaging system, and wherein each image element circuit also comprises the reading circuit of side below multiple pixel section being formed in semiconductor substrate.

Some embodiments comprise a kind of imaging system, and wherein said optical sensitive material is the continuous film of nano crystal material.

Some embodiments comprise a kind of imaging system, it also comprises in order to the analog to digital change-over circuit according to the signal generation digital pixel numerical value read from the image element circuit corresponding to each image sensor array, and the pixel number being configured to process in the first mode of operation corresponding at least two image sensor arrays is to generate the processor of output image.

In the exemplary embodiment, integrated circuit (IC) system can comprise multiple imaging section.Fig. 1 is the block diagram of the image sensor IC (it is also referred to as image sensor chip) comprising multiple imaging section 100,400,500,600,700,800.Imaging section 100 maximum in the middle of these imaging sections has maximum pixel number (such as approximate 8 mega pixels) usually, and imaging section 100 can be referred to as main imaging array.Additional imaging array has less number of pixels usually, and additional imaging array can be referred to as secondary imaging array 400,500,600,700,800.

In pel array 100,400,500,600,700,800, incident light is converted into electronic signal.Electronic signal is integrated in charge storage storehouse, and the content in charge storage storehouse is relevant with integration light incident within the frame period with voltage levvl.Such as 110 and 120,410 are used to reset each pixel with the row and column circuit such as 420 and read the signal relevant with the content in each charge storage storehouse, so that the outer peripheral of the information delivery relevant with the integration light in each pixel in the frame period to chip.In further detail Fig. 1 is described below.

Figure 2 illustrates various analog circuit, comprise 130,140,150,160 and 230.Pixel electrical signal from column circuits is fed at least one AD converter 160, and at AD converter 160 place, it is converted into the digital value of the luminosity (light level) representing each pixel place.Described pel array and ADC are by the analog circuit support providing biased and reference level 130,140 and 150.

In certain embodiments, given integrated circuit can adopt more than one ADC 160.In certain embodiments, an ADC can be had for each imaging section 100,400,500 etc.In certain embodiments, all imaging sections can share single ADC.In certain embodiments, multiple ADC can be used, but given ADC can be responsible for the analog to digital conversion of the signal of more than one imaging section.

Various digital circuit comprises 170,180,190 and 200 shown in figure 2.Image Enhancement Circuit 170 is for providing image enhancement functions to improve signal to noise ratio output from the data of ADC.Line buffer 180 temporarily stores the pixel number of several lines to promote Digital Image Processing and IO function.Register 190 is the global operation of regulation system and/or the Parasites Fauna of frame format.The operation of square frame 200 control chip.

In the embodiment adopting multiple imaging array, digital circuit can obtain information from multiple imaging array, and the data that the information provided by multiple imaging array is provided can be generated, such as the version through amendment of single image or the image from multiple imaging array.

I/O circuit 210 and 220 had both supported that serial input/output was also supported in parallel I/O.I/O circuit 210 is parallel I/O interface, each bit of its simultaneously output pixel numerical value.I/O circuit 220 is serial I/O interface, each bit of sequentially output pixel numerical value at this place.

In certain embodiments, given integrated circuit can adopt more than one I/O circuit.In certain embodiments, an I/O system can be had for each imaging section 100,400,500 etc.In certain embodiments, all imaging sections can share single I/O system.In certain embodiments, multiple I/O system can be used, but given I/O system can be responsible for the analog to digital conversion of the signal of more than one imaging section.

Phase-locked loop 230 provides clock for whole chip.

In a specific exemplary embodiment, when employing 0.11 μm of CMOS technology node, along row axle and along the periodicity repeat distance of the pixel of row axle can be 700nm, 900nm, 1.1 μm, 1.2 μm, 1.4 μm, 1.55 μm, 1.75 μm, 2.2 μm or larger.The realization of the minimum pixel size in the middle of these Pixel Dimensions (particularly 700nm, 900nm, 1.1 μm, 1.2 μm and 1.4 μm) may need to carry out transistors share in the middle of the Geng great group of each pair of neighborhood pixels or neighborhood pixels.

Pixel Dimensions in lateral dimensions can from be less than about 0.5 to 3 microns or be included in any scope wherein (from be less than about 0.5 to 3 microns square area or any scope of being included in wherein) change.In some instances, Pixel Dimensions can be less than about 1.3,1.4,1.5,1.7,2,2.2 or 2.5 microns (and have be less than this quantity square area).Concrete example is 1.2 and 1.4 microns.Primary array can have the pixel being greater than secondary array.Primary array can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron, and is less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron.Described one or more secondary array also can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron and be less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron, but will be less than primary array.For example, primary array can be greater than X, and secondary array can be less than X, and wherein X is 1.2,1.4,1.5,1.7 or 2 etc.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode (pinned photodiode), part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

In certain embodiments, very little pixel can be implemented.The all silicon circuit regions be associated with each pixel are associated can promote the enforcement of small pixel with reading electronic installation.In certain embodiments, optics sensing can separately be realized by the optical sensitive layer occuping upperside interconnection layer at another vertical-horizontal place.

In certain embodiments, can global electronic shutter and many array image sensor systems combined.Global electronic shutter refers to a kind of like this configuration, wherein can sample to given imaging array in the substantially the same time.In other words, in global electronic shutter, can making to integrate the period for all pixels in imaging array section, to start and integrate the absolute time that the period terminates be identical substantially.

In certain embodiments, multiple pattern matrix can adopt global electronic shutter, and its view data can be combined afterwards.In certain embodiments, for making to integrate the period with all pixels that the multiple arrays in imaging system are associated, to start and integrate the absolute time that the period terminates be identical substantially.

In certain embodiments, image sensor system comprises: the first imageing sensor section; Second imageing sensor section; Wherein each imageing sensor section implements global electronic shutter, wherein during first time period, the electron charge that each accumulation in the middle of described at least two imageing sensor sections is proportional with the photon integrated flux in each pixel in each imageing sensor section; And during the second time period, each imageing sensor section extracts the electronic signal proportional with the electron charge accumulated in each pixel section in the integration period corresponding in each pixel section.

Fig. 3 A-18B shows the additional pixels circuit comprising " overall situation " shutter and arrange.Global shutter arranges the voltage allowing to correspond to multiple pixel or whole pel array at identical Time capture.In the exemplary embodiment, can these image element circuits and small pixel section combined use, described small pixel section can have the area that is less than 4 square microns in the exemplary embodiment and be less than the distance between the electrode of 2 microns.Pixel section can be formed on semiconductor substrate, and below pixel section, image element circuit can be formed on the substrate or in described substrate.Image element circuit can be electrically connected to the electrode of pixel section by the through hole of integrated circuit and interconnection layer.Can metal level be set to shield the impact that image element circuit avoids (comprising the transistor or diode that are used to global shutter) light be incident on the optical sensitive layer in pixel section, below as further describing.

Some embodiments of global shutter image element circuit have single global shutter and catch, and wherein before the new integration period starts, read all row.Other embodiments have continuous global shutter, and it allows the new integration of a frame and the reading of former frame to occur simultaneously.Just the same with rolling shutter, greatest frame rate equals read-out speed.Single global shutter may need to stop when pixel is integrated reading.Therefore, greatest frame rate may be reduced due to additional integrating time.

The embodiment of the global shutter image element circuit described below comprises several modification utilizing quantum dot film to realize 5T, 4T, 3T, 2T and 1T pixel of global shutter.In one exemplary embodiment, described quantum dot film can be the photoconductor with optical sensitive nano crystal material described above.In the exemplary embodiment, the electric current through described film has non-linear relation with the luminous intensity absorbed by nano crystal material.Apply biased at nano crystal material two ends by electrode described above, this biased voltage difference causing described film two ends.In the exemplary embodiment, when apply at described film two ends described above this biased time, described film provides photoconductive gain.Described electrode can adopt any photoconductor configuration described above or other configurations.In certain embodiments, these circuit can be used to the one deck reading multilayer or Multi sectional colour element, as further describing below.

In the exemplary embodiment of global shutter image element circuit, can some or all of following characteristics be used:

-described film can be configured to current source or current sink.

-charge storage storehouse can to isolate with radiation source independent of the film in pixel section.

-dividing element between membrane interface and memory element can be used (to comprise non-linear element; Such as diode or switch).

-reading transistor can be used, read the amplifier that transistor is configured to the device operation that jointly can connect independent of other.Described amplifier operates usually used as source follower, but also can use other embodiments.

-implicit or parasitic diode, in certain embodiments, can be used to reset described film or control reading transistor.

The array of-pixel section can have the common electrode shared between all pixel section (or set of neighborhood pixels), and each pixel section can have and other electrode isolation absolute electrode.In certain embodiments, described common electrode can be positive or negative, and need not be subject to the constraint of CMOS track or ESD device.In certain embodiments, described common electrode can accept dynamic signaling.

-for utilizing the continuous shutter operation read simultaneously, use the mechanism resetting described film independent of charge storage storehouse in the exemplary embodiment.

Fig. 3-18 below illustrates the global shutter image element circuit according to exemplary embodiment.Fig. 3 A-18A is the pixel schematic circuit of a specific embodiment respectively.Corresponding Fig. 3 B-18B be a diagram that the device profile map that the physics of the related circuit in integrated circuit (IC)-components is arranged respectively.

The abbreviation being used to describe each embodiment is explained: 4T shows use 4 transistors as below; C shows " continuously "; NC shows " discontinuous "; 2D shows 2 diodes; And+1pD shows 1 parasitism (or being in fact " freedom ") diode.

4T, NC global shutter circuit:

The operating concept of 4T is also the basis for other designs.Fig. 3 A is the circuit diagram of the pixel/section/layout of the embodiment corresponding to 4T, NC device 120.Device 120 is the isolating switches enabling global shutter.Pixel is reset by RT is high and T is high.After when being exposed to, T is switched to low, and described film is no longer integrated on the grid of 140.RS is switched to height, and INT is sampled at CS place.

Following RT and T is switched to height according to suitable order and is switched to low subsequently.Signal RESET is sampled.Pixel number is RESET-INT.Regulate the darkness (dark level) of pixel by CD being set to desired numerical value, this numerical value can be different from the CD numerical value during the overall situation resets.Two sampling (double sampling) is for removing changes of threshold and setting the object of darkness side-play amount.The film at 110 places serves as current sink.Device 150 serves as the switch of the source electric current of the follower for 140 places.Device 130 resets memory node and described film.Memory node is in 115 places.

5T, C global shutter circuit:

Fig. 4 A is the circuit diagram of the pixel/section/layout of the embodiment corresponding to 5T, C device.In order to realize the continuous global shutter operation shown in Fig. 4 A, reset film 210 independent of memory element 215.The 5th transistor 221 as shown in Figure 4 A achieves this point.There is parasitic antenna (parasitics) then film be regarded as the integrator of integrated.It resets by 230, and utilizes 220 transfer charges.Described sampling plan designs identical with 4T, and its difference is the following fact: the memory element at 215 places is reset independent of described film now, and that is when RT is brought to high, signal T is low.

4T (+1pD), C global shutter circuit:

Fig. 5 A is a kind of modification of the circuit of the 4T corresponded in Fig. 4 A, wherein with the addition of parasitic antenna.In this embodiment, these parasitic antennas can be used to only utilize 4T to realize the operation of continuous global shutter.Parasitic diode 312 allows to reset film 310 now.Common membrane electrode F is brought to negative value, thus makes 312 to open and described film is reset to desired level.So just to parasitic membrane capacitance 311(, it is not necessarily in described film) charging.F electrode is upwards brought back to new more high level now, and described film is integrated.Number of times desired by described film can being reset when not affecting the memory element at 315 places now.

4T (+1D), C global shutter circuit:

By adding diode 411, in 4T, achieve the continuous shutter operation shown in Fig. 6 A.Described diode utilizes the PN junction of N well region section 485 inside to produce.Operate identical with the 5T shown in Fig. 4 A.Main difference is, instead of replacement device with diode.When RTF is high, electric current can flow thus move the film at 410 places to replacement level.RTF falls subsequently, to allow the integration of film Nodes.Parasitic capacitance provides main memory node.

3T (+2D), C global shutter circuit:

Fig. 7 A shows 3T configuration, and wherein diode 520 replaces the transistor from 320.Parasitic diode 512 is used to reset film 510 independent of the memory node at the grid place of 540.This is by pulsing F node to negative value thus making diode 512 open and realize.After 511 places integrate electric charge, shift described electric charge by F being driven into high voltage.Open diode 520 like this.

2T (+2D), C global shutter circuit:

Fig. 8 A shows the 2T pixel can carrying out continuous global shutter operation.Two diodes at 612 and 620 places are used for resetting pixel and transfer charge, as described herein.The row selector part at present 550 places is removed.Pixel utilizes single alignment 670 and single line 660 to carry out work.By adding RT line, 2 horizontal alignments and 1 horizontal path are needed altogether for operation.This reduces for the necessary cloth specific electric load of each pixel.Pixel carries out work by the memory node at the grid place of 640 being reset to high voltage and subsequently R being reduced to minimum numerical value.Have turned off the source follower at 640 places like this.In order to read pixel, R is brought to height.Along with R is brought to height, the parasitic capacitance at pixel place (particularly the drain/source place of 630) makes memory node rise to more high level.In this " winner is complete to be obtained " configuration, being about to only activates alignment.

3T (+1pD), C global shutter circuit:

Show another embodiment of 3T contiguous pixels in figure 9 a.Here, row selector part described above is removed.An advantage of this 3T is do not have obvious diode.The parasitic diode at 712 places resets pixel independent of memory node.Device profile in block 794 shows that little layout is possible.

1T (+3D) global shutter circuit:

The 1T version of pixel has been shown in Figure 10 A, and wherein diode replaces vital transistor.First film 810 is reset by F being taken to negative value.Next by F is taken to intermediate level to integrate.Transfer charge is carried out finally by F is taken to height.Even if described scheme makes in the saturated condition, F is taken to height and still electric charge can be shifted onto on memory node.Lowly memory node is reset by R is taken to.Because electric charge is always pulled on memory node, therefore we ensure that function of reset correctly can set initial charge.

4T, PMOS global shutter circuit:

The PMOS version of 4T has been shown in Figure 11 A.Its class of operation is similar to 4T NMOS version, and difference is that continuous shutter operation is feasible for P+/N trap diode 911.Enough low by CD is taken to, film 910 is reset to CD by described diode.

3T, PMOS global shutter circuit:

Show the PMOS version of 3T in fig. 12.Row selector part is removed now, and defines compact layout.

2T, PMOS global shutter circuit:

Show the PMOS version of 2T in figure 13a.It carries out work by CS being taken to the low next described film of overall replacement.Subsequently through 1120 transfer charges.

3T (+1D), NC global shutter circuit:

Figure 14 A shows the 3T version of pixel, wherein film 1210 generation current and not Absorption Current.Pixel is integrated when F is high.When F is forced low, diode 1220 turns off.Once described diode turns off, then no longer stored charge.

2T (+1D), NC global shutter circuit:

Figure 15 A shows 2T version, and wherein row selector part is removed.Do like this and save some areas compared with 3T, but reduce pixel coverage.

2T (+1D) alt, NC global shutter circuit:

Figure 16 A shows the replacement layout corresponding to 2T, and wherein diode is used as resetting device.

2T (+1pD), NC global shutter circuit:

Figure 17 A eliminates replacement device, and utilizes parasitic diode 1512 to reset described film.

1T (+2D), NC global shutter circuit:

There is the 1T generation compact layout as shown in figure 18 of 2 diodes.If do not need global shutter to operate, then likely produce the 1T with 1 diode.Described diode is very little in this case.This 1T+1D pixel eliminates the diode 1620 between film 1610 and source follower gate 1640, and forms the direct connection from described film to source follower gate.The operation of this pixel can be inferred from behind for the description of 1T+2D.First by F being taken to height and R being taken to low and resets pixel.Described film is reset to the low-voltage (such as gnd) at R place downwards by 2 diodes.Next R is driven into 1V.This makes described film start to integrate.The voltage at source follower gate place starts to increase.If voltage increase starts to exceed 1V, it is by by the voltage clamping at R place.Here it is saturation level.For non-saturated pixel, described grid is less than the voltage of 1V by increasing.In order to stop integrating electric charge, F is driven to low.Do like this and to have blocked electric current due to diode action and flow to path in memory node.When reading pixel, R is driven upwardly 3V, and the R at other every a line places is maintained at 1V simultaneously.Make memory element in voltage, promote nearly 1V like this.R provides drain current for source follower, and alignment is by the row cutting activated and can not by other row cutting, must configure this is because source follower is in that winner is complete.INT numerical value is sampled.Following R is lowered to low level and is again drawn high subsequently.Do replacement memory node like this, and subsequently RESET level is sampled.By about the suitable R level of the lever selection that uses when resetting described film, likely set darkness side-play amount.

Image element circuit above can be together used with any photoelectric detector as described herein and pixel section structure.In certain embodiments, by using an image element circuit for each section (redness of such as optical sensitive material, green and blue section), can together use image element circuit above with Multi sectional pixel arrangement.Described image element circuit can signal-obtaining in buffer, and described buffer stores the multiple color data corresponding to each pixel.For example, described array can read pixel on a row by row basis.Described signal can be converted into color digital pixel data subsequently.These image element circuits are only exemplary, and other embodiments can use other circuit.In certain embodiments, described film can be used in direct integration mode.Described film is treated by as photo-resistor usually, and photo-resistor is along with luminosity change electric current or resistance.In this direct integration mode, described film is biased to direct voltage output device.Voltage level directly shows incident luminosity.

In certain embodiments, the transistor with strong noise factor can be utilized to read quantum film signal.For example, having other noise sources of large leakage current and transistor itself to deposit in case, thin oxide transistor can be used to read quantum film signal.It may be because described film has the intrinsic gain helping to suppress transistor noise that this way becomes.

As previously mentioned, the metal in vertical stacked and/or metal contact element can be laid in the different layers of photodetector structure, and are used as contact and/or are used as shielding or barrier assembly or element.In certain embodiments, one or more metal level is such as used to isolate or shields the assembly (such as charge storage storehouse or charge storage device) of lower circuit or other assemblies of IC.Figure 19 and 20 shows an embodiment, wherein between the charge storage storehouse of the pixel section of correspondence, places electric conducting material, thus the charge storage storehouse of described correspondence and the light be incident on optical sensitive layer are isolated.Described electric conducting material at least partially with the optical sensitive layer electric connection of corresponding pixel section.Electric contact piece as described herein can also be used as except it as except the function of isolated component at the metal section also described shown in Figure 37 and 38 or layer.

Figure 19 shows the vertically profiling that metal covers pixel.Described pixel comprises silicon part 140, polysilicon layer 130 and metal level 120 and 110.In this embodiment, 120 and 110 arrangement (staggered) is staggered to cover the silicon part of pixel completely.Part incident light 100 is by 110 reflections.Remaining incident light 100 is covered, typically with metal layers 120 reflections.Consequently, do not have luminous energy to get at and reach silicon 140.So just improve the insensitivity of memory node (141) for incident light completely.

Figure 20 shows the layout (top view) that metal covers pixel.In this embodiment, three metal levels (such as corresponding to the metal 4/5/6 of the layer 108,110 and 112 in Figure 19) are used to cover the silicon part of pixel completely.Section 200 is metals 4, and section 210 is metals 5, and section 220 is metals 6.The whole pixel region of section 200/210/220 Inertial manifolds, and therefore prevent any light from arriving the silicon part of lower pixel.

With reference to Figure 21, some embodiments comprise a kind of method comprised the following steps:

At operation 2101 place, provide signal to show to integrate the initial of period;

At operation 2103 place, propagate described signal at least two imaging array sections;

At operation 2105 place, synchronously or puppet synchronously start to be incorporated in each in the middle of described two imaging array sections;

At operation 2107 place, synchronously or asynchronously read signal from each imaging array section;

At operation 2109 place, process described signal, comprise analog gain, analog to digital conversion and Digital Signal Processing potentially;

At operation 2111 place, combination or Combined Treatment are from the numerical data of at least two imaging array sections;

At operation 2113 place, provide combination from the numeral of the image of the information of each imaging array section.

With reference to Figure 22, a kind of imaging system can comprise: the first imageing sensor S1 visual field FOV1 being carried out to imaging; And the second imageing sensor S2 and imaging is carried out to visual field FOV2.In certain embodiments, described imaging system can provide combination from the digital picture of the information of S1 and S2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 23, a kind of imaging system can comprise: the first imageing sensor S1 visual field FOV1 being carried out to imaging; And the second imageing sensor S2 and imaging is carried out to visual field FOV2.In certain embodiments, described imaging system can provide combination from the digital picture of the information of S1 and S2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 24, a kind of imaging system can comprise integrated circuit S1, and it comprises: imaging array section A1 and imaging array section A2; Wherein A1 carries out imaging to visual field FOV1; And A2 carries out imaging to visual field FOV2.In certain embodiments, described imaging system can provide combination from the digital picture of the information of A1 and A2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 25, a kind of imaging system can comprise: the first imageing sensor S1 and the first optical element O1, O1 comprise at least one lens L1.1, and it together carries out imaging to visual field FOV1; Second imageing sensor S2 and the second optical element O2, O2 comprise at least one lens L2.1, and it together carries out imaging to visual field FOV2.In certain embodiments, described imaging system can provide combination from the digital picture of the information of S1 and S2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 26, a kind of imaging system can comprise: the first imaging array section A1 and the first optical element O1, O1 comprise at least one lens L1.1, and it together carries out imaging to visual field FOV1; Second imaging array section A2 and the second optical element O2, O2 comprise at least one lens L2.1, and it together carries out imaging to visual field FOV2.In certain embodiments, A1 and A2 can occupy on single IC for both S1.In certain embodiments, described imaging system can provide combination from the digital picture of the information of A1 and A2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 27, a kind of imaging system can comprise: the first imageing sensor S1 and the first optical element O1, O1 comprise at least one wafer-level lens L1.1, and it together carries out imaging to visual field FOV1; Second imageing sensor S2 and the second optical element O2, O2 comprise at least one wafer-level lens L2.1, and it together carries out imaging to visual field FOV2.In certain embodiments, described imaging system can provide combination from the digital picture of the information of S1 and S2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 28, a kind of imaging system can comprise: the first imaging array section A1 and the first optical element O1, O1 comprise at least one wafer-level lens L1.1, and it together carries out imaging to visual field FOV1; Second imaging array section A2 and the second optical element O2, O2 comprise at least one wafer-level lens L2.1, and it together carries out imaging to visual field FOV2.In certain embodiments, A1 and A2 can occupy on single IC for both S1.In certain embodiments, described imaging system can provide combination from the digital picture of the information of A1 and A2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 29, a kind of imaging system can comprise: the first imageing sensor S1; Second imageing sensor S2; First optical element O1, O1 comprise at least one wafer-level lens system L1; Wherein L1 is imaged onto visual field FOV1 on S1; And L1 is imaged onto visual field FOV2 on S2.In certain embodiments, described imaging system can provide combination from the digital picture of the information of S1 and S2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 30, a kind of imaging system can comprise: the first imaging array section A1; Second imaging array section A2; First optical element O1, O1 comprise at least one wafer-level lens system L1; Wherein L1 is imaged onto visual field FOV1 on A1; And L1 is imaged onto visual field FOV2 on A2.In certain embodiments, A1 and A2 can occupy on single IC for both S1.In certain embodiments, described imaging system can provide combination from the digital picture of the information of A1 and A2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 31, a kind of imaging system can comprise: the first imaging array section A1; Second imaging array section A2; First optical element O1, O1 comprise at least one wafer-level lens system L1; Wherein L1 is imaged onto visual field FOV1 on A1; And L1 is imaged onto visual field FOV2 on A2.In certain embodiments, L1 and L2} at least one of them can comprise at least one lens non-centrosymmetrical or lens element; In certain embodiments, it may comprise astigmatism (astigmatism).In certain embodiments, A1 and A2 can occupy on single IC for both S1.In certain embodiments, described imaging system can provide combination from the digital picture of the information of A1 and A2, to produce the image substantially crossing over visual field FOV3 in its information content, wherein FOV3 crosses over the union of FOV1 and FOV2 substantially.

With reference to Figure 32 and Figure 33, a kind of imaging system can comprise: the first imaging array section A1; Second imaging array section A2; 3rd imaging array A3; And the 4th imaging array A4.In certain embodiments, { at least two in the middle of A1, A2, A3, A4} can occupy on single IC for both S1.In certain embodiments, described imaging system can provide combination from { A1, A2, A3, the digital picture of the information of at least two in the middle of A4}, substantially crosses over visual field { FOV1, FOV2 to produce in its information content, the image of at least two (see Figure 33) in the middle of FOV3, FOV4}.

With reference to Figure 34 and Figure 35, a kind of imaging system can comprise a series of imaging array section, such as { A1...A7}.In certain embodiments, { at least two in the middle of A1...A7} can occupy on single IC for both S1.In certain embodiments, described imaging system can provide combination from { digital picture of the information of at least two in the middle of A1...A7}, substantially crosses over the visual field { image of at least two (see Figure 35) in the middle of FOV1...FOV7} to produce in its information content.In certain embodiments, { total angle at least one x, y in the middle of FOV1...FOV7} or all both direction is crossed over and is significantly less than, and { at least another x, y in the middle of FOV1...FOV7} or the total angle all in both direction are crossed over.In certain embodiments, { the area of at least one in the middle of A1...A7} is significantly less than { at least another the area in the middle of A1...A7}.In certain embodiments, { the area of each pixel at least one in the middle of the A1...A7} is significantly less than { area of each pixel at least in another in the middle of A1...A7}.In certain embodiments, described first elemental area is selected from list { 1.4x1.4 μm, 1.1x1.1 μm }, and less described second elemental area is selected from list { 1.1x1.1 μm, 0.9x0.9 μm, 0.7x0.7 μm and 0.5x0.5 μm }.In certain embodiments, the resolution than higher degree in other arrays can be realized in some imaging array.In certain embodiments, if heart place wishes higher resolution in the picture compared with peripheral with image, then by individual high resolution sensor and/or combination from the information of multiple array, special total resolution can be chosen to heart place in the picture higher.

In certain embodiments, at least one imaging array section provides the visual angle different from the second imaging array section about scene or sight line, that is there are the different apparent locations of the given object from two imaging array sections viewings.In certain embodiments, the difference at sight line, parallax or visual angle is used to infer that object is to the degree of depth in scene.In certain embodiments, estimating depth is carried out by combination from the information of at least two imaging array sections collection.In certain embodiments, imaging system can adopt one to train the period after assembling, in the training period, utilize selected known test scene to determine sight line difference; And adopt software, described software adopts knowledge about the specific parallactic error of specific imaging system of having assembled to provide estimation of Depth.In certain embodiments, fabrication tolerance is reduced due to the fact that: do not need to realize accurate side-play amount; But contrary, final side-play amount can be estimated after assembling.

In certain embodiments, along the first dimension being marked as x, number n_x imaging array section can be adopted; And along being marked as second dimension of y, number n_y imaging array section can be adopted.In certain embodiments, the image from multiple imaging array section can be combined, to provide than as larger visual field, the individual visual field of at least one in the imaging array section of part.In certain embodiments, n_x is not equal to n_y.In certain embodiments, n_x=2, n_y=1.In certain embodiments, nx=3, n_y=1.In certain embodiments, nx=3, n_y=2.In certain embodiments, nx=4, n_y=2.

In certain embodiments, along the first dimension being marked as x, a number n_x optical system can be adopted, i.e. video camera; And along being marked as second dimension of y, a number n_y video camera can be adopted.In certain embodiments, the image from multiple video camera can be combined, to provide the visual field larger than the individual visual field as at least one in the video camera of part.In certain embodiments, n_x is not equal to n_y.In certain embodiments, n_x=2, n_y=1.In certain embodiments, nx=3, n_y=1.In certain embodiments, nx=3, n_y=2.In certain embodiments, nx=4, n_y=2.

In certain embodiments, the image sensor IC forming many arrays or multiple ic imaging system can be selected from following set:

The imageing sensor of frontlighting;

The imageing sensor of back lighting;

Adopt the imageing sensor of the optical sensitive layer of the metal electrode be electrically coupled in the imageing sensor of frontlighting;

Adopt the imageing sensor of the optical sensitive layer of the metal electrode be electrically coupled in the imageing sensor of back lighting;

Adopt the imageing sensor of the optical sensitive layer of the silicon diode be electrically coupled in the imageing sensor of frontlighting; And

Adopt the imageing sensor of the optical sensitive layer of the silicon diode be electrically coupled in the imageing sensor of back lighting.

In certain embodiments, array can adopt the pixel with different size.In certain embodiments, primary array can adopt 1.4 μm of x1.4 μm of pixels, and secondary array can adopt 1.1 μm of x1.1 μm of pixels.

In certain embodiments, array can comprise the pixel with different size.In one exemplary embodiment, at least one pixel can have the linear-scale of 1.4 μm x1.4 μm, and at least one pixel on identical image sensor IC can have the linear-scale of 1.1 μm of x1.1 μm of pixels.

Pixel Dimensions in lateral dimensions can from be less than about 0.5 micron to 3 microns or be included in any scope wherein (from be less than about 0.5 to 3 microns square area or any scope of being included in wherein) change.In some instances, Pixel Dimensions can be less than about 1.3,1.4,1.5,1.7,2,2.2 or 2.5 microns (have be less than this quantity square area).Concrete example is 1.2 and 1.4 microns.Primary array can have the pixel being greater than secondary array.Primary array can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron, and is less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron.Described one or more secondary array also can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron and be less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron, but will be less than primary array.For example, primary array can be greater than X, and secondary array can be less than X, and wherein X is 1.2,1.4,1.5,1.7 or 2 etc.

In the exemplary embodiment, array A1 and A2 can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

The structure relevant with quantum dot pixel chip structure (QDPC) 100 according to exemplary embodiment and regional is shown referring again to Fig. 1, Fig. 1.As shown in fig. 1, QDPC 100 can be adapted to radiation 1000 receiver, wherein provides quantum-dot structure 1100 with receiver radiation 1000, such as light.QDPC 100 comprises quantum dot pixel 1800 and chip 2000, and wherein said chip is adapted to the signal of telecommunication that process is received from quantum dot pixel 1800.Quantum dot pixel 1800 comprises quantum-dot structure 1100, and quantum-dot structure 1100 comprises several assembly and sub-component, such as quantum dot 1200, quanta point material 200 and the customized configuration relevant with material 200 with point 1200 or quantum dot layout 300.Quantum-dot structure 1100 can be used to produce photodetector structure 1400, and wherein quantum-dot structure is associated with electrical interconnection 1404.There is provided electrical connection 1404 to receive the signal of telecommunication from quantum-dot structure, and the described signal of telecommunication is sent to the image element circuit 1700 be associated with dot structure 1500.Can be laid with vertical all styles of according to plane as quantum-dot structure 1100, photodetector structure 1400 can have specific photoelectric detector geometric layout 1402.Photodetector structure 1400 can be associated with dot structure 1500, and wherein the electrical interconnection 1404 of photodetector structure is associated with image element circuit 1700 in electric.Dot structure 1500 can also be laid in the pixel layout 1600 of the vertical and plane figure comprised on chip 2000, and image element circuit 1700 can be associated with other assemblies 1900, and other assemblies 1900 such as comprise memory.Image element circuit 1700 can comprise for the passive and active block in pixel 1800 level processing signals.Pixel 1800 machinery and electric in be all associated with chip 2000.From electric angle, image element circuit 1700 can communicate with other electronic installations (such as chip processor 2008).Other electronic installations described can be adapted to be processing digital signal, analog signal, mixed signal etc., and he can be adapted to be process and handle the signal being received from image element circuit 1700.In other embodiments, chip processor 2008 or other electronic installations can be included on the semiconductor substrate identical with QDPC, and can utilize system on chip framework to build.Chip 2000 also comprises physical structure 2002 and other functional units 2004, after also will be further described in more detail it.

QDPC 100 detects electromagnetic radiation 1000, and electromagnetic radiation 1000 can be the radiation of any frequency from electromagnetic spectrum in certain embodiments.Although electromagnetic spectrum is continuous print, but usually frequency range is called the frequency band in whole electromagnetic spectrum, such as radio bands, microwave band, infrared band (IR), visible frequency band (VIS), ultraviolet band (UV), X ray, gamma ray etc.QDPC 100 can sense any frequency in whole electromagnetic spectrum; But embodiment here can relate to special frequency band in electromagnetic spectrum or frequency band combination.Should be understood that, use these frequency bands to be not intended to limit QDPC 100 frequency range that can sense under discussion, and be only be used as example.In addition, some frequency bands have the common sub-band used, such as near-infrared (NIR) and far infrared (FIR), and the more wide in range frequency band term (such as IR) of use is not intended a QDPC 100 sensitiveness is restricted to any frequency band or sub-band.In addition, in description below, such as " electromagnetic radiation ", " radiation ", " electromagnetic spectrum ", " frequency spectrum ", " transmitted spectrum " etc. term can be used interchangeably, and term " color " is used to the selected frequency band describing the radiation 1000 that can be in any part of radiation 1000 frequency spectrum, and be not intended to any particular range being limited to radiation 1000, such as visible " color ".

In the exemplary embodiment shown in fig. 1, nano crystal material described above and photodetector structure can be used to be provided for the quantum dot pixel 1800 of photosensor arrays, imageing sensor or other opto-electronic devices.In the exemplary embodiment, pixel 1800 comprise can receiver radiation 1000 quantum-dot structure 1100, be adapted to be and receive from the photodetector structure of the energy of quantum-dot structure 1100 and dot structure.In certain embodiments, quantum dot pixel as described herein can be used to provide following characteristics: high fill factor, the potentiality of binning (bin), stacked potentiality, realize the potentiality of small pixel size, from the high-performance of larger Pixel Dimensions, simplify color filter array, eliminate demosaicing, from gain setting/automatic growth control, high dynamic range, global shutter ability, automatic exposure, local contrast, reading speed, the low noise of pixel level reads, use the ability of greater processing geometry (more low cost), use the ability of general manufacturing process, digital manufacturing process is used to carry out constructing analog circuit, other functions are added under pixel, such as memory, A to D, the two sampling of true correlation, binning etc.It is some or all of that exemplary embodiment can provide in these features.But some embodiments can not use these features.

Quantum dot 1200 can be nanostructure, and it is nanometer semiconductor structure normally, and retrains conduction band electron, valence band hole or exciton (binding of conduction band electron and valence band hole is to (bound pair)) in all three spatial directions.Quantum dot shows the effect of the discrete quantized power spectrum of idealized zero-dimensional system in its absorption spectra.Wave function corresponding to this discrete power spectrum is spatially localised in described quantum dot usually substantially, but extends on many cycles of the lattice of material.

Figure 36 shows an example of quantum dot 1200.In one exemplary embodiment, QD 1200 has the core 1220 of semiconductor or compound semiconductor materials, such as PbS.Ligand (ligand) 1225 can be attached to part or all of outer surface, or can be removed in certain embodiments, as further describing below.In certain embodiments, the core 1220 of contiguous QD can merge, thus forms the continuous film with the nano crystal material of nanoscale features.In other embodiments, each core can be connected to each other by connecting molecule (linker molecule).

Some embodiments of QD optics are the single image sensor chips with multiple pixel, and wherein each pixel comprises the QD layer for radiation 1000 sensitivity (such as optically active), and with at least two electrodes of QD layer electric connection.Electric current between described electrode and/or voltage relevant with the amount of the radiation 1000 received by QD layer.Specifically, the photon that absorbed by QD layer generates electron-hole pair, if thus apply electrically biased, then have current flowing.By determining the electric current and/or the voltage that correspond to each pixel, the image across chip can be rebuild.Described image sensor chip has: detect at Low emissivity the high sensitivity that in 1000 application, possibility is useful; Allow the wide dynamic range of superior image detail; And small pixel size.By utilizing the quantum size effect in QD, the responsiveness of tuned sensor chip for different optical wavelength can also be carried out by the size changing the QD in device.Pixel can be made little of 1 square micron or less, such as 700x700nm, or large to 30x30 micron or larger, or be included in any scope wherein.

In the exemplary embodiment, photodetector structure 1400 is configured to the device that it can be used to detect radiation 1000.By the type of the quantum-dot structure 1100 of use in photodetector structure 1400, can be the wavelength of the defined detecting radiation 1000 detector " tuning ".Photodetector structure can be described as the quantum-dot structure 1100 with I/O, this is because be applied with the state that certain input/output capabilities visits quantum-dot structure 1100.Once can reading state, just by electrical interconnection 1404, described state can be sent to image element circuit 1700, wherein image element circuit can comprise the electronic installation (such as passive and/or active) reading described state.In one embodiment, photodetector structure 1400 can be quantum-dot structure 1100(such as film) add electrical contact liner, thus described liner can be associated with electronic installation to read the state of the quantum-dot structure be associated.

In certain embodiments, process can comprise carries out binning to pixel, to reduce and the build-in attribute of quantum-dot structure 1100 or the random noise that is associated with readout.Binning can relate to packed-pixel 1800, such as produces the super pixel of 2x2,3x3,5x5 etc.The noise decrease be associated with packed-pixel 1800 or binning can be had, this is because along with area linear increase, random noise increases according to square root, thus decreases noise or improve effective sensitivity.In view of QDPC 100 is for the potentiality of very little pixel, can when not needing utilize binning when sacrificing spatial resolution, that is pixel can be so little to such an extent as to start to make packed-pixel can not reduce the requisite space resolution of system.Binning also may be effective improving in the speed that can run of detector, thus improves some features of system, such as focuses on or exposure.

In certain embodiments, described chip can have the functional unit allowing high speed readout ability, and it can promote the reading of the large array of such as 5,000,000 pixels, 6,000,000 pixels, 8,000,000 pixels, 12,000,000 pixels, 24,000,000 pixels etc. and so on.Readability may need more complicated, the more circuit of transistor size, the electrical interconnection of more multi-layered number, more more number, wider interconnect traces etc. under pixel 1800 array faster.

In certain embodiments, downscaled images size sensor may be wished, so that total chip cost that reduction may be proportional with chip area.Some embodiments comprise use lenticule.Some embodiments comprise the less procedure geometric structure of use.

In certain embodiments, can Pixel Dimensions be reduced when not reducing fill factor and thus reduce chip size.In certain embodiments, larger procedure geometric structure can be used, this is because transistor size and interconnect line widths, that cannot make pixel fuzzy because photoelectric detector place on the top and occupy interconnection top.In certain embodiments, the geometry of such as 90nm, 0.13 μm and 0.18 μm can be adopted when not fuzzy pixel.In certain embodiments, such as 90nm and following little geometry can also be adopted, and these can be the processes of standard instead of imageing sensor customization, thus cause lower cost.In certain embodiments, the use for little geometry can be more compatible with the high-speed digital video camera on identical chips.This can cause sooner, the process of more cheap and/or higher-quality chip epigraph transducer.In certain embodiments, more advanced geometry is used can to contribute to the more low power consumption of the imageing sensor processing capacity for given degree for Digital Signal Processing.

Pixel Dimensions in lateral dimensions can from be less than about 0.5 micron to 3 microns or be included in any scope wherein (be less than about 0.5 to 3 microns square area or any scope of being included in wherein) change.In some instances, Pixel Dimensions can be less than about 1.3,1.4,1.5,1.7,2,2.2 or 2.5 microns (have be less than this quantity square area).Concrete example is 1.2 and 1.4 microns.Primary array can have the pixel being greater than secondary array.Primary array can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron, and is less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron.Described one or more secondary array also can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron and be less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron, but will be less than primary array.For example, primary array can be greater than X, and secondary array can be less than X, and wherein X is 1.2,1.4,1.5,1.7 or 2 etc.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

Due to optical sensitive layer with on be present in integrated circuit the plane of separating to the reading circuit that the particular section of optical sensitive material reads, the shape of the optical sensitive section that therefore (look from top) (1) pixel readout circuit and (2) are read by (1) can be different usually.Such as may wish that the optical sensitive section corresponding to pixel is defined as square; And corresponding reading circuit can be configured to rectangle the most efficiently.

Based on be connected to by through hole below reading circuit top optical sensitive layer imaging array in, each metal level, through hole and interconnect dielectric are unnecessary is substantially or even partly optically transparent, but they can be transparent in certain embodiments.These are different from the situation of the cmos image sensor of frontlighting, must there is the optical path through the stacked substantial transparent of interconnection in the cmos image sensor of frontlighting.When traditional cmos image sensor, this gives additional constraint in the line arrangements of interconnection.This usually reduces the degree in fact can distributing one or more transistor.Such as usually adopt 4:1 share, and do not adopt higher share ratio.On the other hand, the reading circuit be designed for top surface optical sensitive layer can adopt 8:1 and 16:1 share.

In certain embodiments, optical sensitive layer can be electrically connected to the reading circuit of below, wherein between optical sensitive layer and the reading circuit of below, does not insert metal.

The embodiment of QD device comprises QD layer and Custom Design or the electronics that makes in advance reads integrated circuit.QD layer is directly formed into described Custom Design subsequently or the electronics that makes in advance reads on integrated circuit.In certain embodiments, cover circuit Anywhere at QD layer, it covers and one of them a little feature of contact circuit continuously.In certain embodiments, if QD layer covers the three-dimensional feature of circuit, then QD layer can with these feature conformals.In other words, read at the electronics of QD layer and lower floor the interface existing between integrated circuit and substantially adjoin.One or more electrode in circuit contacts with QD layer, and can the information relay about QD layer to reading circuit, and the information about QD layer is such as the electronic signal relevant with the amount of the radiation 1000 on QD layer.QD layer can be provided to cover whole lower circuit according to continuation mode, such as reading circuit, or it can be patterned.If provide QD layer according to continuation mode, then fill factor can close to about 100%, and for patterning situation, fill factor is reduced, but still can much larger than corresponding to typical 35% of some the exemplary cmos sensors using silicon photoelectric diode.

In certain embodiments, be easy to utilize be usually used to make conventional CMOS device facility in can technology to make QD optics.For example, such as can utilize the spin coating as standard CMOS procedure that one deck QD solution is applied (solution-coated) on the electronic reading circuits made in advance, and utilize other cmos compatible technology to process alternatively further, to provide the final QD layer be used in described device.Because QD layer does not need technology that is novel or difficulty to make, but standard CMOS procedure can be utilized make on the contrary, therefore can make QD optics in a large number, and not have the remarkable increase of the capital cost (except material) exceeding current C MOS process steps.

Two row that Figure 37 shows in the usually larger array of top surface electrode take advantage of three row sub-segments.The array of electric contact piece provides the tectal electric connection going to optical sensitive material.1401 represent the common electrode grid being used to provide the shared contact going to optical sensitive layer.1402 represent pixel electrode, and it is provided for another contact with optical sensitive layer electric connection.In certain embodiments, the voltage bias of-2V can be applied to common grid 1401, and the beginning can integrating the period at each applies the voltage of+2.5V to each pixel electrode 1402.

In certain embodiments, direct nonmetal contact section (such as the contact of pn knot) instead of metal interconnected pixel electrode can be used for 1402.

In view of Common contact 1401 is in single current potential in preset time across array, pixel electrode 1402 can change in Time and place across array.For example, if circuit is configured to make the biased of 1402 places change about flowing into or flow out the electric current of 1402, then, in the middle of the whole process integrating the period, different electrodes 1402 can be in different being biased.Section 1403 represents the contactless section be in lateral plane between 1401 and 1402.1403 normally insulating material, for being minimized in the dark current of flowing between 1401 and 1402.1401 and 1402 can be made up of different materials usually.Each material such as can be selected from such as following list: TiN; TiN/Al/TiN; Cu; TaN; Ni; Pt; And can have from list material above be superimposed upon another layer on one or all two contact or layer set, it selects in the middle of following material: Pt, alkyl hydrosulfide (alkanethiol), Pd, Ru, Au, ITO or other conduction or partially conductive material.

In the exemplary embodiment, pixel electrode 1402 can be made up of the semiconductor of such as silicon and so on (silicon comprises p-type or N-shaped silicon), instead of metal interconnected pixel electrode.

Each embodiment as described herein can be combined.Exemplary embodiment comprises the image element circuit adopting the pixel electrode be made up of semiconductor instead of the metal of such as silicon and so on.In certain embodiments, film can be formed be connected with direct between diode instead of metallic pixel electrodes (front or the back side).Other features as described herein can be used with this method or architecture combined.

In the exemplary embodiment of the structure in face before use, interconnection 1452 can form the electrode with the electric capacity on semiconductor substrate, impurity section or other charge storage storehouse electric connections.

In certain embodiments, described charge storage storehouse can be pinprick diode.In certain embodiments, described charge storage storehouse can be the pinprick diode be communicated with optical sensitive material, and there is not intermetallic metal between pinprick diode and optical sensitive layer.

In certain embodiments, voltage is applied to charge storage storehouse, and discharges due to the current flowing through optical sensitive film in an integrating time section.At the end of described integrating time section, remaining voltage is sampled, thus generate the signal corresponding to the luminous intensity absorbed by optical sensitive layer during integrating the period.In other embodiments, can be biased pixel section, thus in an integrating time section, voltage be accumulated in charge storage storehouse.At the end of described integrating time section, can sample to described voltage, thus generate the signal corresponding to the luminous intensity absorbed by optical sensitive layer during integrating the period.In some exemplary embodiments, due to electric discharge or the accumulation of the voltage at charge storage storehouse place, the biased of optical sensitive layer two ends may change in described integrating time section.This may cause also changing in described integrating time section through the current flow rate of optical sensitive material then.In addition, described optical sensitive material can be the nano crystal material with photoconductive gain, and described current flow rate can have non-linear relation with the luminous intensity absorbed by optical sensitive layer.Consequently, in certain embodiments, circuit can be used to the signal from pixel section to convert digital pixel data to, described digital pixel data with in the systemic luminous intensity of described integrating time section, there is linear relationship by pixel section.The non-linear attributes of optical sensitive material can be used to provide high dynamic range, and circuit can be used to carry out linearisation to signal, to provide digital pixel data after reading signal.Further describe below for the exemplary pixels circuit from pixel section read output signal.

Figure 37 A represent closed simple style 1430(such as concept diagram) and 1432(be such as used to generation photodetector structure through hole).In closed schematic representations 1430-1432, in the central area of square electrical interconnection 1450 comprising ground connection, provide positively biased electrical interconnection 1452.Square electrical interconnection 1450 can ground connection or can be in another reference potential, so that the optical sensitive material two ends in pixel section provide biased.For example, positive voltage can be utilized to carry out biasing interconnects 1452 and negative voltage can be utilized to carry out biasing interconnects, so that the nano crystal material two ends in pixel section in-between the electrodes provide desired voltage drop.In this configuration, produce electric charge when the radiation 1000 that described layer responds to it drops in described square area, and described electric charge attracted to center positive bias electrical interconnection 1452 and moves towards it.If copy these to close simple style on a region of described layer, then each is closed simple style and forms a part or whole pixel, and wherein said style catches the electric charge be associated with the incident radiation 1000 dropped on internal square area.In the exemplary embodiment, electrical interconnection 1450 can be a part for the grid forming the common electrode corresponding to a pixel section array.Every side of interconnection 1450 can be shared with contiguous pixel section, thus forms the part around the electrical interconnection of neighborhood pixels.In this embodiment, voltage on this electrode can for all pixel section (or for neighbor section each set) be identical, the voltage interconnected on 1452 then changes in integrating time section based on the luminous intensity absorbed by the optical sensitive material in pixel section, and can be read out thus generate the picture element signal corresponding to each pixel section.In the exemplary embodiment, interconnection 1450 can for the border of each pixel section formation around electrical interconnection 1452.Described common electrode can be formed on and interconnect on 1452 identical layers, and is placed around interconnection 1450 by side direction.In certain embodiments, described grid can be formed on above or below the optical sensitive material layer in pixel section, but the biased boundary condition that still can provide around pixel section on electrode, to reduce intersect (the cross over) with neighborhood pixels section.

In certain embodiments, described optical sensitive material can with pixel electrode, charge storage storehouse or the direct electric connection of pinprick diode, wherein there is not intermetallic metal at described optical sensitive material and between described pixel electrode, charge storage storehouse or pinprick diode.

Figure 37 B shows the simple style of opening of electrical interconnection.Open simple style does not form closed style usually.Region between the open unfavorable positive bias electrical interconnection 1452 of simple style and ground connection 1450 surrounds the electric charge produced as incident radiation 1000 result; But the electric charge produced in the region between described two electrical interconnections will attracted to positive bias electrical interconnection 1452 and move towards it.The array comprising open simple structure separately can provide charge separation system, and charge separation system can be used to the position of identification incident radiation 1000 and thus identify that corresponding pixel assigns (pixel assignment).As previously mentioned, electrical interconnection 1450 can be grounded or be in other reference potentials a certain.In certain embodiments, electrical interconnection 1450 can be electrically connected with the respective electrode of other pixels (such as by the interconnection layer of lower floor), therefore can apply voltage at pel array two ends.In other embodiments, interconnection 1450 can extend linearly across multiple pixel section, thus forms the common electrode across a row or column.

The image element circuit that can be used to from pixel section read output signal will be described now.As already described above, in certain embodiments, the dot structure 1500 in the QDPC 100 of Fig. 1 can have pixel layout 1600, and wherein pixel layout 1600 can have the multiple layout configurations such as such as vertical, plane, diagonal.Dot structure 1500 can also have embedded image element circuit 1700.Dot structure can also be associated with the electrical interconnection 1404 between photodetector structure 1400 and image element circuit 1700.

In certain embodiments, quantum dot pixel 1800 in the QDPC 100 of Fig. 1 can have image element circuit 1700, and image element circuit 1700 can be embedded in or specific to 1800, the one group of quantum dot pixel 1800 of the individual quantum dot pixel in pel array, all quantum dot pixels 1800 etc.Different quantum dot pixel 1800 in the array of quantum dot pixel 1800 can have different image element circuits 1700, or can not have individual pixel circuit 1700 completely.In certain embodiments, image element circuit 1700 can provide multiple circuit, such as biased, voltage bias, current offset, Charger transfer, amplifier, replacement, sampling and maintenance, address logic, decoder logic, memory, TRAM unit, flash cell, gain, simulation summation, analog to digital conversion, resistance bridge etc.In certain embodiments, image element circuit 1700 can have multiple function, such as reading, sampling, correlated-double-sampling, subframe sampling, regularly, integrations, summation, gain control, automatic growth control, offset adjusted, calibration, side-play amount regulate, memory storage, frame cushions, dark current subtracts each other, binning etc.In certain embodiments, image element circuit 1700 can have the electrical connection of other circuit gone in QDPC 100, is such as wherein arranged at least one of them other circuit of the following: other features 2204 of the circuit of the functional unit 2004 of the second quantum dot pixel 1800, column circuits, row circuit, QDPC 100 or the integrated system 200 of QDPC 100 etc.The design flexibility be associated with image element circuit 1700 can provide product improvement widely and technological innovation.

Image element circuit 1700 in quantum dot pixel 1800 can take various ways, and its scope is from not having circuit completely, only having the circuit of the functions such as interconnect electrode is such as biased to providing, replacement, buffering, sampling, conversion, addressing, memory.In certain embodiments, the electronic installation in order to regulate or to process the signal of telecommunication can be placed and configure in several ways.For example, can each pixel, pixel groups place, in the end of each column or row, after array is left in signal transfer, just when signal transfer being left chip 2000 before etc. implement the amplification of signal.In another example, can each pixel, pixel groups place, in the end of each column or row, in the functional unit 2004 of chip 2000, signal transfer leave chip 2000 after etc. provide analog to digital to change.In addition, can implement the process of any level in each step, the part wherein processed is implemented a position, and the Part II of process is implemented in another position.An example can be implement analog to digital conversion in two steps, the simulation combination at such as pixel 1800 place, and changes as the analog to digital of the higher rate of a part for the functional unit 2004 of chip 2000.

In certain embodiments, different electrical arrangement may need reprocessing in various degree, such as to compensate this fact of the calibrated horizontal be associated with the reading circuit of each pixel that each pixel has himself.QDPC 100 can provide calibration, gain control, memory function etc. for the reading circuit at each pixel place.Due to the structure that the height of QDPC 100 is integrated, the circuit being in quantum dot pixel 1800 and chip 2000 level can be available, and it can allow QDPC 100 to be whole image sensor systems on chip.In certain embodiments, the quanta point material 200 that QDPC 100 can also be combined by the conventional semiconductors technology with such as CCD and CMOS and so on is formed.

Image element circuit may be defined as and is included in the electrode place contacted with quanta point material 200 and starts and the assembly terminated when signal or information transfer to other treatment facilities from pixel, the functional unit 2004 of such as lower layer chip 200 or another quantum dot pixel 1800.Electrode place on quanta point material 200 starts, and signal is translated or reads.In certain embodiments, quanta point material 200 can provide the change of current flowing in response to radiation 1000.Quantum dot pixel 1800 may need biasing circuit 1700 to produce readable signal.This signal can be exaggerated and select for reading subsequently then.

In certain embodiments, when photoelectric detector biased can be constant or time become.Change room and time and can reduce crosstalk, and allow quantum dot pixel 1800 to narrow down to less size, and need the connection between quantum dot pixel 1800.Can by implementing to be biased in the corner of pixel 1800 and middle some place ground connection.Biased can only to occur when implementing to read, thus realize contiguous pixel 1800 there is no field, force in contiguous pixel 1800 identical biased, first read odd column and read even column etc. subsequently.Can also between pixel 1800 shared electrode and/or biased.Be biased and can be implemented to voltage source or current source.Can voltage be applied at the pixel two ends of some but sense separately subsequently, or as single large biased a string pixel 1800 two ends be applied on the diagonal.Current source along a line drive current, can be read subsequently on row.Involved current level can be improved like this, thus reading noise level can be reduced.

In certain embodiments, by using bias scheme or the configuration of voltage bias, the configuration of described field can produce isolation between the pixels.Electric current can flow in each pixel, thus makes only have the electron-hole pair generated in this pixel volume to flow in this pixel.Can allow to implement pixel separation for electrostatically when there is no physical separation like this to reduce from crosstalk.This can interrupt physical isolation reduce with crosstalk between associate.

In certain embodiments, image element circuit 1700 can comprise the circuit read for pixel.Pixel read can relate to a kind of circuit, this circuit read signal from quanta point material 200 and described signal is transferred to other assemblies 1900, chip functions assembly 2004, transfer to integrated system 2200 other features 2204 or transfer to other chip component.Pixel readout circuit can comprise quanta point material 200 interface circuit, such as such as 3T and 4T circuit.Pixel reads to relate to and reads the different modes of picture element signal, the different modes converted picture element signal, voltage of applying etc.Pixel reads may need the metal contact element with the some of quanta point material 200, such as 2,3,4,20 etc.In certain embodiments, pixel reads can relate to optical sensitive material and the direct electric connection between pixel electrode, charge storage storehouse or pinprick diode, wherein there is not intermetallic metal at described optical sensitive material and between described pixel electrode, charge storage storehouse or pinprick diode.

These electric contact pieces can be customized configuration for size, barrier degree (degree of barrier), electric capacity etc., and can relate to other electric assemblies of such as Schottky contact and so on.Pixel readout times can continue how long (such as reach several milliseconds or several microseconds) with the electron-hole pair that radiation 1000 causes relevant.In certain embodiments, this time can be associated with quanta point material 200 process steps, such as changes persistence, gain, dynamic range, noise efficient etc.

Quantum dot pixel 1800 as described herein can be arranged in multiple pixel layout 1600.Such as with reference to Figure 38 A to 38P, traditional pixel layout 1600(such as Bayer filter layout 1602) comprise layout group pixels in one plane, wherein different pixels is responsive for the radiation 1000 of different colours.In traditional imageing sensor, such as be used in those imageing sensors in most of consumer digital photography machine, by using the chromatic filter be arranged in above lower floor's photoelectric detector, make pixel responsive for the different colours of radiation 1000, thus make photoelectric detector generate signal in response to the radiation 1000 of particular frequency range or color.In this configuration, the piecing together of pixel of different colours is usually referred to as color filter array or chromatic filter is pieced together.Although different styles can be used, but most typical style is the Bayer filter style 1602 shown in Figure 38 A, wherein use two green pixels, a red pixel and blue pixel, wherein green pixel (it is usually referred to as briliancy senser) is positioned on a foursquare diagonal, and redness and blue pixel (it is usually referred to as colourity senser) are positioned on another diagonal.Use for the second green pixel is used to simulation human eye to the sensitiveness of green light.Because the undressed output of the sensor array in Bayer style is made up of the style of signal, wherein each signal corresponds to the light of only a kind of color, therefore uses demosaicing algorithm to carry out interpolation to the redness of every bit, green and blue values.Different algorithms causes the different quality of final image.Various algorithm can be applied by the computing element on video camera or by the image processing system of the separation being in video camera outside.Quantum dot pixel can be laid in traditional chromatic filter system style of such as Bayer RGB style and so on; But also can use other styles of the light being more suitable for the larger quantity of transmission, such as blue-green, magenta, yellow (CMY).Usually know that redness, green, blueness (RGB) chromatic filter system can the more light of absorptance CMY system.Incorporating quantum point pixel can also use more advanced system, such as RGB blue-green (RGB Cyan) or RGB transparent (RGB Clear).

In one embodiment, quantum dot pixel 1800 as described herein is configured in piecing together of imitation Bayer style 1602; But replace and use chromatic filter, quantum dot pixel 1800 can be configured to respond to the radiation 1000 with selected color or color-set when not using chromatic filter.Therefore, the Bayer style 1602 in an embodiment situation comprises the set of the quantum dot pixel 1800 of green sensitive, red sensitive and blue-sensitive.In certain embodiments, due to the radiation 1000 not using filter to carry out filtering different colours, therefore the radiation 1000 seen of each pixel is more.

Imageing sensor can detect the signal from the light-sensitive material in each pixel section, and this signal changes based on the luminous intensity be incident on described light-sensitive material.In one exemplary embodiment, described light-sensitive material is the continuous film of interconnect nanoparticles.Electrode is used to apply at each pixel region two ends to be biased.Image element circuit be used to for each pixel section in certain hour section signal integration in charge storage storehouse.Described circuit stores the signal of telecommunication proportional with the luminous intensity be incident on during integrating the period on optical sensitive layer.Can the described signal of telecommunication be read from image element circuit and process subsequently, to construct the digital picture corresponding to the light be incident on pixel element array.In the exemplary embodiment, in integrated circuit (IC)-components, image element circuit can be formed below light-sensitive material.For example, can in CMOS integrated circuit (IC)-components lamination nanocrystal light-sensitive material, thus formed imageing sensor.Metal contact layer from CMOS integrated circuit can be electrically connected to and provide biased electrode at pixel section two ends.The title submitted on April 18th, 2008 is the U.S. Patent Application Serial Number 12/106 of " Materials; Systems and Methods for Optoelectronic Devices ", 256(US publication application number 2009/0152664) comprise additional description for opto-electronic device, system and the material that can use in combination with exemplary embodiment, and be incorporated in this in full with for referencial use thus.This is only an exemplary embodiment, and other embodiments can use different photoelectric detectors and light-sensitive material.For example, some embodiments can use silicon or GaAs (GaAs) photoelectric detector.

In the exemplary embodiment, the pixel element of big figure can be provided, to provide high-resolution for imageing sensor.For example, the array with 4,6,8,12,24 or more million pixels can be provided.

Use for the pixel element of such big figure is combined with the needs of image sensor IC production to small size (such as the Diagonal Dimension of about 1/3 inch or 1/4 inch), inevitable with using less individual pixel.The pixel geometry meeting expectation such as comprises 1.75 μm of linear lateral dimension, 1.4 μm of linear lateral dimension, 1.1 μm of linear lateral dimension, 0.9 μm of linear lateral dimension, 0.8 μm of linear lateral dimension and 0.7 μm of linear lateral dimension.

Pixel Dimensions in lateral dimensions can from be less than about 0.5 to 3 microns or be included in any scope wherein (be less than about 0.5 to 3 microns square area or any scope of being included in wherein) change.In some instances, Pixel Dimensions can be less than about 1.3,1.4,1.5,1.7,2,2.2 or 2.5 microns (and have be less than this quantity square area).Concrete example is 1.2 and 1.4 microns.Primary array can have the pixel being greater than secondary array.Primary array can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron, and is less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron.Described one or more secondary array also can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron and be less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron, but will be less than primary array.For example, primary array can be greater than X, and secondary array can be less than X, and wherein X is 1.2,1.4,1.5,1.7 or 2 etc.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

Some embodiments comprise the system realizing large fill factor, this be by guarantee each pixel 100% or close to 100% area comprise optical sensitive material realize, the interested light be incident on when imaging on described optical sensitive material is absorbed substantially.The chief ray (chief ray) that some embodiments comprise provides large accepts the imaging system at angle.Some embodiments comprise does not need lenticular imaging system.Some embodiments comprise following imaging system: this imaging system is less sensitive for lenticular concrete placement (lenticule skew) due to its larger fill factor.Some embodiments comprise extremely sensitive imageing sensor.Some embodiments comprise imaging system, and the ground floor wherein near optics light incident side absorbs incident light substantially; And the semiconductor circuit that wherein can comprise transistor implements electronics read out function.

Some embodiments comprise optical sensitive material, and absorb comparatively strong in this optical sensitive material, that is absorption length is shorter, is such as less than the absorption length (1/ α) of 1 μm.Some embodiments comprise imageing sensor, described imageing sensor comprises optical sensitive material, is all absorbed in the optical sensitive material thickness being less than approximate 1 micron in optical sensitive material across substantially all light of visible wavelength spectrum (being outwards included in red approximately 630nm).

Some embodiments comprise imageing sensor, and in imageing sensor, the lateral space yardstick of pixel is approximate 2.2 μm, 1.75 μm, 1.55 μm, 1.4 μm, 1.1 μm, 900nm, 700nm, 500nm; And wherein optical sensitive layer is less than 1 μm and substantially absorbs the light (visible ray in such as exemplary embodiment) across interested spectral region; And the crosstalk (optics of combination and electrical crosstalk) wherein between neighborhood pixels is less than 30%, is less than 20%, is less than 15%, be less than 10%, or be less than 5%.

Pixel Dimensions in lateral dimensions can from be less than about 0.5 to 3 microns or be included in any scope wherein (be less than about 0.5 to 3 microns square area or any scope of being included in wherein) change.In some instances, Pixel Dimensions can be less than about 1.3,1.4,1.5,1.7,2,2.2 or 2.5 microns (have be less than this quantity square area).Concrete example is 1.2 and 1.4 microns.Primary array can have the pixel being greater than secondary array.Primary array can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron, and is less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron.Described one or more secondary array also can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron and be less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron, but will be less than primary array.For example, primary array can be greater than X, and secondary array can be less than X, and wherein X is 1.2,1.4,1.5,1.7 or 2 etc.

Some embodiments comprise the image element circuit operated with optical sensitive material combinedly, measure wherein by optical sensitive material and image element circuit being integrated, at least one item in the middle of dark current, noise, photoresponse nonuniformity and dark current inhomogeneities is minimized.

Some embodiments comprise the low fringe cost realization with manufacture view and can make in factory the integrated and processing method realizing (or substantially or partly realizing) at CMOS silicon.

Figure 39 A depicts the cmos image sensor pixel of frontlighting, and wherein optical sensitive material has been integrated into and silicon diode close contact.601 silicon substrates depicting making image transducer thereon.603 depict the diode be formed in silicon.605 is metal interconnected, and 607 be used within integrated circuit stacked with the interlayer dielectric providing the signal of telecommunication to be communicated with across integrated circuit.609 is that be in will the optical sensitive material of main positions of light of imaging for absorbing.611 is transparency electrodes, and it is used to provide the electrically biased of optical sensitive material, to allow therefrom to carry out photocarrier collection.613 is passivation layers, its can by the inorganic matter of organic or polymeric sealant (such as Parylene) or such as Si3N4 and so on or merge they combination stacked in the middle of at least one form.613 are used for protecting subsurface material and circuit from environmental impact, the impact of such as water or oxygen.615 is color filter array layers, and it is the spectral selection optical transmitter being used to help to realize colour imaging.617 is lenticules, and its help focuses light onto on 609 optical sensitive materials.

With reference to Figure 39 A, in certain embodiments, with high efficiency, the photoelectric current generated in 609 optical sensitive materials due to illumination can be transferred to diode ' 2 ' from sensitized material 609.Absorb because most of incident photon will be sensitized material ' 5 ', therefore diode 603 no longer needs the role serving as leading Photoelectric Detection.On the contrary, its premiere feature serves as the diode allowing maximum charge transfer and minimum dark electric current.

With reference to Figure 39 A, diode 603 can utilize sensitized material 609 to carry out pinprick (pinned) in its surface.The thickness of sensitized material 609 can be approximate 500nm, and its scope can be from 100nm to 5 μm.In certain embodiments, p-type sensitized material 609 can be adopted for light conversion operations, and for exhausting N-shaped silicon diode 603.Knot between sensitized material 609 and silicon diode 603 can be referred to as p-n heterojunction in this embodiment.

With reference to Figure 39 A, when not electrically being biased, N-shaped silicon 603 and p-type sensitized material 609 reach balance, and that is its Fermi level is formed and aims at.In one exemplary embodiment, the band curvature (band-bending) obtained produces built in potential in p-type sensitized material 609, thus formation exhausts section wherein.When apply in silicon circuit suitable biased time (such as applying this potential difference by the difference between 611 in Figure 39 A and 603), the amplitude of this current potential is strengthened by the current potential being applied, thus causes described depletion region to be deepened thus arrive in p-type sensitized material 609.The electric field obtained causes photoelectron to extract n+ silicon layer 603 from sensitized material 609.Biased and doping in silicon 603 realizes collecting photoelectron from sensitizing layer 609, and can realize exhausting completely of N-shaped silicon 603 under normal bias (such as normal range (NR) be 1V to 5V situation under 3V).By the second contact (in such as Figure 39 A 611), sensitizing layer 609 is extracted in hole.

With reference to Figure 39 A, when vertical devices, contact 611 can be formed on sensitized material 609 pushes up.

Figure 39 B depicts the cmos image sensor pixel of frontlighting, and wherein optical sensitive material has been integrated into and silicon diode close contact.631 silicon substrates depicting making image transducer thereon.633 depict the diode be formed in silicon.639 is metal interconnected, and 637 are used within integrated circuit with provide the interlayer dielectric be communicated with of the signal of telecommunication across integrated circuit stacked.641 is that be in will the optical sensitive material of main positions of light of imaging for absorbing.643 is transparency electrodes, and it is used to provide the electrically biased of optical sensitive material, to allow therefrom to carry out photocarrier collection.645 is passivation layers, its can by the inorganic matter of organic or polymeric sealant (such as Parylene) or such as Si3N4 and so on or merge they combination stacked in the middle of at least one form.645 are used for protecting subsurface material and circuit from environmental impact, the impact of such as water or oxygen.647 is color filter array layers, and it is the spectral selection optical transmitter being used to help to realize colour imaging.649 is lenticules, and its help focuses light onto on 641 optical sensitive materials.635 is occupy the material between optical sensitive material 641 and diode 633.635 can be referred to as interpolation pinprick layer.Exemplary embodiment comprises p-type silicon layer.Exemplary embodiment comprises the nonmetallic materials of such as semiconductor and so on, and/or it can comprise polymer and/or organic material.In certain embodiments, material 635 can provide to be had enough conductivity and flow to the path of diode to make electric charge from optical sensitive material, but will not be metal interconnected.In certain embodiments, 635 surfaces being used for diode passivation, and produce the pinprick diode (instead of the optical sensitive material that will be on this extra play top) in this exemplary embodiment.

With reference to Figure 39 C, the device of side direction substantially can be formed, wherein can adopt the electrode that the silicon 661 occupy below sensitized material 659 pushes up.In certain embodiments, metal or other conductors (such as TiN, TiOxNy, Al, Cu, Ni, Mo, Pt, PtSi or ITO) can be utilized to form electrode 661.

With reference to Figure 39 C, the device of side direction substantially can be formed, wherein can adopt and occupy p doped silicon 661 below sensitized material 659 for biased.

Exemplary embodiment provides the imageing sensor using pixel element array to carry out detected image.Described pixel element can comprise light-sensitive material, it is also referred to as sensitized material here, corresponding to 1103 in 1003 and Figure 61 A to 61F in 903 in the filled ellipse shape in 709 in 659 in 641 in 609 in Figure 39 A, Figure 39 B, Figure 39 C, Figure 39 A, light 801 incidence Figure 41 thereon, Figure 59, Figure 60.In further detail Figure 59 and 61A to 61F is discussed below.

Figure 39 C depicts the cmos image sensor pixel of frontlighting, and wherein optical sensitive material has been integrated into and silicon diode close contact.In this embodiment, optical sensitive material is directly biased by silicon substrate; Consequently, in this embodiment, transparency electrode is not needed atop.651 silicon substrates depicting making image transducer thereon.653 depict the diode be formed in silicon.655 is metal interconnected, and 657 are used within integrated circuit with provide the interlayer dielectric be communicated with of the signal of telecommunication across integrated circuit stacked.659 is that be in will the optical sensitive material of main positions of light of imaging for absorbing.The exemplar section of 661 sensing silicon substrates 651, this section is used to provide the electrically biased of optical sensitive material, to allow therefrom to carry out photocarrier collection.663 is passivation layers, its can by the inorganic matter of organic or polymeric sealant (such as Parylene) or such as Si3N4 and so on or merge these combination stacked in the middle of at least one form.663 are used for protecting subsurface material and circuit from environmental impact, the impact of such as water or oxygen.665 is color filter array layers, and it is the spectral selection optical transmitter being used to help to realize colour imaging.667 is lenticules, and its help focuses light onto on 659 optical sensitive materials.

Figure 40 A depicts the section of the cmos image sensor pixel of back lighting, and wherein optical sensitive material has been integrated into and silicon photoelectric diode close contact.705 silicon substrates depicting making image transducer thereon.707 depict the diode be formed in silicon.703 is metal interconnected, and 701 are used within integrated circuit with provide the interlayer dielectric be communicated with of the signal of telecommunication across integrated circuit stacked.709 is that be in will the optical sensitive material of main positions of light of imaging for absorbing.711 is transparency electrodes, and it is used to provide the electrically biased of optical sensitive material, to allow therefrom to carry out photocarrier collection.713 is passivation layers, its can by the inorganic matter of organic or polymeric sealant (such as Parylene) or such as Si3N4 and so on or merge they combination stacked in the middle of at least one form.713 are used for protecting subsurface material and circuit from environmental impact, the impact of such as water or oxygen.715 is color filter array layers, and it is the spectral selection optical transmitter being used to help to realize colour imaging.717 is lenticules, and its help focuses light onto on 709 optical sensitive materials.

Figure 40 B depicts the section of the cmos image sensor pixel of back lighting, and wherein optical sensitive material has been integrated into and silicon photoelectric diode close contact.735 silicon substrates depicting making image transducer thereon.737 depict the diode be formed in silicon.733 is metal interconnected, and 731 are used within integrated circuit with provide the interlayer dielectric be communicated with of the signal of telecommunication across integrated circuit stacked.741 is that be in will the optical sensitive material of main positions of light of imaging for absorbing.743 is transparency electrodes, and it is used to provide the electrically biased of optical sensitive material, to allow therefrom to carry out photocarrier collection.745 is passivation layers, its can by the inorganic matter of organic or polymeric sealant (such as Parylene) or such as Si3N4 and so on or merge they combination stacked in the middle of at least one form.745 are used for protecting subsurface material and circuit from environmental impact, the impact of such as water or oxygen.747 is color filter array layers, and it is the spectral selection optical transmitter being used to help to realize colour imaging.749 is lenticules, and its help focuses light onto on ' 5 ' optical sensitive material.739 is occupy the material between optical sensitive material 741 and diode 737.739 can be referred to as interpolation pinprick layer.Exemplary embodiment comprises p-type silicon layer.Exemplary embodiment comprises the nonmetallic materials of such as semiconductor and so on, and/or it can comprise polymer and/or organic material.In certain embodiments, material 739 can provide to be had enough conductivity and flow to the path of diode to make electric charge from optical sensitive material, but will not be metal interconnected.In certain embodiments, 739 surfaces being used for diode passivation, and produce the pinprick diode (instead of the optical sensitive material that will be on this extra play top) in this exemplary embodiment.

Figure 41 is the circuit diagram of the imageing sensor corresponding to back lighting, and wherein optical sensitive material is integrated into silicon from the back side.801 light depicting light optics sensitive material (there is the filling circle of the arrow pointing to below).The 803 biased electrodes being to provide optical sensitive material two ends.It corresponds to top transparent electrode (711 of Figure 40 A), or corresponding to being used to the section (743 of Figure 40 B) providing the silicon substrate be electrically biased.805 is silicon diode (corresponding respectively in Figure 39 A, 39B, 39C, 40A and 40B 603,633,653,707 and 737).805 also can be referred to as charge storage storehouse.805 can be referred to as pinprick diode.807 is the electrodes (metal) in silicon front, and it is connected to the transistor gate of M1.809 is transistor M1, and its described diode separates with the remainder of sense node and reading circuit.The grid of this transistor is 807.Transfer signal is applied to this grid, so as between diode and sense node 811 transfer charge.811 is sense node.It separates with diode, thus allows the flexibility of readout scheme.813 is the electrodes (metal) in silicon front, and it is connected to the transistor gate of M2.815 is the electrodes (metal) in silicon front, and it is connected to the transistor drain of M2.815 can be referred to as reference potential.815 can be provided for the VDD reset.817 is transistor M2, and it serves as replacement device.It is used to initialization sense node before reading.It is also used to initialization diode (when being all opened as M1 and M2) before integration.The grid of this transistor is 813.Reset signal is applied to this grid, to reset sense node 811.819 is transistor M3, and it is used to read sense node voltage.821 is transistor M4, and it is used to pixel to be connected to read bus.823 is the electrodes (metal) in silicon front, and it is connected to the grid of M4.When it is high, pixel driver read bus vcol.825 is read bus vcol.801 and 803 and 805 occupy in the back side of silicon.807-825 occupy in the front of silicon, comprises metal stacking and transistor.

With reference to Figure 41, comprise diagonal to help to describe back side implementation.Transistor on the right side of this line will be formed on front.Diode and the optical sensitive material in left side will be in the back side.Diode will extend through substrate from the back side and close to front.This allows to be formed between the transistor in front to connect, so that sense node 811 transfer charge from diode to image element circuit.

With reference to Figure 41, image element circuit may be defined as the set of all circuit elements in this figure, except optical sensitive material.Described image element circuit comprises reading circuit, and the latter comprises source follower transistor 819, has row selecting transistor 821 and row reading 825 that row selects grid 823.

With reference to Figure 42, in certain embodiments, image element circuit can operate in such a way.

Implement first and reset (operation 4201 place of Figure 42), to reset sense node (from 811 of Figure 41) and diode (from 805 of Figure 41) before integration.Reset transistor (from 817 of Figure 41) and charge transfer transistor (from 809 of Figure 41) open circuit during first resets.So just sense node (from 811 of Figure 41) is reset to reference potential (such as 3 volts).Diode is fixed to fixed voltage when it exhausts.What the fixed voltage that diode is fixed to can be referred to as diode exhausts voltage.Described replacement exhausts diode, and this resets the voltage (being such as reset to 1 volt) of diode.Because it is fixed, therefore it can not reach the voltage level identical with sense node.

Charge transfer transistor (from 809 of Figure 41) is closed subsequently (operation 4203 place of Figure 42), to start to integrate the period, integrates the period sense node and diode-isolated.

During integrating time section, electric charge is integrated (operation 4205 of Figure 42) in diode by from optical sensitive material.The electrode of biased optical sensitive film is in the voltage (such as 0 volt) lower than diode, thus there is voltage difference at described material two ends, and electric charge integration is to diode.It is integrated that electric charge contacts section by described material and nonmetal between diode.In certain embodiments, this is the knot that the n of optical sensitive material and diode adulterates between section.In certain embodiments, other non-metallic layers (such as p-type silicon) can be there are between optical sensitive material and diode.Make diode by pinprick with the interface of optical sensitive material, and by providing the surface of hole accumulation layer and passivation n doping section.Which reduces originally by the noise that generated by the silica be formed on the top surface of diode and dark current.

After the integration period, second of sense node resets (operation 4207 place of Figure 42) and just in time occurred before reading (reset transistor is opened, and diode keeps isolation simultaneously).Which provides the known starting voltage for reading, and eliminate the noise/leakage being incorporated into sense node during integrating the period.The two reset process read for pixel are referred to as the two sampling of true correlation.

Reset transistor is closed subsequently, and charge transfer transistor is open at (operation 4209 place of Figure 42), electric charge is transferred to sense node from diode, sense node is read out by source follower and alignment subsequently.

Referring again to Figure 39 A, use sensitized material 609 can provide the absorption length shorter than silicon across interested spectral region.Sensitized material can provide 1 μm and shorter absorption length.

With reference to Figure 39 A, the high efficiency shifted via the photocarrier of the reading integrated circuit of diode 603 from sensitized material 609 to below can be realized.

With reference to Figure 39 A, by optical sensitive material 609 via diode 603 and silicon reading circuit integrated, described system can realize minimum dark current and/or noise and/or photoresponse nonuniformity and/or dark current inhomogeneities.

With reference to Figure 39 A, the example of optical sensitive material 609 comprises the high-density film be made up of Colloidal Quantum Dots.Constituent material comprises PbS, PbSe, PbTe; CdS, CdSe, CdTe; Bi2S3, In2S3, In2Se3; SnS, SnSe, SnTe; ZnS, ZnSe, ZnTe.The diameter of nano particle can be within the scope of 1-10nm, and can be monodispersed substantially, that is can have substantially the same size and dimension.Described material can comprise organic ligand and/or crosslinking agent to help surface passivation, and has the length and conductivity that combine and promote Charger transfer between quantum dot.

With reference to Figure 39 A, the example of optical sensitive material 609 comprises the film be made up of the organic material in some or all of interested wave-length coverage interior focusing with strong absorption.Constituent material comprises P3HT, PCBM, PPV, MEH-PPV and copper phthalocyanine and relevant metal phthalocyanine.

With reference to Figure 39 A, the example of optical sensitive material 609 comprises the film be made up of inorganic material, and inorganic material is such as CdTe, copper indium gallium (di) selenium (CIGS), Cu2ZnSnS4(CZTS) or the III-V types of material of such as AlGaAs and so on.

With reference to Figure 39 A, optical sensitive material 609 can be directly integrated as follows with diode 603: which can reduce dark current among other benefits.The directly integrated dark current that can cause the minimizing be associated with the interface trap be positioned on Diode facets of optical sensitive material 609 and silicon diode 603.This concept can allow from diode to the Charger transfer completely substantially floating sense node, thus allows two sampling operations of true correlation.

With reference to Figure 39 A, 39B and 39C, corresponding sensitized material 609,641 and 659 can be integrated with the imageing sensor of frontlighting, and be used for strengthening its sensitivity and reduce its crosstalk.At sensitized material 609,641 and 659 with corresponding diode 603, realize between 633 and 653 being electrically connected.

With reference to Figure 40 A and 40B, corresponding sensitized material 709 and 741 can be integrated with the imageing sensor of back lighting, and be used for strengthening its sensitivity and reduce its crosstalk.First wafer top applies and after skiving second wafer, adds any other implant and surface treatment, provide substantially plane silicon face.Can sensitized material 709 and 741 and this material integrated.

Substantially the electrically biased of sensitized material can be realized on lateral or vertical direction.

With reference to Figure 39 A, it can be referred to as the bias conditions of perpendicular, and the biased of sensitized material 609 two ends is provided between diode 603 and top electrodes 611.In this case, wish that top electrodes 611 is transparent for the optical wavelength that will sense substantially.The example that can be used to the material forming top electrodes 611 comprises MoO3, ITO, the organic material of AZO, such as BPhen and so on and the very thin layer of the such as metalloid of aluminium, silver, copper, nickel etc.

With reference to Figure 39 B, it can be referred to as side direction or coplanar bias conditions substantially, and the biased of sensitized material 641 two ends is provided between diode 633 and silicon substrate electrode 639.

With reference to Figure 39 C, it can be referred to as partly side direction, partly vertical bias conditions, and the biased of sensitized material 659 two ends is provided between diode 653 and electrode 661.

Exemplary embodiment comprises image sensor system, and wherein zoom level or visual field are not select when original image is caught, but selects at image procossing or when selecting.

Some embodiments comprise: the first imageing sensor section or primary image sensor section, and its process exceeds the first sum of all pixels of at least 8 million pixels; And at least the second imageing sensor section, its process is less than the second sum of all pixels of 2,000,000 pixels.

Some embodiments comprise the system providing true optical zoom (different from electronics or digital zooming), and wherein total z is highly minimized.Some embodiments realize the system of true optical zoom when being included in the mechanical displacement means not using and such as may need in telephoto (telephoto) system.

Some embodiments comprise image sensor system, and it provides true optical zoom when not increasing unnecessary cost to image sensor system.

Some embodiments comprise a kind of file format, and it comprises at least two width composing images: the first image, corresponding to primary imaging section or visual field; And at least the second image, correspond to (in angular range) usually and be less than the second visual field of the first visual field.

Some embodiments comprise a kind of file format, and it comprises at least three width composing images: the first image, and it corresponds to primary imaging section or visual field; At least the second image, it corresponds to (in angular range) usually and is less than the second visual field of the first visual field; And the 3rd image, it corresponds to (in angular range) usually and is less than the second visual field of the first visual field.

Some embodiments comprise a kind of multiple aperture image sensor system, and it to be everyly made up of following: single IC for both; Image sensing sub-segments; And be less than the AD converter of some of number of image sensing sub-segments.

Some embodiments comprise a kind of multiple aperture image sensor system, and it to be everyly made up of following: single IC for both; Image sensing sub-segments; The area of wherein said image sensor IC is less than the area of the set realizing the identical discrete images transducer needed for total imaging area.

Some embodiments comprise a kind of image sensor IC, and it comprises: the pixel of at least two classifications; Wherein the first pixel class comprises the pixel with the first area; And the second pixel class comprises the pixel with second area; Wherein the area of the first pixel is different from the area of the second pixel.

In certain embodiments, the pixel of first category has area (1.4 μm of x1.4 μm of pixels), and other pixel of Equations of The Second Kind has area (1.1 μm of x1.1 μm).Pixel Dimensions in lateral dimensions can from be less than about 0.5 to 3 microns or be included in any scope wherein (be less than about 0.5 to 3 microns square area or any scope of being included in wherein) change.In some instances, Pixel Dimensions can be less than about 1.3,1.4,1.5,1.7,2,2.2 or 2.5 microns (have be less than this quantity square area).Concrete example is 1.2 and 1.4 microns.Primary array can have the pixel being greater than secondary array.Primary array can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron, and is less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron.Described one or more secondary array also can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron and be less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron, but will be less than primary array.For example, primary array can be greater than X, and secondary array can be less than X, and wherein X is 1.2,1.4,1.5,1.7 or 2 etc.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

In certain embodiments, image sensor system comprises multiple aperture imaging, wherein multiple lens still single integrated image sensor circuit enforcement multiple aperture imaging.

In certain embodiments, image sensor system comprises: the first imageing sensor section; Second imageing sensor section; Wherein the beginning of the integration period of each imageing sensor section is aligned (time alignment between each imageing sensor section or synchronism) in time in 1 millisecond.

In certain embodiments, image sensor system comprises: the first imageing sensor section; Second imageing sensor section; And the 3rd imageing sensor section; Wherein the beginning of the integration period of each imageing sensor section aims at (time alignment between each imageing sensor section or synchronism) in time in 1 millisecond.

In certain embodiments, image sensor system comprises: the first imageing sensor section; Second imageing sensor section; Wherein each imageing sensor section implements global electronic shutter, wherein during first time period, the electron charge that each accumulation in the middle of described at least two imageing sensor sections is proportional with the photon integrated flux in each pixel in each imageing sensor section; And during the second time period, each imageing sensor section extracts the electronic signal proportional with the electron charge accumulated in each pixel section in the integration period corresponding at it.

In certain embodiments, by adopting following characteristics to realize super-resolution: the first imaging section relative to the visual field of imaging with the first phase shift; There is the second imaging section of the second visual field; Wherein control described relative phase shift by applying electric field to the circuit of control second imaging section.

In certain embodiments, first or primary imaging section comprise the first number of pixels; And at least the second or secondary imaging section comprise the second number of pixels; Number of pixels wherein in secondary imaging section is 1/2 of the number of pixels in the first imaging section at the most.

In certain embodiments, image sensor system comprises: for implementing the circuit of global electronic shutter; And there is the pixel of the linear-scale being less than (1.4 μm of x1.4 μm of pixels).

In certain embodiments, by adopting following characteristics to realize super-resolution: the first imaging section relative to the visual field of imaging with the first phase shift; There is the second imaging section of the second visual field; Wherein control described relative phase shift by applying electric field to the circuit of control second imaging section.

In certain embodiments, the super-resolution through optimizing is realized by following steps: provide at least two imaging sections with certain phase shift; Described phase shift is determined by the image comparing described in utilization the given scenario that at least two imaging sections gather; And in response to the described relative phase shift more dynamically regulating two imaging sections, to optimize the super-resolution of realization by combining the information utilizing described two imaging sections to gather.

Some embodiments comprise fused images, and wherein the first imaging section realizes high spatial resolution; And the second imaging section (such as around the framework of described first imaging section) realizes comparatively low spatial resolution.

Some embodiments comprise image sensor system, and it comprises: the first camera module providing the first image; And (one or more) second second camera module of image is provided; Wherein the interpolation of the second camera module provides convergent-divergent.

Figure 43 shows an exemplary embodiment of multiple aperture convergent-divergent from the visual angle of pattern matrix.The rectangle comprising 202.01 is primary array.The ellipse comprising 202.01 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 202.01.The rectangle comprising 202.02 amplifies array.The ellipse comprising 202.02 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 202.02.

Figure 44 shows an exemplary embodiment of multiple aperture convergent-divergent from the visual angle of the scene of imaging.Rectangle 212.01 represents the scene parts be imaged onto on the primary array 202.01 of Figure 43.Rectangle 212.02 represents the scene parts be imaged onto on the amplification array 202.02 of Figure 43.

With reference to Figure 43, in one exemplary embodiment, primary array (or primary array) is 8,000,000 pel arrays comprising approximate 3266 pixels along its level (transverse direction) axle.Described imaging system projects to the scene corresponding to approximate 25 ° of visual fields on this array.This projection is represented by 212.01 of Figure 44.In this embodiment, each pixel in primary array takes into account the visual field of approximate 0.008 ° of scene.

Amplifying array (or secondary array) is also 8,000,000 pel arrays comprising approximate 3266 pixels along its level (transverse direction) axle.Described imaging system projects to the scene corresponding to approximate 25 °/3=8 ° visual field on this array.This projection is represented by 212.02 of Figure 44.In this embodiment, each pixel of amplifying in array takes into account the visual field of approximate 0.008 ° of scene/3=0.0025 °.

Primary array can comprise at least 4 to 12,000,000 pixels or be included in any scope (such as 4,6,8,10 or 12,000,000 pixel) wherein.For secondary array, show that it also can be identical size (4,6,8,10,12).In various embodiments, the secondary array of some (1 to 20 million pixels or any scope be included in wherein, particularly 1,2,4,6,8,10,12,14 or 16,000,000 pixels) can be had.Secondary array all can be less than 1 to 8 million pixels or be included in the primary array of any scope (such as 1,2,4,6 or 8,000,000 pixel) wherein.In certain embodiments, all secondary pattern matrixs can be identical sizes (and can be less than primary picture array).In other embodiments, the size of secondary array itself can change (such as it can change between 1,2 or 4,000,000 pixels).They can be polychrome or monochrome (particularly having the secondary array of multiple of two greens, a blueness and a redness and this ratio).In some instances, primary array can have 1x convergent-divergent, secondary array can by more times of amplifications (1.5x to 10x or any scope be included in wherein, particularly 2,3 or 4x convergent-divergent).In other embodiments, primary array can have the zoom level between the zoom level being in each secondary array.Primary array can have the convergent-divergent of x, and a secondary array can be half (0.5) x, and another can be 2x.Another example will be at least two secondary arrays reduced (1,2 or 4,000,000 pixel) of 1/4th (0.25) x and half (0.5) x, the primary array (2,4,8 or 12,000,000 pixel) of 1x convergent-divergent, and at least two secondary arrays (1,2 or 4,000,000 pixel) amplified.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

In this exemplary embodiment, in amplification array, realize 3x optical zoom.In amplification array, each pixel is responsible for 1/3 of the visual field in primary array.The area of overall imaging integrated circuit is approximate 2 times of the original required area when only employing has the single imaging section of equal resolution and Pixel Dimensions.Not damaged in image quality in primary array.

In the exemplary embodiment, the image gathered in each array can be captured in simultaneously.In the exemplary embodiment, can be captured in the image gathered in each array by means of global electronic shutter, initial time and the dwell time of the integration period in each pixel wherein in each array are approximately uniform.

In two array case, the process for the image utilizing multiple array to generate provides different zoom level.

Figure 45 describes a kind of method, and wherein first image sensor system gathers two width images.Subsequent picture sensing system is sent to graphic process unit view data.Graphic process unit selects wherein piece image to store subsequently.

With reference to Figure 45, in the exemplary embodiment, the width in the middle of two width images only can be stored.For example, the user of imaging system may indicate for reducing or the preference of amplification mode, and can only retain preferred image in this case.

Figure 46 describes a kind of method, and wherein first image sensor system gathers two width images.Subsequent picture sensing system is sent to graphic process unit view data.Graphic process unit generates the image of the data that can adopt from each imageing sensor subsequently.

With reference to Figure 46, in the exemplary embodiment, whole two width images can be sent to Graphics Processing Unit, and Graphics Processing Unit can use described Computer image genration to combine the image of the information comprised in two images.Graphics Processing Unit significantly can not change image in the section of only being caught image by primary imageing sensor.Graphics Processing Unit can provide more high-resolution section at the immediate vicinity of reported image, and wherein this section benefits from the information of the center combination being combined in Peripheral-array and the content by the report of amplification array.

Figure 47 describes a kind of method, and wherein first image sensor system gathers two width images.Image sensor system is sent to graphic process unit view data subsequently.Graphic process unit transmits each width in the middle of two width images subsequently to store.Sometime afterwards, graphic process unit generates the image of the data that can adopt from each imageing sensor subsequently.

With reference to Figure 47, in the exemplary embodiment, the user of imaging system may wish to be retained in afterwards select the option of zoom level sometime---comprise effective optical zoom level.In the exemplary embodiment, the view data gathered by each array segment can be made to can be used for follow-up image procossing application, for processing the image had desired by desired convergent-divergent afterwards based on the information be included in every piece image.

Figure 48 describes a kind of method, and wherein first image sensor system gathers two width images.Image sensor system is sent to graphic process unit view data subsequently.Graphic process unit transmits each width in the middle of two width images subsequently to store.Sometime afterwards, each width in the middle of two width images is sent to another device.Sometime afterwards, a certain device or system or application generate the image of the data that can adopt from each imageing sensor subsequently.

With reference to Figure 48, in the exemplary embodiment, the user of imaging system may wish to be retained in afterwards select the option of zoom level sometime---comprise effective optical zoom level.In the exemplary embodiment, the view data gathered by each array segment can be made to can be used for a certain device, for having the image desired by desired convergent-divergent based on the information processing be included in every piece image afterwards.

In certain embodiments, continuous print or the set close to continuous print zoom level option can be provided to user.User can carry out convergent-divergent minimum reducing in fact continuously between the zoom level of maximum amplification.

Figure 49 shows an exemplary embodiment of multiple aperture convergent-divergent from the visual angle of pattern matrix.The rectangle comprising 207.01 is primary array, and that is it is that maximum individual pixel changes into picture section.The ellipse comprising 207.01 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 1.The rectangle comprising 207.02 is the first Peripheral-array.The ellipse comprising 207.02 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 207.02.The rectangle comprising 207.03 is the second Peripheral-array.The ellipse comprising 207.03 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 207.03.

Figure 50 shows an exemplary embodiment of multiple aperture convergent-divergent from the visual angle of the scene of imaging.Rectangle 212.01 represents the scene parts be imaged onto on the primary array 207.01 of Figure 49.Rectangle 212.02 represents the scene parts be imaged onto on first Peripheral-array 207.02 of Figure 49.Rectangle 212.03 represents the scene parts be imaged onto on second Peripheral-array 207.03 of Figure 49.

With reference to Figure 49, in one exemplary embodiment, primary array is 8,000,000 pel arrays comprising approximate 3266 pixels along its level (transverse direction) axle.Described imaging system projects to the scene corresponding to approximate 25 ° of visual fields on this array.This projection is represented by 212.01 of Figure 50.In this embodiment, each pixel takes into account the visual field of approximate 0.008 ° of scene.

First Peripheral-array (maximum amplification array) is 2,000,000 pel arrays comprising 1633 pixels along its level (transverse direction) axle.Described imaging system is same scene smaller portions, and---being 25 °/3 visual fields in this embodiment---projects on this array.This projection is represented by 212.02 of Figure 50.In this embodiment, each pixel takes into account the visual field of approximate 2/3*0.008 °=0.005 ° of scene.

Second Peripheral-array (middle convergent-divergent array) is 2,000,000 pel arrays comprising 1633 pixels along its level (transverse direction) axle.Described imaging system projects to a part for same scene on this array, and wherein the angular field of this part is in the centre between 25 °, complete visual field and amplification 8 °, visual field.This projection is represented by 212.03 of Figure 50.In one exemplary embodiment, described system is designed such that each pixel takes into account the visual field of the approximate sqrt (2/3) * 0.008 °=0.0065 ° of scene now.In this embodiment, the scene being projected to the second Peripheral-array corresponds to 25/3/sqrt (2/3)=10.2 °.

Primary array can comprise at least 4 to 12,000,000 pixels or be included in any scope (such as 4,6,8,10 or 12,000,000 pixel) wherein.For secondary array, show that it also can be identical size (4,6,8,10,12).In various embodiments, the secondary array of some (1 to 20 million pixels or any scope be included in wherein, particularly 1,2,4,6,8,10,12,14 or 16,000,000 pixels) can be had.Secondary array can be less than 1 to 8 million pixels or be included in the primary array of any scope (such as 1,2,4,6 or 8,000,000 pixel) wherein.In certain embodiments, all secondary pattern matrixs can be identical sizes (and can be less than primary picture array).In other embodiments, the size of secondary array itself can change (such as it can change between 1,2 or 4,000,000 pixels).It can be polychrome or monochrome (particularly having the secondary array of multiple of two greens, a blueness and a redness and this ratio).In some instances, primary array can have 1x convergent-divergent, and secondary array can by more times of amplifications (1.5x to 10x or any scope be included in wherein, particularly 2,3 or 4x convergent-divergent).In other embodiments, primary array can have the zoom level between the zoom level being in each secondary array.Primary array can have x times of convergent-divergent, and a secondary array can be half (0.5) x, and another can be 2x.Another example will be at least two secondary arrays reduced (1,2 or 4,000,000 pixel) of 1/4th (0.25) x and half (0.5) x, the primary array (2,4,8 or 12,000,000 pixel) of 1x convergent-divergent, and at least two secondary arrays (1,2 or 4,000,000 pixel) amplified.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

In this exemplary embodiment, in the first Peripheral-array (array of maximum amplification), 3x optical zoom is achieved.In the array of maximum amplification, each pixel is responsible for 2/3 of the visual field in primary array.

In addition, in the second Peripheral-array (namely convergent-divergent array), 2.4x optical zoom is achieved.In the array, each pixel is responsible for 82% of the visual field in primary array.

Overall imaging integrated circuit has the following area of approximate 1.5x: this area is the area will needed when only adopting and having the single imaging section of equal resolution and Pixel Dimensions.Do not damage in image quality in primary array.

In addition, the progressive of convergent-divergent is provided by the existence of middle convergent-divergent array.

In three array case, the process for the image utilizing multiple array to generate provides different convergent-divergents.

With reference to Figure 45, in the exemplary embodiment, the width in the middle of three width images only can be stored.For example, the user of imaging system may indicate for reducing or amplifying or the preference of middle zoom mode, and can only retain preferred image in this case.

With reference to Figure 46, in the exemplary embodiment, multiple image can be sent to Graphics Processing Unit, it can use described Computer image genration to combine the image of the information be included in described multiple image.Graphics Processing Unit significantly can not change image in the section of only being caught image by primary imageing sensor.Graphics Processing Unit can provide more high-resolution section at the immediate vicinity of reported image, in reported image this section benefit from be combined in Peripheral-array center combination information with by the content that (one or more) amplify and/or intermediate arrays is reported.

With reference to Figure 47, in the exemplary embodiment, the user of imaging system may wish to be retained in afterwards select the option of zoom level sometime---comprise effective optical zoom level.In the exemplary embodiment, the view data gathered by multiple array segment can be made to can be used for follow-up image procossing application, for having the image desired by desired convergent-divergent based on the information processing be included in multiple array segment afterwards.

With reference to Figure 48, in the exemplary embodiment, the user of imaging system may wish to be retained in afterwards select the option of zoom level sometime---comprise effective optical zoom level.In the exemplary embodiment, the view data gathered by multiple array segment can be made to can be used for a certain device, for having the image desired by desired convergent-divergent based on the information processing be included in multiple array segment afterwards.

Figure 51 shows an exemplary embodiment of multiple aperture convergent-divergent from the visual angle of pattern matrix.The rectangle comprising 208.01 is primary array, and that is it is that maximum individual pixel changes into picture section.The ellipse comprising 208.01 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 208.01.

The rectangle comprising 208.02 is the first Peripheral-array.The ellipse comprising 208.02 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 208.02.208.03,208.04 and 208.05 is second, third and the 4th peripheral and the 5th Peripheral-array similarly.

208.06 be used to the object relevant with imaging (such as biased, regularly, amplify, store, image procossing) the section of integrated circuit.

In certain embodiments, the flexibility of (one or more) position in the region of selection such as 208.06 and so on can be used to optimize distribution, minimize total integrated circuit area and cost.

Figure 52 shows an exemplary embodiment of multiple aperture convergent-divergent from the visual angle of the scene of imaging.Rectangle 218.01 represents the scene parts be imaged onto on the primary array 208.01 of Figure 51.

Rectangle 218.02 represents the scene parts be imaged onto on first Peripheral-array 208.02 of Figure 51.218.03,218.04 and 218.05 is similar.

With reference to Figure 51, in one exemplary embodiment, primary array is 8,000,000 pel arrays comprising approximate 3266 pixels along its level (transverse direction) axle.Described imaging system projects to the scene corresponding to approximate 25 ° of visual fields on this array.This projection is represented by 218.01 of Figure 52.In this embodiment, each pixel takes into account the visual field of approximate 0.008 ° of scene.

First, second, third and fourth array is 2,000,000 pel arrays comprising 1633 pixels along their level (transverse direction) axle respectively.Described imaging system projects to a part for same scene on each array.Projection in the situation of the first Peripheral-array is represented by 218.02 of Figure 52.In one exemplary embodiment, described system is designed such that each pixel takes into account the visual field of approximate 0.008 ° of scene/2=0.004 ° now.In this embodiment, the scene be projected on the second Peripheral-array corresponds to 25 °/(2*2)=6.25 °.The different piece of scene is projected on 218.03,218.04 and 218.05 similarly.In this way, the scene be projected on the combination rectangle formed by 218.02-218.05 corresponds to 12.5 °.

Primary array can comprise at least 4 to 12,000,000 pixels or be included in any scope (such as 4,6,8,10 or 12,000,000 pixel) wherein.For secondary array, show that it also can be identical size (4,6,8,10,12).In various embodiments, the secondary array of some (1 to 20 million pixels or any scope be included in wherein, particularly 1,2,4,6,8,10,12,14 or 16,000,000 pixels) can be had.Secondary array can be less than 1 to 8 million pixels or be included in the primary array of any scope (such as 1,2,4,6 or 8,000,000 pixel) wherein.In certain embodiments, all secondary pattern matrixs can be identical sizes (and can be less than primary picture array).In other embodiments, the size of secondary array itself can change (such as it can change between 1,2 or 4,000,000 pixels).It can be polychrome or monochrome (particularly having the secondary array of multiple of two greens, a blueness and a redness and this ratio).In some instances, primary array can have 1x convergent-divergent, and secondary array can by more amplifications (1.5x to 10x or any scope be included in wherein, particularly 2,3 or 4x convergent-divergent).In other embodiments, primary array can have the zoom level between the zoom level being in each secondary array.Primary array can have the convergent-divergent of x, and a secondary array can be half (0.5) x, and another can be 2x.Another example will be at least two secondary arrays reduced (1,2 or 4,000,000 pixel) of 1/4th (0.25) x and half (0.5) x, the primary array (2,4,8 or 12,000,000 pixel) of 1x convergent-divergent and at least two secondary arrays (1,2 or 4,000,000 pixel) amplified.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

In this exemplary embodiment, 2x optical zoom is achieved by Peripheral-array.Each pixel in Peripheral-array is responsible for 1/2 of the visual field in primary array.

The area of overall imaging integrated circuit be slightly less than 2x when only adopt there is the single imaging section of equal resolution and Pixel Dimensions institute will the area of needs.Do not damage in image quality in primary array.

In addition, amplify array by each and the progressive of convergent-divergent is provided.

Figure 53 shows an exemplary embodiment of multiple aperture convergent-divergent from the visual angle of pattern matrix.The rectangle comprising 209.01 is primary array, and that is it is that maximum individual pixel changes into picture section.The ellipse comprising 209.01 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 209.01.

The rectangle comprising 209.02 is the first Peripheral-array.The ellipse comprising 209.02 represents the approximate extents of optical system (one or more lens may be irises), its will the projection imaging of scene of imaging on 209.02.209.03,209.04,209.05,209.06 is second, third and the 4th peripheral and the 5th Peripheral-array similarly.

209.11 be used to the object relevant with imaging (such as biased, regularly, amplify, store, image procossing) a section of integrated circuit.

Figure 54 shows an exemplary embodiment of multiple aperture convergent-divergent from the visual angle of the scene of imaging.Rectangle 219.01 represents the scene parts be imaged onto on the primary array 209.01 of Figure 53.

Rectangle 219.02 represents the scene parts be imaged onto on first Peripheral-array 209.02 of Figure 53.218.03... be similar.

With reference to Figure 53, in one exemplary embodiment, primary array is 8,000,000 pel arrays comprising approximate 3266 pixels along its level (transverse direction) axle.Described imaging system projects to the scene corresponding to approximate 25 ° of visual fields on this array.This projection is represented by 219.01 of Figure 54.In this embodiment, each pixel takes into account the visual field of approximate 0.008 ° of scene.

Each Peripheral-array is the approximate 320k pel array comprising 653 pixels along their level (transverse direction) axle respectively.Described imaging system projects to a part for same scene on each array.Projection in the situation of the first Peripheral-array is represented by 219.02 of Figure 53.In one exemplary embodiment, described system is designed such that each pixel takes into account the visual field of approximate 0.008 ° of scene/2=0.004 ° now.In this embodiment, the scene be projected on the second Peripheral-array corresponds to 25 °/(2*3)=4.16 °.The different piece of scene is projected on 219.03... similarly.In this way, the scene be projected on the combination rectangle formed by 219.02... corresponds to 12.5 °.

Primary array can comprise at least 4 to 12,000,000 pixels or be included in any scope (such as 4,6,8,10 or 12,000,000 pixel) wherein.For secondary array, show that it also can be identical size (4,6,8,10,12).In various embodiments, the secondary array of some (1 to 20 million pixels or any scope be included in wherein, particularly 1,2,4,6,8,10,12,14 or 16,000,000 pixels) can be had.Secondary array can be less than 1 to 8 million pixels or be included in the primary array of any scope (such as 1,2,4,6 or 8,000,000 pixel) wherein.In certain embodiments, all secondary arrays can be identical sizes (and can be less than primary picture array).In other embodiments, the size of secondary array itself can change (such as it can change between 1,2 or 4,000,000 pixels).It can be polychrome or monochrome (particularly having the secondary array of multiple of two greens, a blueness and a redness and this ratio).In some instances, primary array can have 1x convergent-divergent, and secondary array can by more amplifications (1.5x to 10x or any scope be included in wherein, particularly 2,3 or 4x convergent-divergent).In other embodiments, primary array can have the zoom level between the zoom level being in each secondary array.Primary array can have x convergent-divergent doubly, and a secondary array can be half (0.5) x, and another can be 2x.Another example will be at least two secondary arrays reduced (1,2 or 4,000,000 pixel) of 1/4th (0.25) x and half (0.5) x, the primary array (2,4,8 or 12,000,000 pixel) of 1x convergent-divergent, and at least two secondary arrays (1,2 or 4,000,000 pixel) amplified.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

In this exemplary embodiment, 2x optical zoom is achieved by Peripheral-array.Each pixel in Peripheral-array is responsible for 1/2 of the visual field in primary array.

The area of overall imaging integrated circuit be slightly less than when only adopt there is the single imaging section of equal resolution and Pixel Dimensions institute by 1.2 times of the area of needs.Do not damage in image quality in primary array.

In addition, amplify array by each and the progressive of convergent-divergent is provided.

With reference to Figure 49, in one exemplary embodiment, primary array is 8,000,000 pel arrays comprising approximate 3266 pixels along its level (transverse direction) axle.Described pixel has the linear-scale of 1.4 μm.Described imaging system projects to the scene corresponding to approximate 25 ° of visual fields on this array.This projection is represented by 212.01 of Figure 50.In this embodiment, each pixel takes into account the visual field of approximate (25 °/3266) of scene=0.008 °.

First Peripheral-array (maximum amplification array) is 2* (1.4/0.9)=3.1 million pel array comprising 2540 pixels along its level (transverse direction) axle.Described imaging system is same scene smaller portions, and---being 25 °/3=8 ° visual field in this embodiment---projects on this array.This projection is represented by 212.02 of Figure 50.In this embodiment, each pixel takes into account the angular field of (25 °/3/2540) of scene=0.33 ° now.

Second Peripheral-array (middle convergent-divergent array) is 2* (1.4/0.9)=3.1 million pel array comprising 2540 pixels along its level (transverse direction) axle.Described imaging system projects to a part for same scene on this array, and wherein the angular field of this part is in the centre between complete visual field 25o and amplification visual field 8o.This projection is represented by 212.03 of Figure 50.Described imaging system is a part for same scene, and---being 25 °/2=12.5 ° visual field in this embodiment---projects on this array.This projection is represented by 212.03 of Figure 50.In this embodiment, each pixel takes into account the angular field of (25 °/2/2540) of scene=0.005 ° now.

Primary array can comprise at least 4 to 12,000,000 pixels or be included in any scope (such as 4,6,8,10 or 12,000,000 pixel) wherein.For secondary array, show that it also can be identical size (4,6,8,10,12).In various embodiments, the secondary array of some (1 to 20 million pixels or any scope be included in wherein, particularly 1,2,4,6,8,10,12,14 or 16,000,000 pixels) can be had.Secondary array can be less than 1 to 8 million pixels or be included in the primary array of any scope (such as 1,2,4,6 or 8,000,000 pixel) wherein.In certain embodiments, all secondary pattern matrixs can be identical sizes (and can be less than primary picture array).In other embodiments, the size of secondary array itself can change (such as it can change between 1,2 or 4,000,000 pixels).They can be polychrome or monochrome (particularly having the secondary array of multiple of two greens, a blueness and a redness and this ratio).In some instances, primary array can have 1x convergent-divergent, and secondary array can by more amplifications (1.5x to 10x or any scope be included in wherein, particularly 2,3 or 4x convergent-divergent).In other embodiments, primary array can have the zoom level between the zoom level being in each secondary array.Primary array can have x convergent-divergent doubly, and a secondary array can be half (0.5) x, and another can be 2x.Another example will be at least two secondary arrays reduced (1,2 or 4,000,000 pixel) of 1/4th (0.25) x and half (0.5) x, the primary array (2,4,8 or 12,000,000 pixel) of 1x convergent-divergent, and at least two secondary arrays (1,2 or 4,000,000 pixel) amplified.

In the exemplary embodiment, each array can be on single substrate.Can form photosensitive layer on substrate, wherein image element circuit is in below photosensitive section.In certain embodiments, photosensitive section, such as photodiode, pinned photodiode, part pinned photodiode or photoelectricity door can be formed in the doped region of substrate (instead of the nano crystal material at top).In certain embodiments, described imageing sensor can be nanocrystal or cmos image sensor.In certain embodiments, one or more imageing sensor can be formed at the side of substrate (such as the back side), wherein charge storage storehouse extends to the opposite side (such as front) of (or close) substrate from this side of substrate, and this opposite side has metal interconnecting layer and forms the pixel readout circuit that can carry out from charge storage storehouse reading.

Pixel Dimensions in lateral dimensions can from be less than about 0.5 to 3 microns or be included in any scope wherein (be less than about 0.5 to 3 microns square area or any scope of being included in wherein) change.In some instances, Pixel Dimensions can be less than about 1.3,1.4,1.5,1.7,2,2.2 or 2.5 microns (have be less than this quantity square area).Concrete example is 1.2 and 1.4 microns.Primary array can have the pixel being greater than secondary array.Primary array can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron, and is less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron.Described one or more secondary array also can be greater than 0.5,0.7,1,1.2 or 1.4 or 1.5 micron and be less than 1,1.2,1.5,1.7,2,2.2,2.5 or 3 micron, but will be less than primary array.For example, primary array can be greater than X, and secondary array can be less than X, and wherein X is 1.2,1.4,1.5,1.7 or 2 etc.

In this exemplary embodiment, in the first Peripheral-array (i.e. the array of maximum amplification), 3x optical zoom is achieved.In the array of maximum amplification, each pixel is responsible for 41% of the visual field in primary array.

In addition, in the second Peripheral-array (namely convergent-divergent array), 2x optical zoom is achieved.In the array, each pixel is responsible for 60% of the visual field in primary array.

The area of overall imaging integrated circuit be approximate 1.5x when only adopt there is the single imaging section of equal resolution and Pixel Dimensions institute will the area of needs.Do not damage in image quality in primary array.

In addition, the progressive of convergent-divergent is provided by the existence of middle convergent-divergent array.

Figure 55 depicts a kind of method adopting single image sensor array (label 313.01 is enclosed in complete rectangular wherein).In the exemplary embodiment, described single image sensor array can be 12,000,000 pel arrays.Primary lens Systems Projection utilizes the image of a subset of described complete rectangular.The region utilized is depicted as the ellipse having and comprise label 313.01.In the exemplary embodiment, primary lens system can be imaged onto in 8,000,000 pixel subset utilized of 12,000,000 pel arrays.The rectangle comprising 313.02,313.03,313.04,313.05 represents the section being used to amplification imaging of complete array.The ellipse comprising 313.02,313.03,313.04,313.05 represents and utilizes these complementary lens to form image.

Figure 56 depicts a kind of method adopting single image sensor array (label 314.01 is enclosed in complete rectangular wherein).In the exemplary embodiment, described single image sensor array can be 12,000,000 pel arrays.Primary lens Systems Projection utilizes the image of a subset of described complete rectangle.The region utilized is depicted as the ellipse having and comprise label 314.01.In the exemplary embodiment, primary lens system can be imaged onto in 8,000,000 pixel subset utilized of 12,000,000 pel arrays.The rectangle comprising 314.02-314.16 represents the section being used to amplification imaging of complete array.The ellipse comprising 314.02-314.16 represent utilize these complementary lens formed image.

Multiple complementary lens is used to be amplified to interested single section---super-resolution.

With reference to Figure 57, primary imaging system can carry out imaging to whole interested scene 215.01.At least two lens systems can be imaged onto the substantially the same subdivision 215.02 of whole scene at least two imageing sensor sections.Generally speaking, imaging can be carried out by least two imageing sensor sections to substantially the same section interested.The super resolution for this section interested can be allowed like this.Specifically, the resolution realized can exceed the resolution utilizing a lens system once to be generated on an imageing sensor by this section interested---and undertaken can being combined more than Polaroid obtained information by section interested in this, thus produce super resolution image.

With reference to Figure 58, can lay according to various ways each the interested sub-segments be imaged onto on each secondary array.In certain embodiments, at least lens can produce the image of the overlapping sub-segments near corresponding to picture centre.The information combined from these overlapping sub-segments can produce super-resolution in heart place in the picture.In certain embodiments, at least one lens corresponding to each additional sub-region section can realize predefined variable convergent-divergent and amplify resolution in once taking.

The slightly different visual angle that the lens system of difference corresponding to different sub-segments also will provide about same scene.This Viewing-angle information can with image procossing combined be used to provide the information about the subject depth in scene.This technology can be referred to as 3D imaging.

In certain embodiments, carry out mutual user with the image display system of the display on such as mobile phone, computer or TV and so on and may wish the image that " being in operation " changes them and see.For example, due to the resolution that hope improves, they may wish in the sub-segments of image, to carry out convergent-divergent in fact or in resetting.In certain embodiments, user can be in operation and to amplify in sub-segments, and can be allowed to run middle high-resolution by the availability of the section interested of multiple imaging and amplify.

In certain embodiments, carry out mutual user may wish to be in operation from presenting of 2D image change to presenting of 3D rendering with the image display system of the display on such as mobile phone, computer or TV and so on.For example, they may wish that in fact or playback, be switched to 3D represents.In certain embodiments, user may be in operation and be switched to 3D in sub-segments, and the availability of the pre-recorded image of various visual angles can allow to present the information about subject depth.

Figure 59 depicts image sensor devices in section.901 is substrates, and can comprise circuit and metal and interlayer dielectric and top metal.903 is utilize in 901 and the metal in 905 may be also had to carry out the continuous light-sensitive material contacted.905 is materials that transparent or partially transparent on 903 tops or wavelength selectivity are transparent.907 is opaque materials, its guarantee from top device incident and can not be transferred to the incidence angle light arrived section 905 to illegally such as 909 and so on neighborhood pixels, if described transfer occurs will to be the process being referred to as optical crosstalk.

Figure 60 depicts image sensor devices in section.1001 is substrates, and can comprise circuit and metal and interlayer dielectric and top metal.1003 is utilize in 1001 and the metal in 1005 may be also had to carry out the light-sensitive material contacted.1005 is materials that transparent or partially transparent on 1003 tops or wavelength selectivity are transparent.1007 is opaque materials, it guarantees from top device incident and to arrive section 1005 and thus the light arriving 1003 can not be transferred to the neighborhood pixels of such as 1009 or 1011 and so on, if described transfer occurs to be referred to as optics or electrically or the process of optics and electrical crosstalk by being to incidence angle to illegally.

Figure 61 A to 61F depicts the mode that making that optical crosstalk as shown in Figure 59 reduces structure in section.Figure 61 A depicts substrate 1101, thereon deposit optical sensitive material 1103 and in succession one or more layers 1105, it such as comprises such as sealant, passivating material, dielectric, color filter array, microlens material.In Figure 61 B, layer 1105 is patterned and etches, to define pixelation section.In Figure 61 C, the structure shown in Figure 61 B deposited metal coating 1107.In Figure 61 D, the structure of Figure 61 C is directed etching, to remove metal section from 1107 on a horizontal surface, but is stayed on a vertical plane.The light provided in final structure between neighborhood pixels is covered by the vertical metal layer obtained.In Figure 61 E, deposited another one or multiple passivation/sealing/colour/microlens layer 1109.In Figure 61 F, described surface is flattened.

Referring again to Figure 59, can such as depend on that material is 10-20nm by the thin layer 907(of the deposited on sidewalls reflecting material of the depression of passivation layer between photosensitive layer 903 and color filter array (top sections of 905)) reduce optical crosstalk between pixel.Because layer 905 is deposited on sidewall, therefore its minimum thickness is only defined by the optical properties of material, instead of is defined by the minimum critical yardstick of used photoetching process.

In certain embodiments, deposit a transparent etching stopping layer of thin (such as 5-10nm) dielectric, using as the overlay film on optical sensitive material.Etching stopping layer deposits thicker (such as a 50-200nm) and transparent dielectric passivation layer (SiO2).The checkerboard pattern of the size of etching per unit pixel, utilize conformal process (such as CVD, PECVD, ALD) to deposit 10nm aluminum metal layer on described topological structure, and utilize directed (anisotropy) reactive ion plasma etch process to remove metal from the bottom of the sunk part of described pattern.Described sunk area is filled with identical transparent passivation dielectric (SiO2) and is filled overflow, thus provides enough thick film, to allow the planarization such as utilizing chemico-mechanical polishing or eat-back.Described process is removed too much SiO2 and is also had the kish film on horizontal surface.Isolation for CFA or microlens layer can process like application class.

With reference to Figure 59, vertical metal layer 907 can provide the optics of the improvement between small pixel to isolate when not having remarkable photoresponse to lose.

Referring again to Figure 60, for the optics isolation of the pixel by optical sensitive material 1003, following structure and process can be adopted.Utilize the high resolution lithography technology of such as double-exposure and so on or stamping technique on the surface of optical sensitive material, form hard mask protection pattern.Described mask forms the grid with smallest dimension (such as 22nm or 16nm width).Whole or most of throughout photosensitive layer, utilize anisotropy reacting ion plasma etch process to etch the light-sensitive material be exposed.The depression formed be filled with such as a) have the photon got back in pixel is provided total internal reflection needed for the one or more of dielectric substances of refractive index; Or b) light-sensitive material be exposed is oxidized, thus on the sidewall of described depression, form the thick electricity isolated layer of about 1-5nm, and remaining free space such as utilizes traditional vacuum metallization processes process to be filled with the reflective metal material of such as aluminium and so on.The kish on light-sensitive material surface is removed by wet method or dry etching or by mechanical polishing.

In each disclosed here embodiment, a kind of exemplary imaging system comprises: the first image sensor array; Be configured to first optical system of the first image projection on the first image sensor array, described first optical system has the first zoom level; Second image sensor array; Be configured to second optical system of the second image projection on the second image sensor array, described second optical system has the second zoom level; Wherein, the second image sensor array points to the direction identical with the first optical system with the first image sensor array with the second optical system; Wherein, the second zoom level is higher than the first zoom level, and the second image be therefore projected on the second image sensor array is an amplifier section of the first image be projected on the first image sensor array; And wherein, the first image sensor array comprises at least four million pixels; And wherein, the second image sensor array comprises half or less number of pixels compared with the number of pixels in the first image sensor array.

Exemplary imaging system above, wherein, the first image sensor array comprises at least six million pixels.

Exemplary imaging system above, wherein, the first image sensor array comprises at least eight million pixels.

Any one is in the imaging system of front example, and wherein, the second image sensor array comprises 4,000,000 pixels or less.

Any one is in the imaging system of front example, and wherein, the second image sensor array comprises 2,000,000 pixels or less.

Any one is in the imaging system of front example, and wherein, the second image sensor array comprises 1,000,000 pixels or less.

Any one is in the imaging system of front example, wherein, first image sensor array comprises the first array of the first pixel section and the second image sensor array comprises the second array of the second pixel section, and wherein each first pixel section is greater than each second pixel section.

Any one is in the imaging system of front example, and wherein, each first pixel section has the lateral distance across the first pixel section being less than 2.5 microns.

Any one is in the imaging system of front example, wherein, each first pixel section have be less than about 2.5 microns square area.

Any one is in the imaging system of front example, and wherein, each first pixel section has the lateral distance across the first pixel section being less than 2 microns.

Any one is in the imaging system of front example, wherein, each first pixel section have be less than about 2 microns square area.

Any one is in the imaging system of front example, and wherein, each first pixel section has the lateral distance across the first pixel section being less than 1.5 microns.

Any one is in the imaging system of front example, wherein, each first pixel section have be less than about 1.5 microns square area.

Any one is in the imaging system of front example, and wherein, each second pixel section has the lateral distance across the second pixel section being less than 2.1 microns.

Any one is in the imaging system of front example, wherein, each second pixel section have be less than about 2.1 microns square area.

Any one is in the imaging system of front example, and wherein, each second pixel section has the lateral distance across the second pixel section being less than 1.6 microns.

Any one is in the imaging system of front example, wherein, each second pixel section have be less than about 1.6 microns square area.

Any one is in the imaging system of front example, and wherein, each second pixel section has the lateral distance across the second pixel section being less than 1.3 microns.

Any one is in the imaging system of front example, wherein, each second pixel section have be less than about 1.3 microns square area.

Any one is in the imaging system of front example, and it also comprises: the 3rd image sensor array and being configured to three optical system of the 3rd image projection on the 3rd image sensor array, and described 3rd optical system has the 3rd zoom level; Wherein, the 3rd image sensor array points to the direction identical with the first optical system with the first image sensor array with the 3rd optical system.

The imaging system of example above, wherein, the 3rd zoom level is higher than the second zoom level.

The imaging system of example above, wherein, the 3rd zoom level is less than the first zoom level.

Any one is in the imaging system of front example, and wherein, the 3rd image sensor array comprises the number of pixels identical with the second image sensor array.

Any one is in the imaging system of front example, and wherein, the 3rd image sensor array comprises 4,000,000 pixels or less.

Any one is in the imaging system of front example, and wherein, the 3rd image sensor array comprises 2,000,000 pixels or less.

Any one is in the imaging system of front example, and wherein, the 3rd image sensor array comprises 1,000,000 pixels or less.

Any one is in the imaging system of front example, and wherein, the 3rd image sensor array comprises the 3rd array of the 3rd pixel section, and wherein each the 3rd pixel section is less than each first pixel section.

Any one is in the imaging system of front example, and wherein, each the 3rd pixel section has the lateral distance across this pixel section being less than 1.9 microns.

Any one is in the imaging system of front example, wherein, each the 3rd pixel section have be less than about 1.9 microns square area.

Any one is in the imaging system of front example, and wherein, each the 3rd pixel section has the lateral distance across the 3rd pixel section being less than 1.4 microns.

Any one is in the imaging system of front example, wherein, each the 3rd pixel section have be less than about 1.4 microns square area.

Any one is in the imaging system of front example, and wherein, each the 3rd pixel section has the lateral distance across the 3rd pixel section being less than 1.2 microns.

Any one is in the imaging system of front example, wherein, each the 3rd pixel section have be less than about 1.2 microns square area.

Any one is in the imaging system of front example, and wherein, the first image sensor array and the second image sensor array are formed on the same substrate.

The imaging system of example above, wherein, the 3rd image sensor array is formed on the same substrate.

Any one is in the imaging system of front example, also comprises the user interface controls for selecting zoom level, and for reading image from first sensor array and the second sensor array and generating the circuit of output image based on selected zoom level.

Any one is in the imaging system of front example, wherein, when the first zoom level is selected, selects the first image for output.

Any one is in the imaging system of front example, wherein, when the first zoom level is selected, uses the second image to strengthen the first image for output.

Any one is in the imaging system of front example, wherein, when the first zoom level is selected and the first image is used to enhancing the second image, selects the second image for output.

Any one is in the imaging system of front example, and wherein, described imaging system is a part for camera device, and wherein can select user control in case from camera device export the first image and the second image all the two.

Any one is in the imaging system of front example, and wherein, described imaging system is a part for camera device, and wherein can select user control to export the first image, the second image and the 3rd image from camera device.

Any one is in the imaging system of front example, also comprise for the first image element circuit from the first image sensor array reads image data with for the second image element circuit from the second image sensor array reads image data, and be configured to stop the electronic global shutter of the electric charge integration between the first image sensor array and the first image element circuit and between the second image sensor array and the second image element circuit in the substantially the same time.

Any one is in the imaging system of front example, and wherein, described electronic global shutter is configured to the integration period stopping each pixel section corresponded in the first pixel sensor array and the second pixel sensor array in each other millisecond.

Any one is in the imaging system of front example, it also comprises for the 3rd image element circuit from the 3rd image sensor array reads image data, and wherein electronic global shutter is configured to the electric charge integration stopping between the 3rd image sensor array and the 3rd image element circuit in the time substantially the same with first sensor array and the second sensor array.

Any one is in the imaging system of front example, wherein, the integration period of each the 3rd pixel section corresponded in the 3rd pixel sensor array is stopped in one millisecond that described electronic global shutter is configured to each pixel section in the first image sensor array and the second image sensor array.

In each disclosed here embodiment, a kind of exemplary imaging system comprises: primary image sensor array; Be configured to the primary optic be projected in by primary picture on primary image sensor array, described primary optic has the first zoom level; Multiple secondary image sensor array; Corresponding to the secondary optical system of each secondary image sensor array, wherein each secondary optical system is configured to by secondary image projection on a secondary image sensor array of correspondence, and each secondary optical system has the corresponding zoom level being different from the first zoom level; Wherein, each secondary image sensor array points to the direction identical with primary optic with primary image sensor array with each secondary optical system; And wherein, primary image sensor array is greater than each secondary image sensor array.

Exemplary imaging system above, it also comprises the control circuit in order to export primary picture output during the first operator scheme based on the first image projected on primary image sensor array, wherein, primary picture exports is not based on any secondary Computer image genration projected on secondary pattern matrix.

Exemplary imaging system above, it also comprises the control circuit in order to export primary picture output during the first operator scheme based on the first image projected on primary image sensor array, wherein, strengthen primary picture based at least one secondary image to export.

Any one is in the imaging system of front example, wherein, described control circuit is configured to the zoomed image exporting the zoom level had higher than the first zoom level during the second operator scheme, and wherein, described zoomed image is based at least one width in secondary image and primary picture.

Any one is in the imaging system of front example, and wherein, the number of secondary image sensor array is at least two.

Any one is in the imaging system of front example, and wherein, the number of secondary image sensor array is at least four.

Any one is in the imaging system of front example, and wherein, the number of secondary image sensor array is at least six.

Any one is in the imaging system of front example, and wherein, each secondary optical system has zoom level different from each other.

Any one is in the imaging system of front example, and wherein, at least some zoom level in described multiple secondary optical system is higher than the first zoom level.

Any one is in the imaging system of front example, and wherein, at least some zoom level in described multiple secondary optical system is lower than the first zoom level.

Any one is in the imaging system of front example, wherein, described multiple secondary optical system comprises and having higher than secondary optical system corresponding at least two of zoom level of the first zoom level, and has lower than secondary optical system corresponding at least two of zoom level of the first zoom level.

Any one is in the imaging system of front example, wherein, described imaging system is a part for camera device, also comprise the control circuit being configured to export multiple image during a certain operator scheme, wherein said multiple image comprises at least piece image corresponding to each image sensor array.

Any one is in the imaging system of front example, and wherein, described imaging system is a part for camera device, also comprises the control circuit with the image of super-resolution being configured to export from the first image and at least one secondary Computer image genration.

Any one is in the imaging system of front example, also comprises and is configured to be controlled to substantially the same global electronic shutter circuit corresponding to the imaging period of primary image sensor array with each secondary image sensor array.

Any one is in the imaging system of front example, also comprises and is configured to be controlled to substantially the same global electronic shutter circuit corresponding to the integration period of primary image sensor array with each secondary image sensor array.

In each disclosed here embodiment, a kind of exemplary imaging system comprises: semiconductor substrate; Multiple image sensor array, comprises primary image sensor array and multiple secondary image sensor array; Multiple optical system, comprises at least one optical system corresponding to each image sensor array; Wherein, each optical system has different zoom level; Each image sensor array comprises and is formed in image element circuit on substrate for the image sensor array reading images signal from correspondence, and the image element circuit wherein corresponding to each image sensor array comprises commutation circuit; And be operatively coupled to the control circuit of commutation circuit of each image sensor array.

Exemplary image sensor above, wherein, described control circuit is configured to switch commutation circuit in the substantially the same time, to provide the global electronic shutter corresponding to each image sensor array.

Any one is at the imageing sensor of front example, and wherein, described control circuit is configured to switch commutation circuit, to terminate in the substantially the same time integration period corresponding to each image sensor array.

Any one is in the imaging system of front example, and wherein, the number of secondary image sensor array is at least four.

Any one is in the imaging system of front example, wherein, optical system corresponding to secondary image sensor array comprises optical system corresponding at least two of the zoom level of the zoom level had higher than primary image sensor array, and has lower than optical system corresponding at least two of zoom level of primary image sensor array.

Any one is in the imaging system of front example, and wherein, primary image sensor array is greater than each secondary image sensor array.

Any one is in the imaging system of front example, wherein, image element circuit corresponding to each image sensor array comprises the multiple image element circuits be formed on substrate of each pixel section corresponding to corresponding image sensor array, and each image element circuit comprises charge storage storehouse and the switching device between charge storage storehouse and corresponding pixel section.

Any one is in the imaging system of front example, wherein, the commutation circuit of each image sensor array is operatively coupled to each switching device of each image element circuit in this image sensor array, thus makes the integration period corresponding to each image element circuit be configured to terminate in the substantially the same time.

Any one is in the imaging system of front example, and wherein, each pixel section comprises optical sensitive material on the image element circuit of the pixel section for correspondence.

Any one is in the imaging system of front example, and wherein, each pixel section comprises optical sensitive section in the first side of semiconductor substrate, and wherein said image element circuit comprises the reading circuit of the pixel section for correspondence in the second side of semiconductor substrate.

Any one is in the imaging system of front example, and wherein, described charge storage storehouse comprises pinprick diode.

Any one is in the imaging system of front example, and wherein, described switching device is transistor.

Any one is in the imaging system of front example, and wherein, described switching device is diode.

Any one is in the imaging system of front example, and wherein, described switching device is parasitic diode.

Any one is in the imaging system of front example, and wherein, the switching device that described control circuit is configured in the substantially the same time to each image element circuit switches.

Any one is in the imaging system of front example, wherein, each pixel section comprises the first corresponding electrode and the second corresponding electrode, and the optical sensitive material of wherein corresponding pixel section is between first electrode and the second corresponding electrode of the correspondence of the pixel section of correspondence.

Any one is in the imaging system of front example, wherein, each image element circuit to be configured to when the switching device of the pixel section of correspondence is in the first state transfer charge between the first electrode to charge storage storehouse, and blocks from the first electrode to the Charger transfer in charge storage storehouse when the switching device of the pixel section of correspondence is in the second state.

Any one is in the imaging system of front example, and wherein, described control circuit is configured in the substantially the same time, the switching device of each image element circuit is switched to the second state from the first state for each image element circuit after integrating time section.

Any one is in the imaging system of front example, and wherein, each image element circuit also comprises reset circuit, and reset circuit is configured to the voltage difference resetting optical sensitive material two ends when switching device is in the second state.

Any one is in the imaging system of front example, wherein, each image element circuit be also included in that the side of semiconductor substrate formed below multiple pixel section reading circuit.

Any one is in the imaging system of front example, and wherein, described optical sensitive material is the continuous film of nano crystal material.

Any one is in the imaging system of front example, also comprise in order to from reading the analog to digital change-over circuit generating digital pixel numerical value from the signal of the image element circuit corresponding to each image sensor array, and the pixel number being configured to process in the first mode of operation corresponding at least two in image sensor array is to generate the processor of output image.

The imaging system of example above, wherein, described output image has the zoom level between at least one secondary image sensor array and zoom level of primary image sensor array being in and being used to generate this output image.

Any one is in the imaging system of front example, it also comprises processor, and described processor is configured to during selected operator scheme, generate output image when the amendment not based on the image projected on secondary image sensor array according to the pixel number corresponding to primary image sensor array.

Any one is in the imaging system of front example, wherein, described primary image sensor array comprises the number of pixels of the complete resolution corresponding to imaging system, and wherein each secondary image sensor array comprises the number of pixels of the complete resolution being less than imaging system.

The imaging system of example above, wherein, export the image corresponding to primary image sensor array when selection the first zoom level, and export the image generated from primary image sensor array and at least one secondary image sensor array when selecting different zoom level.

In each disclosed here embodiment, a kind of exemplary imaging system comprises: imageing sensor, comprise the offset array of the pixel electrode for reading signal from this imageing sensor, the array of wherein said pixel electrode is less than the size of the pixel section of imageing sensor by the amount offset; And circuit, be configured to select an offset array of pixel electrode to read signal for from imageing sensor.

Exemplary imaging system above, it also comprises the circuit in order to read view data from each offset array of pixel electrode, and for combining the view data thus the circuit of generation output image that read from each offset array of pixel electrode.

In each disclosed here embodiment, a kind of exemplary imaging system comprises: the first image sensor array, comprise the offset array for the pixel electrode from the first image sensor array read output signal, the array of wherein said pixel electrode is less than the size of the pixel section of the first imageing sensor by the amount offset; Second image sensor array; Be configured to select an offset array of pixel electrode for the circuit from the first image sensor array read output signal; And for reading the circuit of view data from the first image sensor array and the second image sensor array.

Exemplary imaging system above, it also comprises the circuit for generating output image from the view data corresponding to the first image sensor array and the second image sensor array.

Any one is in the imaging system of front example, wherein, be configured to select the described circuit of an offset array of pixel electrode to be configured to select the following offset array of pixel electrode: described offset array is providing the highest super-resolution time combined to the view data from the first image sensor array and the view data from the second image sensor array.

Any one is in the imaging system of front example, wherein, is configured to select the described circuit of an offset array of pixel electrode to be configured to select to provide the offset array of the pixel electrode overlapping with the minimum image of the second image sensor array.

In each disclosed here embodiment, from an illustrative methods for image sensor system synthetic image, described method comprises: the first image reading out the primary importance set from each pixel section corresponding to the first image sensor array from the first image sensor array; And the second image of the second place set from each pixel section corresponding to the first image sensor array is read out from the first image sensor array.

Illustrative methods above, also comprises: according to the first image and the second Computer image genration output image.

In each disclosed here embodiment, from an illustrative methods for image sensor system synthetic image, described method comprises: the first image reading out the primary importance set from each pixel section corresponding to the first image sensor array from the first image sensor array; The second image of the second place set from each pixel section corresponding to the first image sensor array is read out from the first image sensor array; The 3rd image is read from the second image sensor array; And utilize the first image, the second image and the 3rd image to select primary importance set or second place set, read successive image for from the first image sensor array.

Illustrative methods above, it also comprises: read successive image in the time substantially the same with the successive image from the first image sensor array from the second image sensor array.

Illustrative methods above, it also comprises: the successive image according to reading from the second image sensor array generates super-resolution image with the successive image read from the first image sensor array.

Any one is in the method for front example, and wherein, the second image sensor array points to the direction identical with the first image sensor array, and has the zoom level being different from the first image sensor array.

Claims (75)

1. an imaging system, comprising:

First image sensor array;

Be configured to first optical system of the first image projection on the first image sensor array, described first optical system has the first zoom level;

Second image sensor array;

Be configured to second optical system of the second image projection on the second image sensor array, described second optical system has the second zoom level;

Wherein, the second image sensor array points to the direction identical with the first optical system with the first image sensor array with the second optical system;

Wherein, the second zoom level, higher than the first zoom level, makes the second image be projected on the second image sensor array be the amplifier section of the first image be projected on the first image sensor array; And

Wherein, the first image sensor array comprises at least four million pixels; And wherein, the second image sensor array comprises half or less number of pixels compared with the number of pixels in the first image sensor array.

2. the imaging system of claim 1, wherein, the first image sensor array comprises at least six million pixels.

3. the imaging system of claim 1, wherein, the first image sensor array comprises at least eight million pixels.

4. the imaging system of claim 1, wherein, the second image sensor array comprises 4,000,000 pixels or less.

5. the imaging system of claim 1, wherein, the second image sensor array comprises 2,000,000 pixels or less.

6. the imaging system of claim 1, wherein, the second image sensor array comprises 1,000,000 pixels or less.

7. the imaging system of claim 1, wherein, first image sensor array comprises the first array of the first pixel section and the second image sensor array comprises the second array of the second pixel section, and wherein each first pixel section is greater than each second pixel section.

8. the imaging system of claim 1, wherein, each first pixel section has the lateral distance across the first pixel section being less than 2.5 microns.

9. the imaging system of claim 1, wherein, each first pixel section have be less than about 2.5 microns square area.

10. the imaging system of claim 1, wherein, each first pixel section has the lateral distance across the first pixel section being less than 2 microns.

The imaging system of 11. claims 1, wherein, each first pixel section have be less than about 2 microns square area.

The imaging system of 12. claims 1, wherein, each first pixel section has the lateral distance across the first pixel section being less than 1.5 microns.

The imaging system of 13. claims 1, wherein, each first pixel section have be less than about 1.5 microns square area.

The imaging system of 14. claims 1, also comprise the 3rd image sensor array and be configured to three optical system of the 3rd image projection on the 3rd image sensor array, described 3rd optical system has the 3rd zoom level;

Wherein, the 3rd image sensor array points to the direction identical with the first optical system with the first image sensor array with the 3rd optical system.

The imaging system of 15. claims 14, wherein, the 3rd image sensor array comprises the number of pixels identical with the second image sensor array.

The imaging system of 16. claims 1, wherein, the first image sensor array and the second image sensor array are formed on the same substrate.

The imaging system of 17. claims 1, also comprises the user interface controls for selecting zoom level, and for reading image from first sensor array and the second sensor array and generating the circuit of output image based on selected zoom level.

The imaging system of 18. claims 1, wherein, when the first zoom level is selected, selects the first image for output.

The imaging system of 19. claims 1, wherein, when the first zoom level is selected, uses the second image to strengthen the first image for output.

The imaging system of 20. claims 1, wherein, when the first zoom level is selected and the first image is used to enhancing the second image, selects the second image for output.

The imaging system of 21. claims 1, wherein, described imaging system is a part for camera device, and wherein can select user control so as from camera device export the first image and the second image all the two.

The imaging system of 22. claims 1, wherein, described imaging system is a part for camera device, and wherein can select user control to export the first image, the second image and the 3rd image from camera device.

The imaging system of 23. claims 1, also comprise for the first image element circuit from the first image sensor array reads image data with for the second image element circuit from the second image sensor array reads image data, and be configured to stop the electronic global shutter of the electric charge integration between the first image sensor array and the first image element circuit and between the second image sensor array and the second image element circuit in the substantially the same time.

The imaging system of 24. claims 1, wherein, described electronic global shutter is configured to the integration period stopping each pixel section corresponded in the first pixel sensor array and the second pixel sensor array in each other millisecond.

The imaging system of 25. claims 14, it also comprises for the 3rd image element circuit from the 3rd image sensor array reads image data, and wherein electronic global shutter is configured to the electric charge integration stopping between the 3rd image sensor array and the 3rd image element circuit in the time substantially the same with first sensor array and the second sensor array.

26. 1 kinds of imaging systems, it comprises:

Primary image sensor array;

Be configured to the primary optic be projected in by primary picture on primary image sensor array, described primary optic has the first zoom level;

Multiple secondary image sensor array;

Corresponding to the secondary optical system of each secondary image sensor array, wherein each secondary optical system is configured to by secondary image projection on a secondary image sensor array of correspondence, and each secondary optical system has the corresponding zoom level being different from the first zoom level;

Wherein, each secondary image sensor array points to the direction identical with primary optic with primary image sensor array with each secondary optical system; And

Wherein, primary image sensor array is greater than each secondary image sensor array.

The imaging system of 27. claims 26, it also comprises the control circuit in order to export primary picture output during the first operator scheme based on the first image projected on primary image sensor array, wherein, primary picture exports is not based on any secondary Computer image genration projected on secondary pattern matrix.

The imaging system of 28. claims 26, it also comprises the control circuit in order to export primary picture output during the first operator scheme based on the first image projected on primary image sensor array, wherein, strengthen primary picture based at least one secondary image to export.

The imaging system of 29. claims 26, wherein, described control circuit is configured to the zoomed image exporting the zoom level had higher than the first zoom level during the second operator scheme, and wherein, described zoomed image is based at least one width in secondary image and primary picture.

The imaging system of 30. claims 26, wherein, each secondary optical system has zoom level different from each other.

The imaging system of 31. claims 26, wherein, at least some zoom level of described multiple secondary optical system is higher than the first zoom level.

The imaging system of 32. claims 26, wherein, at least some zoom level of described multiple secondary optical system is lower than the first zoom level.

The imaging system of 33. claims 26, wherein, described multiple secondary optical system comprises and having higher than secondary optical system corresponding at least two of zoom level of the first zoom level, and has lower than secondary optical system corresponding at least two of zoom level of the first zoom level.

The imaging system of 34. claims 26, wherein, described imaging system is a part for camera device, also comprises the control circuit being configured to export multiple image during a certain operator scheme, and wherein said institute width image comprises at least piece image corresponding to each image sensor array.

The imaging system of 35. claims 26, wherein, described imaging system is a part for camera device, also comprises the control circuit with the image of super-resolution being configured to export according to the first image and at least one secondary Computer image genration.

The imaging system of 36. claims 26, also comprises and is configured to be controlled to substantially the same global electronic shutter circuit corresponding to the imaging period of primary image sensor array with each secondary image sensor array.

The imaging system of 37. claims 26, also comprises and is configured to be controlled to substantially the same global electronic shutter circuit corresponding to the integration period of primary image sensor array with each secondary image sensor array.

38. 1 kinds of imaging systems, comprising:

Semiconductor substrate;

Multiple image sensor array, comprises primary image sensor array and multiple secondary image sensor array;

Multiple optical system, comprises at least one optical system corresponding to each image sensor array;

Wherein, each optical system has different zoom level;

Each image sensor array comprises and is formed in image element circuit on substrate for the image sensor array reading images signal from correspondence, and the image element circuit wherein corresponding to each image sensor array comprises commutation circuit; And

Operatively be coupled to the control circuit of the commutation circuit of each image sensor array.

The imageing sensor of 39. claims 38, wherein, described control circuit is configured to switch commutation circuit in the substantially the same time, to provide the global electronic shutter corresponding to each image sensor array.

The imageing sensor of 40. claims 38, wherein, described control circuit is configured to switch commutation circuit, to terminate in the substantially the same time integration period corresponding to each image sensor array.

The imaging system of 41. claims 38, wherein, the number of secondary image sensor array is at least four.

The imaging system of 42. claims 38, wherein, optical system corresponding to secondary image sensor array comprises optical system corresponding at least two of the zoom level of the zoom level had higher than primary image sensor array, and has lower than optical system corresponding at least two of zoom level of primary image sensor array.

The imaging system of 43. claims 38, wherein, primary image sensor array is greater than each secondary image sensor array.

The imaging system of 44. claims 38, wherein, image element circuit corresponding to each image sensor array comprises the multiple image element circuits be formed on substrate of each pixel section corresponding to corresponding image sensor array, and each image element circuit comprises charge storage storehouse and the switching device between charge storage storehouse and corresponding pixel section.

The imaging system of 45. claims 38, wherein, the commutation circuit of each image sensor array is operatively coupled to each switching device of each image element circuit in described image sensor array, thus makes the integration period corresponding to each image element circuit be configured to terminate in the substantially the same time.

The imaging system of 46. claims 38, wherein, each pixel section comprises optical sensitive material on the image element circuit of the pixel section for correspondence.

The imaging system of 47. claims 38, wherein, each pixel section comprises optical sensitive section in the first side of semiconductor substrate, and wherein said image element circuit comprises the reading circuit of the pixel section for correspondence in the second side of semiconductor substrate.

The imaging system of 48. claims 38, wherein, described charge storage storehouse comprises pinprick diode.

The imaging system of 49. claims 38, wherein, described switching device is transistor.

The imaging system of 50. claims 38, wherein, described switching device is diode.

The imaging system of 51. claims 38, wherein, described switching device is parasitic diode.

The imaging system of 52. claims 38, wherein, the switching device that described control circuit is configured in the substantially the same time to each image element circuit switches.

The imaging system of 53. claims 38, wherein, each pixel section comprises the first corresponding electrode and the second corresponding electrode, and the optical sensitive material of wherein corresponding pixel section is between first electrode and the second corresponding electrode of the correspondence of the pixel section of correspondence.

The imaging system of 54. claims 38, wherein, each image element circuit to be configured to when the switching device of the pixel section of correspondence is in the first state transfer charge between the first electrode to charge storage storehouse, and blocks from the first electrode to the Charger transfer in charge storage storehouse when the switching device of the pixel section of correspondence is in the second state.

The imaging system of 55. claims 38, wherein, described control circuit is configured in the substantially the same time, the switching device of each image element circuit is switched to the second state from the first state for each image element circuit after integrating time section.

The imaging system of 56. claims 38, wherein, each image element circuit also comprises reset circuit, and reset circuit is configured to the voltage difference resetting optical sensitive material two ends when switching device is in the second state.

The imaging system of 57. claims 38, wherein, the reading circuit that the side that each image element circuit is also included in semiconductor substrate is formed below described multiple pixel section.

The imaging system of 58. claims 38, wherein, described optical sensitive material is the continuous film of nano crystal material.

The imaging system of 59. claims 38, it also comprises: analog to digital change-over circuit, in order to generate digital pixel numerical value from the signal read from the image element circuit corresponding to each image sensor array; And processor, be configured to process in the first mode of operation correspond at least two image sensor arrays pixel number to generate output image.

The imaging system of 60. claims 59, wherein, described output image has the zoom level between at least one secondary image sensor array and zoom level of primary image sensor array being in and being used to generate described output image.

The imaging system of 61. claims 38, also comprise processor, described processor is configured to during selected operator scheme, generate output image when the amendment not based on the image projected on secondary image sensor array according to the pixel number corresponding to primary image sensor array.

The imaging system of 62. claims 38, wherein, described primary image sensor array comprises the number of pixels of the complete resolution corresponding to imaging system, and wherein each secondary image sensor array comprises the number of pixels of the complete resolution being less than imaging system.

The imaging system of 63. claims 62, wherein, export the image corresponding to primary image sensor array when selection the first zoom level, and export the image generated from primary image sensor array and at least one secondary image sensor array when selecting different zoom level.

64. 1 kinds of imaging systems, comprising:

Imageing sensor, comprise the offset array of the pixel electrode for reading signal from this imageing sensor, the array of wherein said pixel electrode is less than the size of the pixel section of imageing sensor by the amount offset; And

Be configured to select an offset array of pixel electrode for the circuit reading signal from imageing sensor.

The imaging system of 65. claims 64, also comprises the circuit for reading view data from each offset array of pixel electrode, and for combining the view data thus the circuit of generation output image that read from each offset array of pixel electrode.

66. 1 kinds of imaging systems, comprising:

First image sensor array, comprises the offset array for the pixel electrode from the first image sensor array read output signal, and the array of wherein said pixel electrode is less than the size of the pixel section of the first imageing sensor by the amount offset;

Second image sensor array;

Be configured to select an offset array of pixel electrode for the circuit from the first image sensor array read output signal; And

For reading the circuit of view data from the first image sensor array and the second image sensor array.

The imaging system of 67. claims 66, also comprises the circuit for generating output image from the view data corresponding to the first image sensor array and the second image sensor array.

The imaging system of 68. claims 67, wherein, be configured to select the circuit of an offset array of pixel electrode to be configured to select the following offset array of pixel electrode: described offset array is providing the highest super-resolution time combined to the view data from the first image sensor array and the view data from the second image sensor array.

The imaging system of 69. claims 67, wherein, is configured to select the circuit of an offset array of pixel electrode to be configured to select to provide the offset array of the pixel electrode overlapping with the minimum image of the second image sensor array.

70. 1 kinds of methods from image sensor system synthetic image, described method comprises:

The first image of the primary importance set from each pixel section corresponding to the first image sensor array is read out from the first image sensor array; And

The second image of the second place set from each pixel section corresponding to the first image sensor array is read out from the first image sensor array.

The method of 71. claims 70, also comprises from the first image and the second Computer image genration output image.

72. 1 kinds of methods from image sensor system synthetic image, described method comprises:

The first image of the primary importance set from each pixel section corresponding to the first image sensor array is read out from the first image sensor array;

The second image of the second place set from each pixel section corresponding to the first image sensor array is read out from the first image sensor array;

The 3rd image is read from the second image sensor array; And

Utilize the first image, the second image and the 3rd image to select primary importance set or second place set, read successive image for from the first image sensor array.

The method of 73. claims 72, being also included in the time substantially the same with the successive image from the first image sensor array reads successive image from the second image sensor array.

The method of 74. claims 73, the successive image also comprised from reading from the second image sensor array generates super-resolution image with the successive image read from the first image sensor array.

The method of 75. claims 73, wherein, the second image sensor array points to the direction identical with the first image sensor array, and has the zoom level being different from the first image sensor array.