CN104935337A - Full-integrated low-loss digital-analog hybrid frequency divider - Google Patents
Full-integrated low-loss digital-analog hybrid frequency divider Download PDFInfo
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Abstract
The invention relates to a full-integrated low-loss digital-analog hybrid frequency divider. The full-integrated low-loss digital-analog hybrid frequency divider comprises a phase frequency detector, a charge pump, a voltage controlled oscillator, a loop filter and a pre-divider which are successively connected from the front to the back, wherein a digital-analog hybrid frequency divider module is arranged between the pre-divider and the phase frequency detector, the digital-analog hybrid frequency divider module is composed of an analog frequency divider and a digital frequency divider which are successively connected from the front to the back, the input end of the phase frequency detector is connected with the output end of the digital-analog hybrid frequency divider module, and the input end of the digital-analog hybrid frequency divider module is connected with the output end of the pre-divider. According to the technical scheme, a digital-analog hybrid frequency division technology is employed, an analogue frequency divider portion employs a current mode logic (CML) circuit so as to be adapted to frequency division under a high frequency condition, and when a frequency is divided to 64Mhz, the frequency is divided to 4Mhz by use of the digital frequency divider. Such arrangement can help to reduce the chip area and power consumption. Besides, the CML circuit is employed under the high-frequency condition so that high-quality frequency division signals can be obtained.
Description
Technical field
The present invention relates to phase-locked loop field, be specifically related to a kind of fully integrated low-power consumption numerical model analysis frequency divider.
Background technology
Frequency divider is one of circuit module important in cycle of phase-locked loop, in phase-locked loop, the phase place of the phase place of the output signal of allocator module and frequency and input reference signal Vref and frequency are carried out frequency and phase discrimination, signal after frequency and phase discrimination produces after radio-frequency (RF) local oscillator signal through voltage controlled oscillator and enters allocator module, realizes frequency division by allocator module.Previous phase-locked loop allocator module just uses the mode of simulation frequency division to realize, not integrated digital frequency division module, such design is not sufficient to the needs of frequency division in performance under adaptation high frequency situations, and the problem such as digital frequency division model calling outside sheet can produce power consumption to phase-locked loop chip and area occupied is larger, high-precision frequency synthesizer technique now cannot be met gradually, as extracted reference carrier for coherent demodulation, set up bit synchronization etc.
Summary of the invention
Object of the present invention is just to provide a kind of fully integrated low-power consumption numerical model analysis frequency divider, and it can effectively solve the problem, and obtains high-quality fractional frequency signal, reduces chip area, reduces power consumption.
For achieving the above object, the present invention implements by the following technical solutions:
A kind of fully integrated low-power consumption numerical model analysis frequency divider; it is characterized in that: the phase frequency detector connected in turn before and after comprising, charge pump, voltage-controlledly wholely swing device, loop filter and pre-divider; numerical model analysis allocator module is provided with between pre-divider and phase frequency detector; the analogous frequency divider that numerical model analysis allocator module is connected in turn by front and back and digital frequency divider form; the input of phase frequency detector is connected with the output of numerical model analysis allocator module, and the input of numerical model analysis allocator module is connected with the output of pre-divider.
In technique scheme, adopt numerical model analysis frequency splitting technology, analogous frequency divider part adopts current mode logic (CML) circuit, and to adapt to the frequency division in high-frequency situation, when frequency division is to 64MHz, employing digital frequency divider completes the frequency division to 4MHz.Such arrangement can reduce chip area, reduces power consumption.And adopt CML circuit under high frequency situations, high-quality fractional frequency signal can be obtained.
Accompanying drawing explanation
Fig. 1 is structure principle chart of the present invention;
Fig. 2 is the circuit structure schematic diagram of phase frequency detector;
Fig. 3 is the circuit structure schematic diagram of buffer stage block;
Fig. 4 is the circuit theory diagrams of two divided-frequency module;
Fig. 5 is the circuit theory diagrams of digital frequency divider.
Embodiment
In order to make objects and advantages of the present invention clearly understand, below in conjunction with embodiment, the present invention is specifically described.Should be appreciated that following word only in order to describe one or more concrete execution modes of the present invention, considered critical is not carried out to the protection range that the present invention specifically asks.
The technical scheme that the present invention takes as shown in Figure 1, a kind of fully integrated low-power consumption numerical model analysis frequency divider, the phase frequency detector 11 connected in turn before and after comprising, charge pump 12, voltage-controlledly wholely swing device 13, loop filter 14 and pre-divider 15, numerical model analysis allocator module is provided with between pre-divider 15 and phase frequency detector 11, the analogous frequency divider 16 that numerical model analysis allocator module is connected in turn by front and back and digital frequency divider 17 form, the input of phase frequency detector 11 is connected with the output of numerical model analysis allocator module, the input of numerical model analysis allocator module is connected with the output of pre-divider.Analogous frequency divider 16 module adopts current mode logic (CML) circuit, and digital frequency divider 17 adopts digital DFF trigger to form.The present invention, on conventional divider architecture basics, adopts the mode of integrated numerical model analysis frequency division, reduces chip area, reduces power consumption, and adopts CML circuit under high frequency situations, can obtain high-quality fractional frequency signal.Charge pump 12, voltage-controlled whole enforcement of swinging device 13, loop filter 14 and pre-divider 15 can refer to conventional phase locked loops frequency divider.
Below by way of concrete enforcement, the present invention is specifically described:
Fig. 2 is the circuit structure schematic diagram of phase frequency detector 11, and circuit structure comprises two d type flip flops and one and door.Phase frequency detector 11 comprises trigger DA, DB and connects supply voltage with the D input of door AND, trigger DA, the CLK input access signal A of trigger DA, and the output QA of trigger DA connects high potential UP; The D input end grounding of trigger DB, the CLK input access signal B of trigger DB, the output QB of trigger DB connects electronegative potential DOWN; The set input RESET of trigger DA, DB is connected; Be connected high potential UP and electronegative potential DOWN respectively with the input of door AND, be connected the set input RESET of trigger DA, DB respectively with the output of door AND.The effect of phase frequency detector 11 is the frequency of output feedback signal and the effect of phase difference of differentiating input reference signal Vref and numerical model analysis allocator module, and signal A, B represent the output feedback signal of input reference signal Vref and numerical model analysis allocator module respectively.
The buffer stage block that analogous frequency divider 16 is connected in turn by front and back and two divided-frequency module form, and the specific embodiments of buffer stage block and two divided-frequency module as shown in Figure 3,4.
Buffer stage block comprises transistor M1, M2, M3, M4, M5, M10, M11, M16, M17 and resistance R5, R6; The grid of transistor M4, M10 connects positive input terminal V1+, V2+ of buffer stage block respectively, and the grid of transistor M5, M11 connects negative input end V1-, V2-of buffer stage block respectively; One end of resistance R6 be connected with the drain electrode of transistor M17 and both contact access buffer stage block positive output end Vout+, one end of resistance R5 be connected with the drain electrode of transistor M16 and both contact access buffer stage block negative output terminal Vout-, the other end of resistance R5, R6 is connected with one end of resistance R7 respectively; The drain electrode of transistor M1 connects the source electrode of transistor M4, M5 respectively, and the drain electrode of transistor M4 connects the drain electrode of transistor M6, M8 and one end of resistance R1 respectively, and the drain electrode of transistor M5 connects the drain electrode of transistor M9, M7 and one end of resistance R2 respectively; The drain electrode of transistor M2 connects the source electrode of transistor M10, M11 respectively, the drain electrode of transistor M10 connects the drain electrode of transistor M12, M14 and one end of resistance R3 respectively, and the drain electrode of transistor M11 connects the drain electrode of transistor M13, M15 and one end of resistance R4 respectively; The equal ground connection of the other end of resistance R1, R2, R3, R4, R7; The drain electrode of transistor M3 connects the source electrode of transistor M16, M17 respectively, and the source electrode of transistor M8, M9, M14, M15 is connected and is connected to the grid of transistor M16, and the source electrode of transistor M6, M7, M12, M13 is connected and is connected to the grid of transistor M17; The grid of transistor M6, M9 meets signal A1, and the grid of transistor M7, M8 meets signal A3, and the grid of transistor M13, M14 meets signal A0, and the grid of transistor M12, M15 meets signal A2.
Two divided-frequency module comprises transistor M18, M19, the source ground of transistor M18, M19, the grid of transistor M18, M19 all connects bias voltage Vbias, the drain electrode of transistor M18 connects the source electrode of transistor M20, M21 respectively, the drain electrode of transistor M19 connects the source electrode of transistor M22 and transistor M23 respectively, the grid of transistor M20, M23 connects clock signal C K respectively, and the grid of transistor M21, M22 connects clock signal C Kb respectively; The drain electrode of transistor M20 connects the source electrode of transistor M24, M25 respectively, the drain electrode of transistor M21 connects the source electrode of transistor M26, M27 respectively, the drain electrode of transistor M22 connects the source electrode of transistor M28, M29 respectively, and the drain electrode of transistor M23 connects the source electrode of transistor M30, M31 respectively; The grid of transistor M24 connects the drain electrode of transistor M31, the grid of transistor M25 connects the drain electrode of transistor M30, drain electrode one end of contact resistance R8 and the drain electrode of transistor M26 respectively of transistor M24, drain electrode one end of contact resistance R9 and the drain electrode of transistor M27 respectively of transistor M25, the grid of transistor M26 connects the drain electrode of transistor M27, the drain electrode of transistor M26 connects positive output end Vout2+, the grid of transistor M27 connects the drain electrode of transistor M26, and the drain electrode of transistor M27 connects negative output terminal Vout2-; Drain electrode one end of contact resistance R10 and the drain electrode of transistor M30 respectively of transistor M28, drain electrode one end of contact resistance R11 and the drain electrode of transistor M31 respectively of transistor M29, the grid of transistor M28 connects the drain electrode of transistor M26, the grid of transistor M29 connects the drain electrode of transistor M27, the grid of transistor M30 connects the drain electrode of transistor M31, the grid of transistor M31 connects the drain electrode of transistor M30, the other end ground connection of resistance R8, R9, R10, R11.Voltage Vbias provides bias voltage for external circuit, and clock signal C K, CKb are the input signal of external circuit.
Fig. 5 is the circuit theory diagrams of digital frequency divider 17, and CP is the clock control signal of circuit, and D is the input signal of circuit, Q and
for the output signal of circuit, Q with
oppositely, output signal Q only just can follow the state of input signal D by electronegative potential to the high switch instant putting position in CP clock signal and change, other time signal Q then remain unchanged.Two inputs of NAND gate NAND4 meet input signal D and clock signal C P respectively, two inputs of NAND gate NAND3 connect the output of clock signal C P and NAND gate NAND4 respectively, two inputs of NAND gate NAND2 connect the output of NAND gate NAND4 and the output of NAND gate NAND1 respectively, two inputs of NAND gate NAND1 connect the output of NAND gate NAND3 and the output of NAND gate NAND2 respectively, the output signal of NAND gate NAND2 is the output signal of Q, NAND gate NAND
Fully integrated low-power consumption numerical model analysis frequency divider provided by the invention; adopt numerical model analysis frequency splitting technology; analogous frequency divider 16 part adopts current mode logic (CML) circuit; to adapt to the frequency division in high-frequency situation; when frequency division is to 64MHz, employing digital frequency divider 17 completes the frequency division to 4MHz.Such arrangement can reduce chip area, reduces power consumption.And adopt CML circuit under high frequency situations, high-quality fractional frequency signal can be obtained.
The above is only the preferred embodiment of the present invention; should be understood that; for those skilled in the art; to know in the present invention after contents; under the premise without departing from the principles of the invention; can also make some equal conversion to it and substitute, these convert on an equal basis and substitute and also should be considered as belonging to protection scope of the present invention.
Claims (3)
1. a fully integrated low-power consumption numerical model analysis frequency divider; it is characterized in that: the phase frequency detector connected in turn before and after comprising, charge pump, voltage-controlledly wholely swing device, loop filter and pre-divider; numerical model analysis allocator module is provided with between pre-divider and phase frequency detector; the analogous frequency divider that numerical model analysis allocator module is connected in turn by front and back and digital frequency divider form; the input of phase frequency detector is connected with the output of numerical model analysis allocator module, and the input of numerical model analysis allocator module is connected with the output of pre-divider.
2. fully integrated low-power consumption numerical model analysis frequency divider according to claim 1, it is characterized in that: the buffer stage block that analogous frequency divider is connected in turn by front and back and two divided-frequency module form, and buffer stage block comprises transistor M1, M2, M3, M4, M5, M10, M11, M16, M17 and resistance R5, R6; The grid of transistor M4, M10 connects positive input terminal V1+, V2+ of buffer stage block respectively, and the grid of transistor M5, M11 connects negative input end V1-, V2-of buffer stage block respectively; One end of resistance R6 be connected with the drain electrode of transistor M17 and both contact access buffer stage block positive output end Vout+, one end of resistance R5 be connected with the drain electrode of transistor M16 and both contact access buffer stage block negative output terminal Vout-, the other end of resistance R5, R6 is connected with one end of resistance R7 respectively; The drain electrode of transistor M1 connects the source electrode of transistor M4, M5 respectively, and the drain electrode of transistor M4 connects the drain electrode of transistor M6, M8 and one end of resistance R1 respectively, and the drain electrode of transistor M5 connects the drain electrode of transistor M9, M7 and one end of resistance R2 respectively; The drain electrode of transistor M2 connects the source electrode of transistor M10, M11 respectively, the drain electrode of transistor M10 connects the drain electrode of transistor M12, M14 and one end of resistance R3 respectively, and the drain electrode of transistor M11 connects the drain electrode of transistor M13, M15 and one end of resistance R4 respectively; The equal ground connection of the other end of resistance R1, R2, R3, R4, R7; The drain electrode of transistor M3 connects the source electrode of transistor M16, M17 respectively, and the source electrode of transistor M8, M9, M14, M15 is connected and is connected to the grid of transistor M16, and the source electrode of transistor M6, M7, M12, M13 is connected and is connected to the grid of transistor M17; The grid of transistor M6, M9 meets signal A1, and the grid of transistor M7, M8 meets signal A3, and the grid of transistor M13, M14 meets signal A0, and the grid of transistor M12, M15 meets signal A2;
Two divided-frequency module comprises transistor M18, M19, the source ground of transistor M18, M19, the grid of transistor M18, M19 all connects bias voltage Vbias, the drain electrode of transistor M18 connects the source electrode of transistor M20, M21 respectively, the drain electrode of transistor M19 connects the source electrode of transistor M22 and transistor M23 respectively, the grid of transistor M20, M23 connects clock signal C K respectively, and the grid of transistor M21, M22 connects clock signal C Kb respectively; The drain electrode of transistor M20 connects the source electrode of transistor M24, M25 respectively, the drain electrode of transistor M21 connects the source electrode of transistor M26, M27 respectively, the drain electrode of transistor M22 connects the source electrode of transistor M28, M29 respectively, and the drain electrode of transistor M23 connects the source electrode of transistor M30, M31 respectively; The grid of transistor M24 connects the drain electrode of transistor M31, the grid of transistor M25 connects the drain electrode of transistor M30, drain electrode one end of contact resistance R8 and the drain electrode of transistor M26 respectively of transistor M24, drain electrode one end of contact resistance R9 and the drain electrode of transistor M27 respectively of transistor M25, the grid of transistor M26 connects the drain electrode of transistor M27, the drain electrode of transistor M26 connects positive output end Vout2+, the grid of transistor M27 connects the drain electrode of transistor M26, and the drain electrode of transistor M27 connects negative output terminal Vout2-; Drain electrode one end of contact resistance R10 and the drain electrode of transistor M30 respectively of transistor M28, drain electrode one end of contact resistance R11 and the drain electrode of transistor M31 respectively of transistor M29, the grid of transistor M28 connects the drain electrode of transistor M26, the grid of transistor M29 connects the drain electrode of transistor M27, the grid of transistor M30 connects the drain electrode of transistor M31, the grid of transistor M31 connects the drain electrode of transistor M30, the other end ground connection of resistance R8, R9, R10, R11.
3. fully integrated low-power consumption numerical model analysis frequency divider according to claim 1 and 2, it is characterized in that: digital frequency divider comprises NAND gate NAND4, NAND3, NAND2, NAND1, two inputs of NAND gate NAND4 connect input signal D and clock signal C P respectively, two inputs of NAND gate NAND3 connect the output of clock signal C P and NAND gate NAND4 respectively, two inputs of NAND gate NAND2 connect NAND gate NAND4 respectively, the output of NAND1, two inputs of NAND gate NAND1 connect NAND gate NAND3 respectively, the output of NAND2, the output signal of NAND gate NAND2 is Q, the output signal of NAND gate NAND is
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017146833A3 (en) * | 2016-02-23 | 2017-10-19 | Qualcomm Incorporated | Current steering phase control for cml circuits |
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| US6859109B1 (en) * | 2003-05-27 | 2005-02-22 | Pericom Semiconductor Corp. | Double-data rate phase-locked-loop with phase aligners to reduce clock skew |
| US20070026816A1 (en) * | 2005-06-01 | 2007-02-01 | Wilinx, Inc. | High frequency synthesizer circuits and methods |
| CN200962589Y (en) * | 2006-11-02 | 2007-10-17 | 熊猫电子集团有限公司 | Ultra-small frequency synthesizer |
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Application publication date: 20150923 |