CN104934325B - A kind of doping method of semiconductor devices - Google Patents
A kind of doping method of semiconductor devices Download PDFInfo
- Publication number
- CN104934325B CN104934325B CN201410105802.9A CN201410105802A CN104934325B CN 104934325 B CN104934325 B CN 104934325B CN 201410105802 A CN201410105802 A CN 201410105802A CN 104934325 B CN104934325 B CN 104934325B
- Authority
- CN
- China
- Prior art keywords
- sull
- semiconductor structure
- doping
- doping method
- fin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of doping method of semiconductor devices, it is characterised in that including:Semiconductor structure is provided;Sull is formed on semiconductor structure, the sull is B2O3Or P2O5;Thermal annealing is carried out, annealing temperature is higher than 600 DEG C, to cause the doping Particle diffusion in sull into semiconductor structure;Remove residual oxide film.The present invention will not cause to damage while the doping of guarantor's type is realized, reduce unnecessary damage, reduce electric leakage, improve the performance of device to semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of doping method of semiconductor devices.
Background technology
Highly integrated with semiconductor devices, MOSFET channel length constantly shortens, a series of in the long raceway grooves of MOSFET
Negligible effect becomes more notable in model.It is proposed to this end that the three-dimensional device of fin formula field effect transistor (Fin-FET)
Part structure, Fin-FET are the transistors for having fin channel structure, and it increases work by the use of several surfaces of thin fin as raceway groove
Make electric current.
In the preparation process of Fin-FET devices, source and drain doping is carried out on fin (Fin), and this requires device in fin
Top it is consistent with two side doping concentrations, i.e., guarantor's type adulterate.
It is more in the industry at present that the doping of guarantor's type is reached using the method for angled ion injection or Plasma immersion injection,
However, traditional angled ion can be influenceed the integrated level of device by Fin effect of distance when being infused in Fin doping, and wait
Gas ions injection can realize preferable guarantor's type doping, but wide-angle injection and plasma injection all can be due to Ions Bombardments
Influence to Fin produce damage, so as to deteriorate the electric leakage of knot.
The content of the invention
The purpose of the present invention is intended at least solve one of above-mentioned technological deficiency, there is provided a kind of manufacturer of semiconductor devices
Method, reduce and leaked electricity during adulterating, and realize that guarantor's type adulterates.
Therefore, the invention provides following technical scheme:
A kind of doping method of semiconductor devices, including:
Semiconductor structure is provided;
Sull is formed on semiconductor structure, the sull is B2O3Or P2O5;
Thermal annealing is carried out, annealing temperature is higher than 600 DEG C, to cause sull at least partly to gasify, and causes oxidation
Doping Particle diffusion in thing film is into semiconductor structure, and in thermal annealing process, the sull is exposed to outer;
Remove residual oxide film.
Optionally, the semiconductor structure is fin.
Optionally, the sull is formed using the method for electron beam evaporation.
Optionally, annealed using rapid thermal anneal process.
Optionally, the thickness of the sull is 1-10nm.
Optionally, the temperature of thermal annealing is 700-1000 DEG C.
Optionally, the time of thermal annealing is 1-30s.
The doping method of semiconductor devices provided in an embodiment of the present invention, the shape on the semiconductor structure for needing to be doped
Into B2O3Or P2O5Sull, the fusing point of the film is relatively low, in thermal annealing, the gasification of most of film, realizes
While guarantor's type adulterates, semiconductor structure will not be caused to damage, reduce unnecessary damage, reduced electric leakage, improve device
Performance.
Brief description of the drawings
Of the invention above-mentioned and/or additional aspect and advantage will become from the following description of the accompanying drawings of embodiments
Substantially and it is readily appreciated that, wherein:
Fig. 1 is the schematic flow sheet according to the doping method of the semiconductor devices of the embodiment of the present invention;
Fig. 2-Fig. 6 shows that method according to embodiments of the present invention forms the section signal in each stage of semiconductor devices
Figure.
Embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not construed as limiting the claims.
As the description of background technology, in order to realize that guarantor's type adulterates, while reduce electric leakage, the present invention proposes one kind and partly led
The doping method of body device, with reference to shown in figure 1, including:
Semiconductor structure is provided;
Sull is formed on semiconductor structure, the sull is B2O3Or P2O5;
Thermal annealing is carried out, annealing temperature is higher than 600 DEG C, to cause the doping Particle diffusion in sull to semiconductor
In structure;
Remove residual oxide film.
In the present invention, B is formd on the semiconductor structure for needing to be doped2O3Or P2O5Sull, should
The fusing point of film is relatively low, and in thermal annealing, most of film gasification, will not be to semiconductor while realizing the doping of guarantor's type
Structure causes to damage, and reduces unnecessary damage, reduces electric leakage, improves the performance of device.
In order to be better understood from the present invention, it is described in detail below with reference to specific embodiment, in the embodiment
In, illustrated exemplified by applying on the semiconductor structure of fin, but it is understood that, this method is not limited to be applied to this
Place, can be applied on other devices, such as plane silicon substrate or germanium base device.
First, there is provided substrate 200, with reference to shown in figure 2.
In the present embodiment, the substrate is SOI substrate 200, and SOI substrate 200 includes backing bottom 200-1, oxygen buried layer
200-2 and top layer silicon 200-3.In other embodiments, the substrate can also be other substrat structures for including semiconductor layer.
Then, fin 204 is formed, as shown in Figure 4.
Mask material, such as silicon nitride can be deposited on top layer silicon 200-3, then the graphical mask layer 202, such as schemes
Shown in 3.Then, using lithographic technique, such as RIE (reactive ion etching) method, top layer silicon 200-3 is etched, so as to push up
Fin 202 is formed in layer silicon 200-3, as shown in Figure 4.
Then, sull 206 is formed on the fin 202, the sull is B2O3Or P2O5, such as Fig. 5 institutes
Show.
Can by the method for electron beam evaporation on the surface of fin deposition oxide film 206, the side of electron beam evaporation
Method can cause each surface uniform deposition sull, and in the present embodiment, the thickness of sull can be 1-10nm.
B2O3Or P2O5Film there is relatively low fusing point, can gasify when higher than 600 DEG C.
Then, thermal annealing is carried out, the temperature of thermal annealing is higher than 600 DEG C.
In the present embodiment, annealed using rapid thermal annealing (RTP) technique, the temperature of annealing can be controlled in 700-
1000 degrees Celsius, the time of annealing is 1-30s, and under this annealing temperature, most sull is gasified, meanwhile, B or
P ion is diffused into fin, doped region 208 is formed, with reference to shown in figure 6.The adjustment for the temperature and time that this method passes through annealing, it is real
The regulation of junction depth and doping concentration is now adulterated, the doping of guarantor's type is easy to implement, further, since most sull is being annealed
During all gasified, the residual oxide on fin surface need to only be removed, fin surface will not be caused to damage, reduce leakage
Electricity, improve the performance of device.
Finally, residual oxide film is removed, as shown in Figure 6.
In the present embodiment, DHF (dilute hydrofluoric acid) can be used to remove the sull of fin remained on surface.
So far the doped region of the semiconductor devices of the present embodiment is formd.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention, the technical spirit according to the present invention is to made for any of the above embodiments any simple
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (7)
- A kind of 1. doping method of semiconductor devices, it is characterised in that including:Semiconductor structure is provided;Sull is formed on semiconductor structure, the sull is B2O3Or P2O5;Thermal annealing is carried out, annealing temperature is higher than 600 DEG C, to cause sull at least partly to gasify, and make it that oxide is thin Doping Particle diffusion in film is into semiconductor structure, and in thermal annealing process, the sull is exposed to outer;Remove residual oxide film.
- 2. doping method according to claim 1, it is characterised in that the semiconductor structure is fin.
- 3. doping method according to claim 1, it is characterised in that the oxidation is formed using the method for electron beam evaporation Thing film.
- 4. doping method according to claim 1, it is characterised in that annealed using rapid thermal anneal process.
- 5. doping method according to claim 1, it is characterised in that the thickness of the sull is 1-10nm.
- 6. doping method according to claim 1, it is characterised in that the temperature of thermal annealing is 700-1000 DEG C.
- 7. doping method according to claim 6, it is characterised in that the time of thermal annealing is 1-30s.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410105802.9A CN104934325B (en) | 2014-03-20 | 2014-03-20 | A kind of doping method of semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410105802.9A CN104934325B (en) | 2014-03-20 | 2014-03-20 | A kind of doping method of semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104934325A CN104934325A (en) | 2015-09-23 |
CN104934325B true CN104934325B (en) | 2018-04-06 |
Family
ID=54121434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410105802.9A Active CN104934325B (en) | 2014-03-20 | 2014-03-20 | A kind of doping method of semiconductor devices |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104934325B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017113266A1 (en) * | 2015-12-31 | 2017-07-06 | 上海凯世通半导体有限公司 | Finfet doping method |
CN112885715A (en) * | 2021-01-08 | 2021-06-01 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102237278A (en) * | 2010-04-28 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Method for doping fin field-effect transistors |
CN103594341A (en) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | A semiconductor structure, a doping method thereof, and a method for forming a fin field effect transistor |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8785286B2 (en) * | 2010-02-09 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Techniques for FinFET doping |
-
2014
- 2014-03-20 CN CN201410105802.9A patent/CN104934325B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102237278A (en) * | 2010-04-28 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Method for doping fin field-effect transistors |
CN103594341A (en) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | A semiconductor structure, a doping method thereof, and a method for forming a fin field effect transistor |
Also Published As
Publication number | Publication date |
---|---|
CN104934325A (en) | 2015-09-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102010140B1 (en) | Forming doped regions in semiconductor strips | |
CN104124273B (en) | There is MOS device of strained buffer layer and forming method thereof | |
US8969157B2 (en) | Method of manufacturing semiconductor device having field plate electrode | |
US9825151B2 (en) | Method for preparing substrate using germanium condensation process and method for manufacturing semiconductor device using same | |
US20160233105A1 (en) | Method of forming a trench in a semiconductor device | |
CN102956492B (en) | Semiconductor structure and manufacture method thereof and MOS (metal oxide semiconductor) transistor and manufacture method thereof | |
CN106653844A (en) | Fin field effect transistor and forming method thereof | |
CN106158957A (en) | Transverse diffusion metal oxide semiconductor field effect pipe and manufacture method thereof | |
US20200006529A1 (en) | Method for manufacturing isolation structure for ldmos | |
CN104934325B (en) | A kind of doping method of semiconductor devices | |
TW201715612A (en) | Semiconductor structure and method for forming the same | |
WO2016045377A1 (en) | Method for preparing nanoscale field effect transistor | |
CN108231594A (en) | A kind of production method of FinFET | |
CN105226022A (en) | The formation method of semiconductor structure | |
JP2018505552A (en) | Method for manufacturing lateral insulated gate bipolar transistor | |
CN106876465A (en) | The gate oxide structure and process of MOS device | |
US20150303302A1 (en) | Semiconductor device and formation thereof | |
CN104183500A (en) | Method for forming ion-implantation side wall protection layer on FinFET device | |
CN104599972B (en) | A kind of semiconductor devices and forming method thereof | |
US9601624B2 (en) | SOI based FINFET with strained source-drain regions | |
CN103794482B (en) | The forming method of metal gates | |
CN106571298A (en) | Formation method of semiconductor structure | |
CN104716044B (en) | Semiconductor devices and forming method thereof | |
US8669616B2 (en) | Method for forming N-shaped bottom stress liner | |
CN104167363A (en) | Method for forming ion injection side wall protecting layer on FinFET device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |