CN104899008B - Shared storage organization in parallel processor and method - Google Patents
Shared storage organization in parallel processor and method Download PDFInfo
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- CN104899008B CN104899008B CN201510346816.4A CN201510346816A CN104899008B CN 104899008 B CN104899008 B CN 104899008B CN 201510346816 A CN201510346816 A CN 201510346816A CN 104899008 B CN104899008 B CN 104899008B
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Abstract
The invention belongs to field of computer architecture, the more particularly to information storage in parallel processor and transmission.Its technical solution is：A kind of shared storage organization in parallel processor, including：Several information channels read and write dual-channel memory, several multicast counter groups and moderator.The present invention provides the information transmission mechanisms between parallel processor multithreading, realize the multicast transmission of information, usually only need a clock that can complete memory access mutual exclusion inspection, greatly reduce communication overhead and power consumption.The structure of the present invention can also efficiently realize concurrent operation with method on programmable processor array.
Description
Technical field
The invention belongs to field of computer architecture, more particularly to are passed using information between the thread in parallel processor
Pass data exchange and the storage of mechanism.
Background technology
Modern computing machine architecture improves its processing capacity in a manner of multiprocessor, multi-threaded parallel, this mode is wanted
It asks and exchanges information to low overhead between multithreading.And the information of cross-thread transmits mutual exclusion of the generally use by software realization at present
Mechanism, efficiency is very low, realizes also very complicated.
Invention content
The purpose of the present invention is：There is provided between a kind of multithreading dedicated for multiprocessor using information transmission mechanism,
The shared storage organization and method of data exchange efficiently complete the information exchange of multithreading between processor in parallel machine.
The technical scheme is that：A kind of shared storage organization in parallel processor, it is characterized in that：It includes：Number
A information channel reads and writes dual-channel memory, several multicast counter groups and moderator；
Several information channels respectively connect multiple parallel processors, and each parallel processor executes 2-16 line
Journey；Several information channels include：Address signal line end, storage enable signal line end, read-write selection signal line end, word
Signal line end, input data signal line end, outputting data signals line end, output useful signal line end are selected in selected parts；The input number
It is believed that a number line end includes：Input data line end, multicast count line end and obstruction/non-blocking mode line end；
The read-write dual-channel memory is used to access the data that the cross-thread transmits, and data width is 4 bytes, energy
Byte access is enough pressed, data are 32 single precision words or 64 double precision words；
Several multicast counter groups respectively contain n counter, and the counter counts letter for recording multicast
Breath, is chosen by address signal, and corresponding signal control reads and writes and decrement operations；
The moderator executes repeating query arbitration algorithm, selects a thread to the read-write dual-channel memory every time
It is written and read.
A kind of shared storage method in parallel processor, the shared storage organization in its upper described parallel processor,
And execute following operation：
A. the write operation of blocking model
A1. when several threads from described information channel ask to write data to the dual-channel memory simultaneously, by
The moderator chooses one of thread, and exports the address signal that the thread provides；
A2. a multicast counter group is chosen by minimum 1-2 of described address signal, by described address signal
Other are chosen corresponding counter in the multicast counter group, check whether the value of the counter is 0；
A3. if it is 0, the multicast which is provided, which counts, is written the counter, the output useful signal line end
1 is set, giving address according to the thread writes data into the dual-channel memory；Otherwise,
A4. the output useful signal line end is set to 0, the failure of this write operation；
B. the read operation of blocking model
B1. when several threads from described information channel ask to read data from the dual-channel memory simultaneously, by
The moderator chooses one of thread, and exports the address signal that the thread provides, which is also used for selecting institute
State a byte of dual-channel memory；
B2. a multicast counter group is chosen by minimum 1-2 of described address signal, by described address signal
Other are chosen corresponding counter in the multicast counter group, check whether the value of the counter is more than 0；
B3. if it is greater than 0, then the Counter Value is subtracted 1, the output useful signal line end sets 1, given according to the thread
Read the specified bytes of the dual-channel memory in address；Otherwise,
B4. the output useful signal line end is set to 0, this read operation failure；
C. the write operation of non-blocking mode
C1. when several threads from described information channel ask to write data to the dual-channel memory simultaneously, by
The moderator chooses one of thread, and exports the address signal that the thread provides；
C2. a multicast counter group is chosen by minimum 1-2 of described address signal, by described address signal
Other are chosen corresponding counter in the multicast counter group；
C3. the multicast thread provided, which counts, is written the counter, and the output useful signal line end sets 1, according to this
Thread gives address and writes data into the dual-channel memory；
D. the read operation of non-blocking mode
D1. when several threads from described information channel ask to read data from the dual-channel memory simultaneously, by
The moderator chooses one of thread, and exports the address signal that the thread provides, which is also used for selecting institute
State a byte of dual-channel memory；
D2. a multicast counter group is chosen by minimum 1-2 of described address signal, by described address signal
Other are chosen corresponding counter in the multicast counter group, check whether the value of the counter is more than 0；
D3. if it is greater than 0, then the Counter Value is subtracted 1, the output useful signal line end sets 1, given according to the thread
Read the specified bytes of the dual-channel memory in address；Otherwise,
D4. the output useful signal line end is set to 0, this read operation failure.
The present invention provides the information transmission mechanisms between parallel processor multithreading, realize the multicast transmission of information, usually
It only needs a clock that can complete memory access mutual exclusion inspection, greatly reduces communication overhead and power consumption.The present invention structure with
Method can also efficiently realize concurrent operation on programmable processor array.
Description of the drawings
Attached drawing 1 is schematic structural view of the invention；
Attached drawing 2 is multicast counter group structural schematic diagram in the present invention；
Attached drawing 3 is the write operation flow chart of blocking model in the present invention；
Attached drawing 4 is the read operation flow chart of blocking model and non-blocking mode in the present invention；
Attached drawing 5 is the write operation flow chart of non-blocking mode in the present invention.
Specific implementation mode
Embodiment 1：Referring to attached drawing 1,2, the shared storage organization in a kind of parallel processor, it is characterized in that：It includes：Number
A information channel reads and writes dual-channel memory, several multicast counter groups and moderator；
Several information channels respectively connect multiple parallel processors, and each parallel processor executes 2-16 line
Journey；Several information channels include：Address signal line end, storage enable signal line end, read-write selection signal line end, word
Signal line end, input data signal line end, outputting data signals line end, output useful signal line end are selected in selected parts；The input number
It is believed that a number line end includes：Input data line end, multicast count line end and obstruction/non-blocking mode line end；
The read-write dual-channel memory is used to access the data that the cross-thread transmits, and data width is 4 bytes, energy
Byte access is enough pressed, data are 32 single precision words or 64 double precision words；
Several multicast counter groups respectively contain n counter, and the counter counts letter for recording multicast
Breath, is chosen by address signal, and corresponding signal control reads and writes and decrement operations；
The moderator executes repeating query arbitration algorithm, selects a thread to the read-write dual-channel memory every time
It is written and read.
Embodiment 2：Referring to attached drawing 1,2, the shared storage organization in parallel processor as described in Example 1, it is characterized in that：
The quantity in described information channel is 4, and each described information channel connects 4 parallel processors；
The quantity of the multicast counter group is 16, and the counter that each multicast counter group includes is 16,
Each counter is 3-4 bits, supports the data multicast of 6-8 cross-thread；
Described information, which is transmitted, shares the address space that storage organization occupies the parallel processor data storage, is mapped in this
The highest address part of data space.
Embodiment 3：Referring to attached drawing 3,4,5, the shared storage method in a kind of parallel processor, it is used such as embodiment 1
Or the shared storage organization in the parallel processor described in 2, and execute following operation：
A. the write operation of blocking model
A1. when several threads from described information channel ask to write data to the dual-channel memory simultaneously, by
The moderator chooses one of thread, and exports the address signal that the thread provides；
A2. a multicast counter group is chosen by minimum 1-2 of described address signal, by described address signal
Other are chosen corresponding counter in the multicast counter group, check whether the value of the counter is 0；
A3. if it is 0, the multicast which is provided, which counts, is written the counter, the output useful signal line end
1 is set, giving address according to the thread writes data into the dual-channel memory；Otherwise,
A4. the output useful signal line end is set to 0, the failure of this write operation；
B. the read operation of blocking model
B1. when several threads from described information channel ask to read data from the dual-channel memory simultaneously, by
The moderator chooses one of thread, and exports the address signal that the thread provides, which is also used for selecting institute
State a byte of dual-channel memory；
B2. a multicast counter group is chosen by minimum 1-2 of described address signal, by described address signal
Other are chosen corresponding counter in the multicast counter group, check whether the value of the counter is more than 0；
B3. if it is greater than 0, then the Counter Value is subtracted 1, the output useful signal line end sets 1, given according to the thread
Read the specified bytes of the dual-channel memory in address；Otherwise,
B4. the output useful signal line end is set to 0, this read operation failure；
C. the write operation of non-blocking mode
C1. when several threads from described information channel ask to write data to the dual-channel memory simultaneously, by
The moderator chooses one of thread, and exports the address signal that the thread provides；
C2. a multicast counter group is chosen by minimum 1-2 of described address signal, by described address signal
Other are chosen corresponding counter in the multicast counter group；
C3. the multicast thread provided, which counts, is written the counter, and the output useful signal line end sets 1, according to this
Thread gives address and writes data into the dual-channel memory；
D. the read operation of non-blocking mode
D1. when several threads from described information channel ask to read data from the dual-channel memory simultaneously, by
The moderator chooses one of thread, and exports the address signal that the thread provides, which is also used for selecting institute
State a byte of dual-channel memory；
D2. a multicast counter group is chosen by minimum 1-2 of described address signal, by described address signal
Other are chosen corresponding counter in the multicast counter group, check whether the value of the counter is more than 0；
D3. if it is greater than 0, then the Counter Value is subtracted 1, the output useful signal line end sets 1, given according to the thread
Read the specified bytes of the dual-channel memory in address；Otherwise,
D4. the output useful signal line end is set to 0, this read operation failure.
Claims (3)
1. the shared storage organization in a kind of parallel processor, it is characterized in that：It includes：Several information channels, read-write binary channels
Memory, several multicast counter groups and moderator；
Several information channels respectively connect multiple parallel processors, and each parallel processor executes 2-16 thread；
Several information channels include：Address signal line end, storage enable signal line end, read-write selection signal line end, byte
Selection signal line end, input data signal line end, outputting data signals line end, output useful signal line end；The input data
Signal line end includes：Input data line end, multicast count line end and obstruction or non-blocking mode line end；
The read-write dual-channel memory is used to access the data that the cross-thread transmits, the number for the data that the cross-thread transmits
Be 4 bytes according to width, can by byte access, data that the cross-thread transmits be 32 single precision word or 64
Double precision word；
Several multicast counter groups respectively contain n counter, and the counter is used to record multicast count information, by
Address signal is chosen, and corresponding signal control reads and writes and decrement operations；
The moderator executes repeating query arbitration algorithm, selects a thread to carry out the read-write dual-channel memory every time
Read-write.
2. the shared storage organization in parallel processor according to claim 1, it is characterized in that：
The quantity in described information channel is 4, and each described information channel connects 4 parallel processors；
The quantity of the multicast counter group is 16, and the counter that each multicast counter group includes is 16, each
The counter is 3-4 bits, supports the data multicast of 6-8 cross-thread；
The shared storage organization occupies the address space of the parallel processor data storage, is mapped in the ground of data storage
The highest address part in location space.
3. the shared storage method in a kind of parallel processor, it is used in parallel processor as claimed in claim 1 or 2
Shared storage organization, and execute following operation：
A. the write operation of blocking model
A1. when several threads from described information channel ask to write data to the dual-channel memory simultaneously, by described
Moderator chooses one of thread, and exports the address signal that the thread provides；
A2. a multicast counter group is chosen by minimum 1-2 of described address signal, by the other of described address signal
Corresponding counter in the multicast counter group is chosen in position, checks whether the value of the counter is 0；
A3. if it is 0, the multicast which is provided, which counts, is written the counter, and the output useful signal line end sets 1,
Address, which is given, according to the thread writes data into the dual-channel memory；Otherwise,
A4. the output useful signal line end is set to 0, the failure of this write operation；
B. the read operation of blocking model
B1. when several threads from described information channel ask to read data from the dual-channel memory simultaneously, by described
Moderator chooses one of thread, and exports the address signal that the thread provides, which is also used for selecting described double
One byte of channel memory；
B2. a multicast counter group is chosen by minimum 1-2 of described address signal, by the other of described address signal
Corresponding counter in the multicast counter group is chosen in position, checks whether the value of the counter is more than 0；
B3. if it is greater than 0, then the Counter Value is subtracted 1, the output useful signal line end sets 1, and address is given according to the thread
Read the specified bytes of the dual-channel memory；Otherwise,
B4. the output useful signal line end is set to 0, this read operation failure；
C. the write operation of non-blocking mode
C1. when several threads from described information channel ask to write data to the dual-channel memory simultaneously, by described
Moderator chooses one of thread, and exports the address signal that the thread provides；
C2. a multicast counter group is chosen by minimum 1-2 of described address signal, by the other of described address signal
Choose corresponding counter in the multicast counter group in position；
C3. the multicast thread provided, which counts, is written the counter, and the output useful signal line end sets 1, according to the thread
Given address writes data into the dual-channel memory；
D. the read operation of non-blocking mode
D1. when several threads from described information channel ask to read data from the dual-channel memory simultaneously, by described
Moderator chooses one of thread, and exports the address signal that the thread provides, which is also used for selecting described double
One byte of channel memory；
D2. a multicast counter group is chosen by minimum 1-2 of described address signal, by the other of described address signal
Corresponding counter in the multicast counter group is chosen in position, checks whether the value of the counter is more than 0；
D3. if it is greater than 0, then the Counter Value is subtracted 1, the output useful signal line end sets 1, and address is given according to the thread
Read the specified bytes of the dual-channel memory；Otherwise,
D4. the output useful signal line end is set to 0, this read operation failure.
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| CN1758229A (en) * | 2005-10-28 | 2006-04-12 | 中国人民解放军国防科学技术大学 | Local space shared memory method of heterogeneous multi-kernel microprocessor |
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| US7680988B1 (en) * | 2006-10-30 | 2010-03-16 | Nvidia Corporation | Single interconnect providing read and write access to a memory shared by concurrent threads |
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| US8392891B2 (en) * | 2008-06-26 | 2013-03-05 | Microsoft Corporation | Technique for finding relaxed memory model vulnerabilities |
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Patent Citations (5)
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| CN1781079A (en) * | 2003-06-11 | 2006-05-31 | 思科技术公司 | Maintaining entity order with gate managers |
| CN1758229A (en) * | 2005-10-28 | 2006-04-12 | 中国人民解放军国防科学技术大学 | Local space shared memory method of heterogeneous multi-kernel microprocessor |
| US7680988B1 (en) * | 2006-10-30 | 2010-03-16 | Nvidia Corporation | Single interconnect providing read and write access to a memory shared by concurrent threads |
| US8392891B2 (en) * | 2008-06-26 | 2013-03-05 | Microsoft Corporation | Technique for finding relaxed memory model vulnerabilities |
| CN102622192A (en) * | 2012-02-27 | 2012-08-01 | 北京理工大学 | Weak correlation multiport parallel store controller |
Non-Patent Citations (1)
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