CN104865756B - Array base palte, display panel and display device - Google Patents
Array base palte, display panel and display device Download PDFInfo
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- CN104865756B CN104865756B CN201510152790.XA CN201510152790A CN104865756B CN 104865756 B CN104865756 B CN 104865756B CN 201510152790 A CN201510152790 A CN 201510152790A CN 104865756 B CN104865756 B CN 104865756B
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- 239000000758 substrate Substances 0.000 claims abstract description 103
- 238000000926 separation method Methods 0.000 claims abstract description 48
- 230000004888 barrier function Effects 0.000 claims description 68
- 239000004020 conductor Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- WABPQHHGFIMREM-AHCXROLUSA-N lead-203 Chemical compound [203Pb] WABPQHHGFIMREM-AHCXROLUSA-N 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Human Computer Interaction (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a kind of array base palte, display panel and display device, including viewing area and the non-display area around viewing area, non-display area includes a plurality of first electrode lead and a plurality of second electrode lead, and the non-display area of array base palte includes：Substrate；It is arranged at the first conductive layer of substrate surface；It is arranged at the gate dielectric layer that the first conductive layer deviates from substrate side；It is arranged at the second conductive layer that gate dielectric layer deviates from substrate side；The dielectric constant for being arranged at the separation layer that the second conductive layer deviates from substrate side, thickness of the thickness more than gate dielectric layer of separation layer, and/or separation layer is less than the dielectric constant of gate dielectric layer；It is arranged at the 3rd conductive layer that separation layer deviates from substrate side；First electrode lead is arranged at the first conductive layer or the second conductive layer, and second electrode lead is arranged at the 3rd conductive layer, by reasonably connecting up, and greatlys save the wiring domain of array base palte.
Description
Technical field
The present invention relates to touch-control Display Technique neighborhood, more specifically, it is related to a kind of array base palte and including the array
The display panel and display device of substrate.
Background technology
With the development of Display Technique, liquid crystal display panel is continuously available improvement so that liquid crystal display panel has fuselage
Thin, power saving, it is radiationless the advantages of so that the application of liquid crystal display panel is more and more wider.Array base palte is LCD
One of significant components in plate, it has the features such as integrated level is high, cabling is complicated, it is necessary to integrated various in limited wiring domain
Device, therefore, a kind of array base palte for saving wiring domain is one of main research project of researcher now.
The content of the invention
In view of this, the embodiments of the invention provide a kind of array base palte, display panel and display device, by that will apply
Signal has two overlapping contact conductors to be arranged at different conductive layers, and then saves the wiring domain of array base palte, to improve
The utilization rate of array base palte.
To achieve the above object, technical scheme provided in an embodiment of the present invention is as follows：
A kind of array base palte, including viewing area and the non-display area around the viewing area, the non-display area
Domain includes a plurality of first electrode lead and a plurality of second electrode lead, and the non-display area of the array base palte includes：
Substrate；
It is arranged at the first conductive layer of the substrate surface；
It is arranged at the gate dielectric layer that first conductive layer deviates from the substrate side；
It is arranged at the second conductive layer that the gate dielectric layer deviates from the substrate side；
The separation layer that second conductive layer deviates from the substrate side is arranged at, the thickness of the separation layer is more than described
The thickness of gate dielectric layer, and/or the separation layer dielectric constant be less than the gate dielectric layer dielectric constant；
And, it is arranged at the 3rd conductive layer that the separation layer deviates from the substrate side；
Wherein, the first electrode lead is arranged at first conductive layer or second conductive layer, and described second
Contact conductor is arranged at the 3rd conductive layer.
In addition, the embodiment of the present invention additionally provides a kind of display panel, including above-mentioned array base palte.
Finally, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned display panel.
Compared to prior art, at least specific advantages below of technical scheme provided in an embodiment of the present invention：
The embodiments of the invention provide a kind of array base palte, display panel and display device, including viewing area and it surround
The non-display area of the viewing area, the non-display area includes a plurality of first electrode lead and a plurality of second electrode is drawn
Line, the non-display area of the array base palte includes：Substrate；It is arranged at the first conductive layer of the substrate surface；It is arranged at institute
State the gate dielectric layer that the first conductive layer deviates from the substrate side；The gate dielectric layer is arranged at away from the of the substrate side
Two conductive layers；The separation layer that second conductive layer deviates from the substrate side is arranged at, the thickness of the separation layer is more than institute
State the thickness of gate dielectric layer, and/or the dielectric constant of the separation layer is less than the dielectric constant of the gate dielectric layer；And, if
It is placed in the 3rd conductive layer that the separation layer deviates from the substrate side；Wherein, the first electrode lead is arranged at described
One conductive layer or second conductive layer, and the second electrode lead is arranged at the 3rd conductive layer.
As shown in the above, technical scheme provided in an embodiment of the present invention, because the thickness of separation layer is more than gate medium
Layer thickness, and/or separation layer dielectric constant be less than gate dielectric layer dielectric constant so that first electrode lead and second electricity
Pole lead is improved between the first electrode lead and second electrode lead of different conductive layers when being applied simultaneously signal
Interference phenomenon, then by reasonably connecting up, the wiring domain of array base palte can be greatlyd save, and then improve array base
The utilization rate of plate.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is a kind of existing structural representation of array base palte；
A kind of structural representation for array base palte that Fig. 2 provides for the embodiment of the present application；
Fig. 3 a are a kind of sectional drawing in Fig. 2 along aa ' directions；
Fig. 3 b are another sectional drawing in Fig. 2 along aa ' directions；
A kind of first electrode lead and the wiring diagram of second electrode lead that Fig. 4 a provide for the embodiment of the present application；
Another first electrode lead and the wiring diagram of second electrode lead that Fig. 4 b provide for the embodiment of the present application；
The structural representation for another array base palte that Fig. 5 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 6 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 7 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 8 provides for the embodiment of the present application；
The structural representation for another array base palte that Fig. 9 provides for the embodiment of the present application；
The structural representation for another array base palte that Figure 10 provides for the embodiment of the present application；
The structural representation for another array base palte that Figure 11 provides for the embodiment of the present application；
The structural representation for another array base palte that Figure 12 provides for the embodiment of the present application；
A kind of touch-control structure schematic diagram for array base palte that Figure 13 provides for the embodiment of the present application；
Figure 14 a are a kind of sectional drawing in Figure 13 along bb ' directions；
Figure 14 b are another sectional drawing in Figure 13 along bb ' directions.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As described in background, because array base palte has the features such as integrated level is high, cabling is complicated, it is necessary to limited
Integrated various devices in domain are connected up, therefore, a kind of array base palte for saving wiring domain is that researcher mainly studies now
One of project.
Specifically, be a kind of structural representation of existing array base palte with reference to shown in Fig. 1, wherein, array base palte includes
Viewing area 101 and around the viewing area non-display area 102, viewing area 101 include a plurality of gate line 101a and
A plurality of data lines 101b；Non-display area 102 includes gate driving circuit region 102a and stepped area 102b；Gate line 101a
Drawn by the gate line lead 101a ' in the 102a of gate driving circuit region, and data wire 101b passes through positioned at step
Data cable lead wire 101b ' in the 102b of region is drawn, because adjacent data line lead 101b ' needs to apply signal simultaneously, therefore
In order to avoid signal is interfered between adjacent data line lead 101b ', the distance between adjacent data line lead 101b ' is drawn
Greatly, and then the wiring domain of array base palte is increased.
Based on this, the embodiment of the present application provides a kind of array base palte, has overlapping two by will be applied in signal time slot
Individual contact conductor is arranged at different conductive layers, and by reasonable line arrangement, to save the wiring domain of array base palte, improves array base
The utilization rate of plate.Specifically with reference to shown in Fig. 2 to Figure 14 b, the array base palte that the embodiment of the present application is provided is described in detail.
With reference to shown in Fig. 2, Fig. 3 a and Fig. 3 b, a kind of structural representation for array base palte that Fig. 2 provides for the embodiment of the present application
Figure, Fig. 3 a are a kind of sectional drawing in Fig. 2 along aa ' directions, and Fig. 3 b are another sectional drawing in Fig. 2 along aa ' directions, wherein,
Array base palte includes：
Viewing area 10；
And around viewing area 10 non-display area 20, non-display area 20 include a plurality of first electrode lead 20a and
A plurality of second electrode lead 20b, and first electrode lead 20a and second electrode lead 20b be applied in period of signal and have overlapping,
The non-display area of array base palte includes：
Substrate 100；
It is arranged at first conductive layer 200 on the surface of substrate 100；
It is arranged at the gate dielectric layer 300 that the first conductive layer 200 deviates from the side of substrate 100；
It is arranged at the second conductive layer 400 that gate dielectric layer 300 deviates from the side of substrate 100；
The separation layer 500 that the second conductive layer 400 deviates from the side of substrate 100 is arranged at, the thickness of separation layer is more than gate medium
Layer thickness, and/or separation layer dielectric constant be less than gate dielectric layer dielectric constant；
And, it is arranged at the 3rd conductive layer 600 that separation layer 500 deviates from the side of substrate 100；
Wherein, first electrode lead 20a is arranged at the first conductive layer 200 or the second conductive layer 400, and second electrode lead
20b is arranged at the 3rd conductive layer 600.
That is, with reference to shown in Fig. 3 a, first electrode lead 20a is arranged at the first conductive layer 200, and second electrode lead 20b
It is arranged at the 3rd conductive layer 600；
And, with reference to shown in Fig. 3 b, first electrode lead 20a is arranged at the second conductive layer 400, and second electrode lead
20b is arranged at the 3rd conductive layer 600.
It should be noted that the thickness of separation layer described above be more than gate dielectric layer thickness, and/or separation layer Jie
Electric constant is less than in the dielectric constant of gate dielectric layer, including three kinds of situations, i.e. the first is more than gate medium for the thickness of separation layer
The thickness of layer, and dielectric constant of the dielectric constant less than gate dielectric layer of separation layer；Second is in gate dielectric layer and separation layer
Thickness it is identical when, the dielectric constant of separation layer is less than the dielectric constant of gate dielectric layer；And, the third is Jie in separation layer
When electric constant is identical with the dielectric constant of gate dielectric layer, the thickness of separation layer is more than the thickness of gate dielectric layer.The embodiment of the present application
It is preferred that separation layer thickness be not less than 1.8 microns.
The first electrode lead and second electrode lead provided for the embodiment of the present application can arbitrarily be set, preferably
, along the printing opacity direction of array base palte, there is overlapping region between first electrode lead and second electrode lead.Specifically, ginseng
Examine shown in Fig. 4 a, a kind of first electrode lead and the wiring diagram of second electrode lead provided for the embodiment of the present application, wherein, the
There is overlapping region between one contact conductor 20a and second electrode lead 20b, and first electrode lead 20a and second electrode are drawn
Line 20b bearing of trend is identical.I.e. along the bearing of trend of any one contact conductor, a contact conductor being capable of another electricity of covering part
Pole lead；Or, along the bearing of trend of any one contact conductor, a contact conductor can all cover another contact conductor；
In addition, with reference to shown in Fig. 4 b, another first electrode lead and second electrode provided for the embodiment of the present application draws
The wiring diagram of line, wherein, there is overlapping region between first electrode lead 20a and second electrode lead 20b, and first electrode is drawn
There is angle between line 20a and second electrode lead 20b bearing of trend, wherein, angle can be 45 degree, any degree such as 60 degree
Number, is not restricted to this.
It should be noted that the embodiment of the present application is for the wire structures between first electrode lead and second electrode lead
It is not specifically limited, it is necessary to be designed according to actual application, and then by reasonable line arrangement, to reduce the wiring of array base palte
Domain.In addition, in order to keep first electrode lead and second electrode lead to transmit the uniformity of signal, the embodiment of the present application is provided
First electrode lead it is identical with the resistance of second electrode lead.
Further, with reference to shown in Fig. 5, the structural representation of another array base palte provided for the embodiment of the present application,
Wherein, non-display area 20 includes gate driving circuit region 21 and stepped area 22, wherein,
Positioned at gate driving circuit region 21 include a plurality of gate line lead 21a, each gate line 21a lead respectively with
One gate line 10a of array base palte is connected；
And positioned at stepped area 22 include a plurality of data lines lead 22a, each data line lead 22a respectively with array base
One data wire 10b of plate is connected；
Wherein, first electrode lead 20a and second electrode lead 20b is gate line lead or data cable lead wire.
The array base palte provided for the embodiment of the present application, the application is not specifically limited to its type, wherein, for battle array
The transistor of row substrate can be bottom-gate-type transistor, or top gate-type transistors, specifically withs reference to Fig. 6 and Fig. 7 shown in, to
The array base palte that application embodiment is provided is described in detail, it is necessary to illustrate, Fig. 6 and Fig. 7 are with based on Fig. 3 a or Fig. 3 b
Illustrated exemplified by the array base palte of offer.
Wherein, the transistor of array base palte can be bottom-gate-type transistor, be that the embodiment of the present application is carried with reference to shown in Fig. 6
The structural representation of another array base palte supplied, wherein, the first conductive layer 200 of array base palte includes grid G, and second is conductive
Layer 400 includes source-drain electrode (wherein, including source S and drain D), and array base palte includes：
The semiconductor layer 700 between the conductive layer 400 of gate dielectric layer 300 and second is arranged at, semiconductor layer 700 includes active
Area A, wherein, grid G, source-drain electrode (source S and drain D) and active area A formation thin film transistor (TFT)s.
Or, the transistor of array base palte can be top gate-type transistors, be that the embodiment of the present application is carried with reference to shown in Fig. 7
The structural representation of another array base palte supplied, wherein, the first conductive layer 200 of array base palte includes grid G, and second is conductive
Layer 400 includes source-drain electrode (wherein, including source S and drain D), and array base palte includes：
The semiconductor layer 700 between the conductive layer 200 of substrate 100 and first is arranged at, semiconductor layer 700 includes active area A；
And, the gate insulation layer 301 between the conductive layer 200 of semiconductor layer 700 and first is arranged at, wherein, grid G, source-drain electrode (its
In, including source S and drain D) and active area A formation thin film transistor (TFT)s.
In addition, the application is equally not specifically limited for the public electrode of array base palte and the position of pixel electrode, tool
Shown in body combination Fig. 8 to Figure 12, the array base palte that the embodiment of the present application is provided is described in detail.
With reference to shown in Fig. 8, the structural representation of another array base palte provided for the embodiment of the present application, wherein,
Array base palte includes：Substrate 100, the first conductive layer 200, gate dielectric layer 300, the second conductive layer 400；
It is arranged at the first insulating barrier 801 that the second conductive layer 400 deviates from the side of substrate 100；
It is arranged at the first electrode 802 that the first insulating barrier 801 deviates from the side of substrate 100；
It is arranged at the second insulating barrier 803 that first electrode 802 deviates from the side of substrate 100；
It is arranged at the second electrode 804 that the second insulating barrier 803 deviates from the side of substrate 100；
It is arranged at the 3rd insulating barrier 805 that second electrode 804 deviates from the side of substrate 100；
And, it is arranged at the 3rd conductive layer 600 that the 3rd insulating barrier 805 deviates from the side of substrate 100；
Wherein, separation layer includes the first insulating barrier, the second insulating barrier and the 3rd insulating barrier.
Or, with reference to shown in Fig. 9, the structural representation of another array base palte provided for the embodiment of the present application, wherein,
Array base palte includes：Substrate 100, the first conductive layer 200, gate dielectric layer 300, the second conductive layer 400；
It is arranged at the first insulating barrier 801 that the second conductive layer 400 deviates from the side of substrate 100；
It is arranged at the first electrode 802 that the first insulating barrier 801 deviates from the side of substrate 100；
It is arranged at the second insulating barrier 803 that first electrode 802 deviates from the side of substrate 100；
It is arranged at the 3rd conductive layer 600 that the second insulating barrier 803 deviates from the side of substrate 100；
It is arranged at the 3rd insulating barrier 805 that the 3rd conductive layer 600 deviates from the side of substrate 100；
And, it is arranged at the second electrode 804 that the 3rd insulating barrier 805 deviates from the side of substrate 100；
Wherein, separation layer includes the first insulating barrier and the second insulating barrier.
Or, with reference to shown in Figure 10, the structural representation of another array base palte provided for the embodiment of the present application, its
In, array base palte includes：Substrate 100, the first conductive layer 200, gate dielectric layer 300, the second conductive layer 400；
It is arranged at the first insulating barrier 801 that the second conductive layer 400 deviates from the side of substrate 100；
It is arranged at the 3rd conductive layer 600 that the first insulating barrier 801 deviates from the side of substrate 100；
It is arranged at the second insulating barrier 803 that the 3rd conductive layer 600 deviates from the side of substrate 100；
It is arranged at the first electrode 802 that the second insulating barrier 803 deviates from the side of substrate 100；
It is arranged at the 3rd insulating barrier 805 that first electrode 802 deviates from the side of substrate 100；
And, it is arranged at the second electrode 804 that the 3rd insulating barrier 805 deviates from the side of substrate 100；
Wherein, separation layer includes the first insulating barrier.
Or, with reference to shown in Figure 11, the structural representation of another array base palte provided for the embodiment of the present application, its
In, array base palte includes：Substrate 100, the first conductive layer 200, gate dielectric layer 300, the second conductive layer 400；
It is arranged at the first insulating barrier 801 that the second conductive layer 400 deviates from the side of substrate 100；
The driving electrodes 806 that the first insulating barrier 801 deviates from the side of substrate 100 are arranged at, driving electrodes 806 include the first electricity
Pole and second electrode；
It is arranged at the second insulating barrier 803 that driving electrodes 802 deviate from the side of substrate 100；
And, it is arranged at the 3rd conductive layer 600 that driving electrodes 803 deviate from the side of substrate 100；
Wherein, separation layer includes the first insulating barrier and the second insulating barrier.
Or, with reference to shown in Figure 12, the structural representation of another array base palte provided for the embodiment of the present application, its
In, array base palte includes：Substrate 100, the first conductive layer 200, gate dielectric layer 300, the second conductive layer 400；
It is arranged at the first insulating barrier 801 that the second conductive layer 400 deviates from the side of substrate 100；
It is arranged at the 3rd conductive layer 600 that the first insulating barrier 801 deviates from the side of substrate 100；
It is arranged at the second insulating barrier 803 that the 3rd conductive layer 600 deviates from the side of substrate 100；
And, the driving electrodes 806 that the second insulating barrier 803 deviates from the side of substrate 100 are arranged at, driving electrodes 806 include
First electrode and second electrode；
Wherein, separation layer includes the first insulating barrier.
In the above, the embodiment of the present application can set first electrode to be public electrode, and second electrode is pixel electricity
Pole；Or, first electrode is pixel electrode, and second electrode is public electrode.
Further, the array base palte that the embodiment of the present application is provided can be self-capacitance touch-control array base palte, with reference to Figure 13
It is shown, a kind of touch-control structure schematic diagram of the array base palte provided for the embodiment of the present application, wherein, the public electrode of array base palte
It is divided into multiple separate touch control electrodes 201；
The a plurality of touch-control line 202 of viewing area 10 is arranged at, each touch-control line 202 is electrical with a touch control electrode 201 respectively
Connection；
Wherein, touch control electrode 201 is applied in common electric voltage in the display stage, and touch control electrode be applied in the touch-control stage it is tactile
Control detection signal；
Wherein, touch-control line 202 is arranged at the 3rd conductive layer.
Optionally, positioned at non-display area 20, including：A plurality of touch-control line lead 203, each touch-control line lead 203 is distinguished
It is connected with a touch-control line 202；
Wherein, it is a kind of sectional drawing along bb ' directions in Figure 13 with reference to shown in Figure 14 a, wherein, based on Fig. 3 a to Figure 14 a
Illustrate, when first electrode lead 20a is arranged at the first conductive layer 200, touch-control line lead 203 is arranged at the second conductive layer
400, and touch-control line lead is electrically connected with touch-control line using via mode；
Or, it is another sectional drawing along bb ' directions in Figure 13 with reference to shown in Figure 14 b, wherein, based on Fig. 3 b to figure
14b is illustrated, and when first electrode lead 20a is arranged at the second conductive layer 400, touch-control line lead 203 is arranged at first and led
Electric layer 200, and touch-control line lead 203 is electrically connected with touch-control line using via mode.Wherein, above-mentioned first electrode lead,
Second electrode lead and touch control electrode lead can be overlapped, and saved lead area occupied, improved the utilization rate of array base palte.
In addition, the embodiment of the present application additionally provides a kind of display panel, including the array that above-mentioned any one embodiment is provided
Substrate.
Finally, the embodiment of the present application additionally provides a kind of display device, including the display panel that above-described embodiment is provided.
The embodiment of the present application provide a kind of array base palte, display panel and display device, including viewing area and surround
The non-display area of the viewing area, the non-display area includes a plurality of first electrode lead and a plurality of second electrode is drawn
Line, and the first electrode lead and second electrode lead be applied in period of signal and have overlapping, the array base palte it is non-aobvious
Show that region includes：Substrate；It is arranged at the first conductive layer of the substrate surface；First conductive layer is arranged at away from the base
The gate dielectric layer of plate side；It is arranged at the second conductive layer that the gate dielectric layer deviates from the substrate side；It is arranged at described
Two conductive layers deviate from the separation layer of the substrate side, and the thickness of the separation layer is more than the thickness of the gate dielectric layer, and/or
The dielectric constant of the separation layer is less than the dielectric constant of the gate dielectric layer；And, the separation layer is arranged at away from described
3rd conductive layer of substrate side；Wherein, the first electrode lead is arranged at first conductive layer or second conduction
Layer, and the second electrode lead is arranged at the 3rd conductive layer.
As shown in the above, the technical scheme that the embodiment of the present application is provided, because the thickness of separation layer is more than gate medium
Layer thickness, and/or separation layer dielectric constant be less than gate dielectric layer dielectric constant so that first electrode lead and second electricity
Pole lead is improved between the first electrode lead and second electrode lead of different conductive layers when being applied simultaneously signal
Interference phenomenon, then by reasonably connecting up, the wiring domain of array base palte can be greatlyd save, and then improve array base
The utilization rate of plate.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (19)
1. a kind of array base palte, including viewing area and the non-display area around the viewing area, the non-display area
Including a plurality of first electrode lead and a plurality of second electrode lead, it is characterised in that the non-display area bag of the array base palte
Include：
Substrate；
It is arranged at the first conductive layer of the substrate surface；
It is arranged at the gate dielectric layer that first conductive layer deviates from the substrate side；
It is arranged at the second conductive layer that the gate dielectric layer deviates from the substrate side；
The separation layer that second conductive layer deviates from the substrate side is arranged at, the thickness of the separation layer is situated between more than the grid
Matter layer thickness, and/or the separation layer dielectric constant be less than the gate dielectric layer dielectric constant；
And, it is arranged at the 3rd conductive layer that the separation layer deviates from the substrate side；
Wherein, the first electrode lead is arranged at first conductive layer or second conductive layer, and the second electrode
Lead is arranged at the 3rd conductive layer.
2. array base palte according to claim 1, it is characterised in that along the printing opacity direction of the array base palte, described
There is overlapping region between one contact conductor and second electrode lead.
3. array base palte according to claim 2, it is characterised in that the first electrode lead and second electrode lead
Bearing of trend is identical.
4. array base palte according to claim 2, it is characterised in that the first electrode lead and second electrode lead
There is angle between bearing of trend.
5. array base palte according to claim 1, it is characterised in that the first electrode lead and second electrode lead
Resistance is identical.
6. array base palte according to claim 1, it is characterised in that the non-display area includes gate driving circuit area
Domain and stepped area, wherein,
Positioned at the gate driving circuit region include a plurality of gate line lead, each gate line lead respectively with the array
One gate line of substrate is connected；
And positioned at the stepped area include a plurality of data lines lead, each data line lead respectively with the array base palte
One data wire is connected；
Wherein, the first electrode lead and second electrode lead are gate line lead or data cable lead wire.
7. array base palte according to claim 1, it is characterised in that the thickness of the separation layer is not less than 1.8 microns.
8. array base palte according to claim 1, it is characterised in that first conductive layer includes grid, described second
Conductive layer includes source-drain electrode, and the array base palte includes：
The semiconductor layer between the gate dielectric layer and second conductive layer is arranged at, the semiconductor layer includes active area,
Wherein, the grid, source-drain electrode and active area formation thin film transistor (TFT).
9. array base palte according to claim 1, it is characterised in that first conductive layer includes grid, described second
Conductive layer includes source-drain electrode, and the array base palte includes：
The semiconductor layer between the substrate and first conductive layer is arranged at, the semiconductor layer includes active area；And,
It is arranged at the gate insulation layer between the semiconductor layer and first conductive layer.
10. array base palte according to claim 1, it is characterised in that the array base palte includes：The substrate, first
Conductive layer, gate dielectric layer, the second conductive layer；
It is arranged at the first insulating barrier that second conductive layer deviates from the substrate side；
It is arranged at the first electrode that first insulating barrier deviates from the substrate side；
It is arranged at the second insulating barrier that the first electrode deviates from the substrate side；
It is arranged at the second electrode that second insulating barrier deviates from the substrate side；
It is arranged at the 3rd insulating barrier that the second electrode deviates from the substrate side；
And, it is arranged at the 3rd conductive layer that the 3rd insulating barrier deviates from the substrate side；
Wherein, the separation layer includes first insulating barrier, the second insulating barrier and the 3rd insulating barrier.
11. array base palte according to claim 1, it is characterised in that the array base palte includes：The substrate, first
Conductive layer, gate dielectric layer, the second conductive layer；
It is arranged at the first insulating barrier that second conductive layer deviates from the substrate side；
It is arranged at the first electrode that first insulating barrier deviates from the substrate side；
It is arranged at the second insulating barrier that the first electrode deviates from the substrate side；
It is arranged at the 3rd conductive layer that second insulating barrier deviates from the substrate side；
It is arranged at the 3rd insulating barrier that the 3rd conductive layer deviates from the substrate side；
And, it is arranged at the second electrode that the 3rd insulating barrier deviates from the substrate side；
Wherein, the separation layer includes first insulating barrier and the second insulating barrier.
12. array base palte according to claim 1, it is characterised in that the array base palte includes：The substrate, first
Conductive layer, gate dielectric layer, the second conductive layer；
It is arranged at the first insulating barrier that second conductive layer deviates from the substrate side；
It is arranged at the 3rd conductive layer that first insulating barrier deviates from the substrate side；
It is arranged at the second insulating barrier that the 3rd conductive layer deviates from the substrate side；
It is arranged at the first electrode that second insulating barrier deviates from the substrate side；
It is arranged at the 3rd insulating barrier that the first electrode deviates from the substrate side；
And, it is arranged at the second electrode that the 3rd insulating barrier deviates from the substrate side；
Wherein, the separation layer includes first insulating barrier.
13. array base palte according to claim 1, it is characterised in that the array base palte includes：The substrate, first
Conductive layer, gate dielectric layer, the second conductive layer；
It is arranged at the first insulating barrier that second conductive layer deviates from the substrate side；
Be arranged at first insulating barrier deviate from the substrate side driving electrodes, the driving electrodes include first electrode and
Second electrode；
It is arranged at the second insulating barrier that the driving electrodes deviate from the substrate side；
And, it is arranged at the 3rd conductive layer that the driving electrodes deviate from the substrate side；
Wherein, the separation layer includes first insulating barrier and the second insulating barrier.
14. array base palte according to claim 1, it is characterised in that the array base palte includes：The substrate, first
Conductive layer, gate dielectric layer, the second conductive layer；
It is arranged at the first insulating barrier that second conductive layer deviates from the substrate side；
It is arranged at the 3rd conductive layer that first insulating barrier deviates from the substrate side；
It is arranged at the second insulating barrier that the 3rd conductive layer deviates from the substrate side；
And, the driving electrodes that second insulating barrier deviates from the substrate side are arranged at, the driving electrodes include first
Electrode and second electrode；
Wherein, the separation layer includes first insulating barrier.
15. the array base palte according to claim 10~14 any one, it is characterised in that the first electrode is public
Electrode, the second electrode is pixel electrode；
Or, the first electrode is pixel electrode, and the second electrode is public electrode.
16. array base palte according to claim 15, it is characterised in that the public electrode is divided into multiple mutually only
Vertical touch control electrode；
The a plurality of touch-control line of the viewing area is arranged at, each touch-control line is electrically connected with a touch control electrode respectively；
Wherein, the touch control electrode is applied in common electric voltage in the display stage, and the touch control electrode is applied in the touch-control stage
Touch control detection signal；
Wherein, the touch-control line is arranged at the 3rd conductive layer.
17. array base palte according to claim 16, it is characterised in that positioned at the non-display area, including：It is a plurality of to touch
Line lead is controlled, each touch-control line lead is connected with a touch-control line respectively；
Wherein, when the first electrode lead is arranged at first conductive layer, the touch-control line lead is arranged at described
Two conductive layers, and the touch-control line lead is electrically connected with the touch-control line using via mode；
Or, when the first electrode lead is arranged at second conductive layer, the touch-control line lead is arranged at described
One conductive layer, and the touch-control line lead is electrically connected with the touch-control line using via mode.
18. a kind of display panel, it is characterised in that including the array base palte described in claim 1~17 any one.
19. a kind of display device, it is characterised in that including the display panel described in claim 18.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710804399.2A CN107340623B (en) | 2015-04-01 | 2015-04-01 | Array substrate, display panel and display device |
| CN201710804398.8A CN107490913B (en) | 2015-04-01 | 2015-04-01 | Array substrate, display panel and display device |
| CN201510152790.XA CN104865756B (en) | 2015-04-01 | 2015-04-01 | Array base palte, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510152790.XA CN104865756B (en) | 2015-04-01 | 2015-04-01 | Array base palte, display panel and display device |
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| CN201710804398.8A Division CN107490913B (en) | 2015-04-01 | 2015-04-01 | Array substrate, display panel and display device |
| CN201710804399.2A Division CN107340623B (en) | 2015-04-01 | 2015-04-01 | Array substrate, display panel and display device |
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| Publication Number | Publication Date |
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| CN104865756A CN104865756A (en) | 2015-08-26 |
| CN104865756B true CN104865756B (en) | 2017-08-25 |
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| CN201710804398.8A Active CN107490913B (en) | 2015-04-01 | 2015-04-01 | Array substrate, display panel and display device |
| CN201510152790.XA Active CN104865756B (en) | 2015-04-01 | 2015-04-01 | Array base palte, display panel and display device |
| CN201710804399.2A Active CN107340623B (en) | 2015-04-01 | 2015-04-01 | Array substrate, display panel and display device |
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|---|---|---|---|---|
| CN105389058B (en) | 2015-12-07 | 2018-11-06 | 上海中航光电子有限公司 | A kind of integrated touch-control display panel and integrated touch control display apparatus |
| CN105427748B (en) * | 2016-01-04 | 2018-10-09 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel, display device and display methods |
| CN105743451B (en) * | 2016-02-03 | 2018-11-06 | 宜确半导体（苏州）有限公司 | A kind of radio-frequency power amplifier domain and radio-frequency power amplifier |
| CN105808027A (en) * | 2016-03-11 | 2016-07-27 | 惠州Tcl移动通信有限公司 | Touch screen sensing structure, touch screen and narrow-bezel electronic display device |
| CN108080041B (en) * | 2016-11-21 | 2023-10-20 | 胡丛余 | Micro fluid actuator |
| CN106547127B (en) * | 2017-01-16 | 2019-10-25 | 上海天马微电子有限公司 | Array substrate, liquid crystal display panel and display device |
| CN106898623B (en) * | 2017-04-19 | 2020-04-03 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN107219956B (en) * | 2017-06-09 | 2021-01-29 | 京东方科技集团股份有限公司 | Display substrate, driving method thereof and display panel |
| JP2019053117A (en) * | 2017-09-13 | 2019-04-04 | シャープ株式会社 | Display device with position input function |
| CN108446053B (en) * | 2018-03-27 | 2021-03-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN108732837B (en) * | 2018-05-29 | 2019-10-18 | 武汉华星光电技术有限公司 | Tft array substrate and liquid crystal display panel |
| US11874575B2 (en) | 2020-08-24 | 2024-01-16 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel having first and second wires extended and arranged in the same direction in the bezel region |
| CN211577626U (en) * | 2020-08-24 | 2020-09-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG136795A1 (en) * | 2000-09-14 | 2007-11-29 | Semiconductor Energy Lab | Semiconductor device and manufacturing method thereof |
| KR101061853B1 (en) * | 2003-08-29 | 2011-09-02 | 삼성전자주식회사 | Display device and its display board |
| TW200638111A (en) * | 2005-04-19 | 2006-11-01 | Prime View Int Co Ltd | Active-matrix display panel |
| CN100405197C (en) * | 2005-08-05 | 2008-07-23 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus having the same |
| JP5175433B2 (en) * | 2005-09-22 | 2013-04-03 | 京セラ株式会社 | Image display device |
| CN101046590A (en) * | 2006-03-31 | 2007-10-03 | 元太科技工业股份有限公司 | Active matrix type display panel |
| CN101872092B (en) * | 2009-04-24 | 2013-02-13 | 上海天马微电子有限公司 | Liquid crystal display panel |
| CN201611659U (en) * | 2009-11-28 | 2010-10-20 | 深圳华映显示科技有限公司 | Activating element array substrate |
| CN102870220B (en) * | 2010-04-30 | 2014-05-07 | 夏普株式会社 | Circuit board and display device |
| KR101065323B1 (en) * | 2010-05-24 | 2011-09-16 | 삼성모바일디스플레이주식회사 | Liquid crystal display device |
| CN201788340U (en) * | 2010-05-26 | 2011-04-06 | 福州华映视讯有限公司 | Active component array substrate |
| TWI516851B (en) * | 2011-05-05 | 2016-01-11 | 友達光電股份有限公司 | Lead line structure of liquid crystal display panel and liquid crystal display panel having the same |
| WO2013077262A1 (en) * | 2011-11-25 | 2013-05-30 | シャープ株式会社 | Liquid crystal display device |
| TWI465979B (en) * | 2012-04-16 | 2014-12-21 | Au Optronics Corp | Touch panel |
| CN102890380B (en) * | 2012-10-12 | 2014-11-05 | 京东方科技集团股份有限公司 | TFT (thin film transistor) array base plate, manufacture method thereof and liquid crystal display device |
| US9690149B2 (en) * | 2013-09-09 | 2017-06-27 | Sharp Kabushiki Kaisha | Active matrix substrate and display device |
| CN104155818A (en) * | 2014-07-22 | 2014-11-19 | 京东方科技集团股份有限公司 | Array substrate and display panel |
-
2015
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| Publication number | Publication date |
|---|---|
| CN107490913B (en) | 2020-11-13 |
| CN107340623A (en) | 2017-11-10 |
| CN107340623B (en) | 2020-05-22 |
| CN104865756A (en) | 2015-08-26 |
| CN107490913A (en) | 2017-12-19 |
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