CN104750225B - The processing method and processor of processor - Google Patents
The processing method and processor of processor Download PDFInfo
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- CN104750225B CN104750225B CN201310751045.8A CN201310751045A CN104750225B CN 104750225 B CN104750225 B CN 104750225B CN 201310751045 A CN201310751045 A CN 201310751045A CN 104750225 B CN104750225 B CN 104750225B
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Abstract
The present invention provides the processing method of processor and processors.It includes instruction set, receiving module and processing module that the processor, which has one or more kernel, the kernel, and instruction set configures to store the multiple instruction including the first instruction, including：Operational order is received by the receiving module；The instruction in described instruction set is transferred to execute the operational order by the processing module, when in the instruction transferred comprising first instruction, while keeping the core clock to continue to run with, stop the processing operation in the kernel at the appointed time.According to this method, stop the various processing operations of kernel during command interval, only retain clock, the power consumption of processor is effectively reduced while without stopping processor.
Description
Technical field
The present invention relates to the processing method of processor and processors, more particularly to can effectively reduce the processor of power consumption
Processing method and processor.
Background technology
Nowadays, with the rapid development of electronic equipment, the performance of processor is also improving therewith.In addition to single core processor
Outside, also creating double-core, four cores, eight cores etc. has the processor of multiple kernels.This multi-core processor can realize that high speed is transported
It calculates, but power problems become more significantly.For mobile device, how to be dropped in the case of limited battery capacity
Low-power consumption becomes present mainstream project.
As the prior art for solving the above subject, it is known that in the operational process of processor, by for running clearance
The modes of addition nop instructions reduces power consumption, but due to nop instructions itself be also required to take location, decoding, execution process,
Therefore the effect unobvious of power consumption are reduced.In multi-core processor, typically stop not by way of the kernel of task come
Power consumption is reduced, but this control mode needs constantly to retrieve the generation of event, this search operaqtion itself by another kernel
Certain power consumption is needed, ideal energy-saving effect can not be reached.
Invention content
The present invention is completed in view of the above project, it is intended that a kind of processing method and processor of processor are provided,
The various processing operations for stopping kernel during command interval, only retain clock, effective while without stopping processor
Reduce the power consumption of processor.
The embodiment provides a kind of processing method of processor, the processor has in one or more
Core, the kernel include instruction set, receiving module and processing module, and instruction set configuration exists to store including the first instruction
Interior multiple instruction, including：Operational order is received by the receiving module；The finger is transferred by the processing module
It enables the instruction in set to execute the operational order, when in the instruction transferred comprising first instruction, is keeping
While the core clock continues to run with, stop the processing operation in the kernel at the appointed time.
Preferably, the processing operation includes taking location operation, decoded operation and executing operation.
Preferably, the stipulated time includes multiple clock cycle.
Preferably, first instruction includes timing parameter, and the processing module includes counter, when what is transferred
When in instruction comprising first instruction, while keeping the core clock to continue to run with, existed by the processing module
Stipulated time, the interior processing operation stopped in the kernel included：Described in processing module stopping described in the counter records
The clock number of processing operation；When in the instruction transferred including first instruction and the timing parameter, by described
Processing module stops the processing operation in the kernel；And after the clock number reaches the timing parameter, by described
Processing module restores the processing operation in the kernel.
The embodiments of the present invention also provide a kind of processors, have one or more kernel, wherein the kernel packet
It includes：Instruction set configures to store the multiple instruction including the first instruction；Receiving module configures to receive operational order；
Processing module, configuration transfer the instruction in described instruction set to execute the operational order, when including in the instruction transferred
When first instruction, while keeping the core clock to continue to run with, at the appointed time by the processing module
Stop the processing operation in the kernel.
Preferably, the processing operation includes taking location operation, decoded operation and executing operation.
Preferably, the stipulated time includes multiple clock cycle.
Preferably described first instruction includes timing parameter, and the processing module includes counter, is configured to record
The clock number that processing module stops the processing operation being stated, when instructing comprising described first in the instruction transferred and being described
When clock parameter, the processing module stops the processing operation in the kernel, after the clock number reaches the timing parameter,
The processing module restores the processing operation in the kernel.
The processing method and processor of processor according to the present invention can stop kernel during command interval
Various processing operations, only retain clock, and the power consumption of processor is effectively reduced while without stopping processor.
Description of the drawings
Fig. 1 is the flow chart of the processing method of the processor of one embodiment of the present of invention.
Fig. 2 is the flow chart of the processing method of the processor of an alternative embodiment of the invention.
Fig. 3 is the functional block diagram of the kernel of the processor of one embodiment of the present of invention.
Specific implementation mode
To make those skilled in the art more fully understand technical scheme of the present invention, this is described in detail below in conjunction with the accompanying drawings
The processing method of the processor of invention and the embodiment of processor.It is noted that based on the embodiments of the present invention, this field
The every other embodiment that those of ordinary skill is obtained without creative efforts, belongs to protection of the present invention
Range.
【The processing method of processor】
In the following, illustrating the embodiment of the processing method of the processor of the present invention in conjunction with Fig. 1 and Fig. 2.
Processor using the processing method of the present invention can be the processor for including one or more kernel.Wherein,
Kernel includes instruction set, receiving module and processing module.Multiple instruction is stored in instruction set.It should be noted that
In the method, instruction set further includes waiting for instruction（First instruction）, which to stop the kernel at the appointed time
Itself（Execute the kernel of waiting instruction）Processing operation.
Receiving module is used to receive operational order from application program etc., and the operational order is sent to processing module.
After processing module receives operational order, instruction corresponding with the operational order in above-metioned instruction set is transferred, and
By executing the instruction, desired processing is realized.
In the following, carrying out the action for the processing method that the present invention will be described in detail in conjunction with Fig. 1.Fig. 1 is one embodiment of the present of invention
Processor processing method flow chart.As shown in Figure 1, first, when an application program is performed and sending out certain operation
When order, the receiving module in kernel receives the operational order（Step S11）.Then, the operational order that receiving module is received
It is sent to the processing module of kernel, which transfers corresponding with the operational order in instruction set instruct（Step
S12）.At this point, judging in transferred instruction whether to include equal Wait Orders（Step 13）, when not comprising equal Wait Orders（Step
S13, it is no）Tenth skill.When comprising equal Wait Orders（Step S13 is）, at the appointed time（Such as in 100 clock cycle
It is interior）Stop the processing operation of the kernel.The processing operation of kernel may include that location is taken to operate, and decoded operation and execute operation,
But the clock in kernel is still in the state continued to run with.
By the above method, it can spontaneously stop the processing operation in kernel, that is, stop during command interval
The various processing operations of kernel, only retain clock, therefore compared with prior art, can more efficiently reduce power consumption.
Next, carrying out the action of the processing method for another embodiment that the present invention will be described in detail in conjunction with Fig. 2.In this implementation
In example, processing module further includes counter, stops the clock number of processing operation for record processing module.Fig. 2 is of the invention
The flow chart of the processing method of the processor of another embodiment.Wherein, step S21 to step S23 and above-mentioned first implementation
Step S11 in example is identical to step S13, therefore the description thereof will be omitted.But it includes timing parameter in the present embodiment, to wait for instruction
（For example, 100）, the clock number for the specified processing operation for stopping kernel.When not comprising equal Wait Orders（Step S23, it is no）
Tenth skill.When comprising equal Wait Orders（Step S23 is）, stop one clock of processing operation of the kernel, while increasing
One counting of counter（Step S24）.Wherein, the processing operation of the kernel of stopping may include that location is taken to operate, decoded operation
And operation is executed, but the clock in kernel is still in the state continued to run with.Then, judge in counter be incremented by after when
Whether clock number has reached timing parameter（Step S25）, when clock number is equal to timing parameter（Step S25 is）, illustrate after being incremented by
Clock number had reached timing parameter, that is, stopped the processing operation of 100 clocks, therefore tenth skill.At that time
When clock number is not equal to timing parameter（Step S25, it is no）, illustrate that timing parameter has not yet been reached in the clock number after being incremented by, therefore move to
Step S24 continues the processing operation for stopping kernel.
By the above method, the clock number for stopping processing operation capable of being specified, therefore kernel can be controlled for greater flexibility
Processing operation, to efficiently control power consumption.
Multiple embodiments of the processing method of the processor of the present invention are explained above.Wherein, processor of the invention can
To be computer, PDA（Personal digital assistant）, processor in smart mobile phone and other any electronic equipments.Obviously, originally
Field technology personnel without departing from the spirit and scope of the present invention can to above-described embodiment various modification can be adapted or deformation.
The every other embodiment that those of ordinary skill in the art are obtained without creative efforts, belongs to this hair
The range of bright protection.
【Processor】
Carry out the processor that the present invention will be described in detail with reference to Fig. 3.The processor of the present invention can be comprising one or
The processor of multiple kernels.Fig. 3 is the functional block diagram of the kernel of the processor of one embodiment of the present of invention.As shown in figure 3, interior
Core 100 includes instruction set 110, receiving module 120 and processing module 130.Instruction set 110 can be in processor
Register or other storage units, are stored with multiple instruction.It should be noted that the kernel 100 of the processor in the present invention
In, instruction set 110 further includes waiting for instruction（First instruction）, which to stop the kernel itself at the appointed time
（Execute the kernel of waiting instruction）Processing operation.
Receiving module 120 receives operational order from application program etc., and the operational order is sent to processing module
130。
After processing module 130 receives operational order, finger corresponding with the operational order in above-metioned instruction set 110 is transferred
It enables, and by executing the instruction, realizes desired processing.
Next, a kind of action for the processor that the present invention will be described in detail.First, when an application program sends out certain behaviour
When ordering, the receiving module 120 in kernel receives the operational order.Then, the operational order that receiving module is received is sent out
It is sent to the processing module 130 of kernel, which transfers corresponding with the operational order in instruction set 110 instruct.This
When, judge in transferred instruction whether to include equal Wait Orders, tenth skill when not comprising equal Wait Orders.When comprising etc. await orders
When enabling, at the appointed time（Such as in 100 clock cycle）Stop the processing operation of the kernel.The processing operation of kernel 100
It may include that location is taken to operate, decoded operation and execute operation, but the clock in kernel 100 is still in the state continued to run with.
Above-mentioned processor can spontaneously stop the processing operation in kernel 100, i.e., stop during command interval
The various processing operations of kernel, only retain clock, therefore compared with prior art, can more efficiently reduce power consumption.
Next, another action for the processor that the present invention will be described in detail.In the present embodiment, processing module further includes
Counter stops the clock number of processing operation for record processing module.In the present embodiment, it includes timing parameter to wait for instruction
（For example, 100）, the clock number for the specified processing operation for stopping kernel 100.Tenth skill when not comprising equal Wait Orders.
When comprising equal Wait Orders, stop one clock of processing operation of the kernel 100, while a counting of increasing counter.
Wherein, the processing operation of kernel 100 may include that location is taken to operate, and decoded operation and execute operation, but the clock in kernel 100
Still in the state continued to run with.Then, judge in counter be incremented by after clock number whether reached timing parameter, at that time
When clock number is equal to timing parameter, illustrates that the clock number after being incremented by has had reached timing parameter, that is, stopped 100 clocks
Processing operation, therefore tenth skill.When clock number is not equal to timing parameter, when illustrating that the clock number after being incremented by has not yet been reached
Clock parameter, therefore the step of repeating to stop one clock of processing operation of the kernel 100.
Above-mentioned processor can specify the periodicity for stopping processing operation, therefore can control the place of kernel for greater flexibility
Reason, to efficiently control power consumption.
Multiple embodiments of the processor of the present invention are explained above.In the present embodiment, receiving module and place are illustrated
Two kinds of modules for managing module, however, receiving module can also be realized with processing module by same physical unit.The processing of the present invention
Device can be computer, PDA（Personal digital assistant）, processor in smart mobile phone and other any electronic equipments.It is aobvious
So, those skilled in the art without departing from the spirit and scope of the present invention can various modification can be adapted to above-described embodiment or
Deformation.The every other embodiment that those of ordinary skill in the art are obtained without creative efforts, all belongs to
In the scope of protection of the invention.
Claims (6)
1. a kind of processing method of processor, the processor has one or more kernel, and the kernel includes instruction set
Conjunction, receiving module and processing module, instruction set configures to store the multiple instruction including the first instruction, wherein wrapping
It includes：
Operational order is received by the receiving module；
The instruction in described instruction set is transferred to execute the operational order, when the finger transferred by the processing module
When in order comprising first instruction, while keeping the core clock to continue to run with, at the appointed time described in stopping
Processing operation in kernel；
Wherein, the stipulated time includes multiple clock cycle.
2. processing method as described in claim 1, wherein
The processing operation includes taking location operation, decoded operation and executing operation.
3. processing method as claimed in claim 2, wherein
First instruction includes timing parameter, and the processing module includes counter,
When in the instruction transferred comprising first instruction, while keeping the core clock to continue to run with, pass through institute
Stating the processing operation that processing module stops at the appointed time in the kernel includes：
Stop the clock number of the processing operation by processing module described in the counter records；
When in the instruction transferred including first instruction and the timing parameter, passes through the processing module and stop institute
State the processing operation in kernel；And
After the clock number reaches the timing parameter, the processing operation in the kernel is restored by the processing module.
4. a kind of processor has one or more kernel, wherein the kernel includes：
Instruction set configures to store the multiple instruction including the first instruction；
Receiving module configures to receive operational order；
Processing module configures to transfer the instruction in described instruction set to execute the operational order, when in the instruction transferred
Including when first instruction, while keeping the core clock to continue to run with, by the processing module in regulation
The interior processing operation stopped in the kernel；
Wherein, the stipulated time includes multiple clock cycle.
5. processor as claimed in claim 4, wherein
The processing operation includes taking location operation, decoded operation and executing operation.
6. processor as claimed in claim 5, wherein
First instruction includes timing parameter,
The processing module includes counter, is configured to record the clock number that the processing module stops the processing operation,
When in the instruction transferred including first instruction and the timing parameter, the processing module stops in described
Processing operation in core,
After the clock number reaches the timing parameter, the processing module restores the processing operation in the kernel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310751045.8A CN104750225B (en) | 2013-12-31 | The processing method and processor of processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310751045.8A CN104750225B (en) | 2013-12-31 | The processing method and processor of processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104750225A CN104750225A (en) | 2015-07-01 |
| CN104750225B true CN104750225B (en) | 2018-08-31 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103484A (en) * | 2009-12-18 | 2011-06-22 | 英特尔公司 | Instruction for enabling a procesor wait state |
| CN102169475A (en) * | 2010-02-08 | 2011-08-31 | 无锡中星微电子有限公司 | Processor and implementation method |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103484A (en) * | 2009-12-18 | 2011-06-22 | 英特尔公司 | Instruction for enabling a procesor wait state |
| CN102169475A (en) * | 2010-02-08 | 2011-08-31 | 无锡中星微电子有限公司 | Processor and implementation method |
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