CN104716134B - A kind of port ESD structures and its equivalent circuit based on the resistance to positive or negative high voltages of HVNMOS - Google Patents
A kind of port ESD structures and its equivalent circuit based on the resistance to positive or negative high voltages of HVNMOS Download PDFInfo
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- CN104716134B CN104716134B CN201310695611.8A CN201310695611A CN104716134B CN 104716134 B CN104716134 B CN 104716134B CN 201310695611 A CN201310695611 A CN 201310695611A CN 104716134 B CN104716134 B CN 104716134B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 230000015556 catabolic process Effects 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- 108010063955 thrombin receptor peptide (42-47) Proteins 0.000 description 1
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Abstract
The invention discloses a kind of port ESD structures and its equivalent circuit based on the resistance to positive or negative high voltages of HVNMOS, port ESD structures include the first NBL buried layers, the 2nd NBL buried layers, the first N+ active areas, the 2nd N+ active areas, the 3rd N+ active areas, the 4th N+ active areas and the first N traps, the 2nd N traps, the 3rd N traps, the 4th N traps being connected with power supply；Using the first P+ active areas, the 2nd P+ active areas as the first p-well contacted；Using the 3rd P+ active areas, the 4th P+ active areas as the second p-well contacted；Connect GND the 5th P+ active areas.Equivalent circuit includes the first metal-oxide-semiconductor N1 and the second metal-oxide-semiconductor N2；First metal-oxide-semiconductor N1 grid is connected with the second metal-oxide-semiconductor N2 grid, first metal-oxide-semiconductor N1 source electrode is connected with the second metal-oxide-semiconductor N2 source electrode, grid of the first metal-oxide-semiconductor N1 source electrode also with the first metal-oxide-semiconductor N1 is connected, and the first metal-oxide-semiconductor N1 drain electrode is connected to port PAD, the second metal-oxide-semiconductor N2 grounded drain.While the present invention has resistance to positive or negative high voltage characteristic, it can also meet ESD protection requirement.
Description
Technical field
The invention belongs to field of semiconductor technology, more particularly, to a kind of port based on the resistance to positive or negative high voltages of HVNMOS
ESD structures and its equivalent circuit.
Background technology
With the diminution of semiconductor processing dimensions, the gap of device operating voltages and breakdown voltage is less and less, integrates electricity
Electrostatic leakage (ESD) problem on road is more and more significant.The operating voltage of IC ports is between 0V and supply voltage under normal circumstances,
ESD device does not have leakage current when only needing to ensure that port voltage is between 0V and supply voltage so as to the ESD structures of port yet.And
Occur that port voltage is higher than supply voltage or the negative pressure less than zero potential, ESD structures now in some interface chips
The positive or negative high voltage of port will be ensured to bear, while meet ESD class requirements.But the main pin of design of current ESD protection
To high voltage bearing requirement, design to resistance to positive/negative-pressure ability substantially without reference to.There is no resistance to positive or negative high voltage port ESD protection, connect
It is difficult to meet ESD protection requirement that mouth chip is when system is applied.
The content of the invention
For the disadvantages described above or Improvement requirement of prior art, the invention provides one kind to be based on the resistance to positive or negative high voltages of HVNMOS
Port ESD devices, its object is to signal port ESD structures are had while resistance to positive or negative high voltage characteristic also to meet
ESD protection design requirement, thus solve in the prior art without the technical problem of resistance to positive or negative high voltage port ESD protection.
The invention provides a kind of port ESD structures based on the resistance to positive or negative high voltages of HVNMOS, including the first NBL buried layers,
2nd NBL buried layers, the first N+ active areas, the 2nd N+ active areas, the 3rd N+ active areas, the 4th N+ active areas being connected with power supply
With the first N traps, the 2nd N traps, the 3rd N traps, the 4th N traps；Using the first P+ active areas, the 2nd P+ active areas as the first p-well contacted；
Using the 3rd P+ active areas, the 4th P+ active areas as the second p-well contacted；Connect GND the 5th P+ active areas；Using when, the 5th N+
Active area is connect together with port PAD, grid oxygen and active area be connected to grid oxygen and active area, N+ active areas ground connection.
Present invention also offers a kind of equivalent circuit based on above-mentioned port ESD structures, including：First metal-oxide-semiconductor N1 and
Second metal-oxide-semiconductor N2；The grid of the first metal-oxide-semiconductor N1 is connected with the grid of the second metal-oxide-semiconductor N2, the first metal-oxide-semiconductor N1
Source electrode be connected with the source electrode of the second metal-oxide-semiconductor N2, the source electrode of the first metal-oxide-semiconductor N1 is also with the first metal-oxide-semiconductor N1's
Grid connects, and the drain electrode of the first metal-oxide-semiconductor N1 is connected to port PAD, the grounded drain of the second metal-oxide-semiconductor N2.
Wherein, it is drain electrode by grid oxygen and N-type region domain, using N+ active areas as source electrode, using the first p-well, PBASE areas as substrate structure
Into the first HVNMOS structures；It is drain electrode by grid oxygen and N-type region domain, N+ active areas be source electrode, and p-well, PBASE areas are substrate composition the
Two HVNMOS structures.
Wherein, when port PAD meets ESD forward direction trigger conditions to the voltage between GND, when port voltage reaches p-well
The breakdown voltage of diode between N- diffusion regions, diode is breakdown between the first metal-oxide-semiconductor N1 drain terminal and p-well, drain terminal, lining
The triode ON that bottom and source are formed is released ESD electric currents, is arrived by the substrate and drain terminal diode of positively biased in the second metal-oxide-semiconductor N2
GND；When port PAD meets ESD negative sense trigger conditions to the voltage between GND, when port voltage absolute value be more than p-well with
Between N- diffusion regions during diode breakdown voltage, diode is breakdown between the second metal-oxide-semiconductor N2 drain terminal and p-well, drain terminal, substrate
The triode ON formed with source is released ESD electric currents, passes through the substrate and drain terminal diode of positively biased in the first metal-oxide-semiconductor N1
To port PAD.
While the present invention has resistance to positive or negative high voltage characteristic, it can also meet ESD protection requirement.
Brief description of the drawings
Fig. 1 is the profile for the ESD device that prior art provides.
Fig. 2 is the equivalent circuit schematic for the ESD device that prior art provides.
Fig. 3 is that the cross-section structure for the port ESD devices based on the resistance to positive or negative high voltages of HVNMOS that the present invention implements to provide is illustrated
Figure.
Fig. 4 is that the equivalent circuit of the port ESD devices provided in an embodiment of the present invention based on the resistance to positive or negative high voltages of HVNMOS is former
Reason figure.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below
Conflict can is not formed each other to be mutually combined.
The invention provides a kind of port ESD devices for being based on HVNMOS (High Voltage NMOS) resistance to positive or negative high voltage,
While the device has resistance to positive or negative high voltage characteristic, it can also meet ESD protection design requirement.
Current high pressure port has a variety of ESD structures, and the profile of one of which structure is as shown in figure 1, its equivalent circuit
As shown in Figure 2.The structure includes P type substrate (PSUB) 1, and N-type buried layer 2 connects power supply by N traps 3 and 19, N+ active areas 4 and 18
Composition shading ring, the P+ active areas 5 and 17 of ground connection, p-well 6, PBASE areas 7 and 16, connect the grid oxygen 10 and 14 of power supply, be connected to end
Mouthful N+ active areas 12, N-type drift region NM 11,13, the N- diffusion regions 9 that are lightly doped.In use, the structure can regard as by
The GGNMOS structures that HVNMOS is formed.When port voltage, which is more than 0V, is less than N- diffusion regions 9 and the junction breakdown voltage of p-well 6,
GGNMOS only has minimum leakage current；To GND under ESD forward direction trigger conditions, port voltage reaches N- diffusion regions 9 and P for port
After the junction breakdown voltage of trap 6, the parasitic diode is breakdown, and ESD electric currents, which flow to p-well substrate, improves substrate electric potential, by source
Thus the parasitic NPN triode ON that N- diffusion regions 9, p-well 6 and N+ active areas 8 are formed, ESD electric currents are released to GND；PAD pairs
For GND under ESD negative sense trigger conditions, p-well turns on electric discharge with the diode forward that N- diffusion regions are formed, and ESD electric currents are from port flow
Walk.But if port normal working voltage can be negative pressure, this ESD structures in normal work are will result between GND and PAD
Electric leakage, so as to influence chip normal work.
The present invention can support port working in positive and negative pressure condition, while have good ESD abilities.Its cross-section structure is as schemed
Shown in 3.The structure includes NBL buried layers 2,38, connects the N+ active areas 4,18,21,36 and N traps 3,19,22,37 of power supply, respectively
P-well 6,35 with P+ active areas 5,17 and 23,34 for contact, by grid oxygen 10,14 and N-type region domain 11 (NM), 12 (N+), 13
(NM), 9 (N-) are drain electrode, and N+ active areas 8 and 15 are source electrode, and p-well 6, PBASE areas 7 and 16 are that the HVNMOS that substrate is formed (schemes
N1 in 4), by grid oxygen 27,31 and N-type region domain 28 (NM), 29 (N+), 30 (NM), 26 (N-) to drain, N+ active areas 25 and 32
For source electrode, p-well 35, PBASE areas 24 and 33 are the HVNMOS (i.e. N2 in Fig. 4) that substrate is formed, and connect GND P+ active areas
20.In use, active area 12 connects port, grid oxygen 10,14 and active area 5,8,15,17 and grid oxygen 27,31 and active area 23,
25th, 32,34 it is connected to together, N+ active areas 29 are grounded.Port to GND under ESD forward direction trigger conditions, when port voltage reaches P
The breakdown voltage of diode between trap and N- diffusion regions, diode is breakdown between N1 drain terminal and p-well in Fig. 4, drain terminal, substrate
The triode ON formed with source is released ESD electric currents, by the substrate and drain terminal diode of positively biased in N2 to GND, avoids ESD
Forward current flows into internal circuit and causes to damage；Port to GND in ESD negative sense trigger conditions, when the absolute value of voltage is less than p-well
Between N- diffusion regions during diode breakdown voltage, the leakage current of the structure is ignored, when voltage absolute value be more than p-well with
Between N- diffusion regions during diode breakdown voltage, diode is breakdown between N2 drain terminal and p-well in Fig. 4, drain terminal, substrate and source
The triode ON that end is formed is released ESD electric currents, by the substrate and drain terminal diode of positively biased in N1 to PAD, avoids ESD negative senses
Electric current flows into internal circuit and causes to damage.I.e. the port normal working voltage of the structural support is tied in negative p-well and N- diffusion regions
Breakdown voltage is between positive p-well and N- diffusion regions junction breakdown voltage, in collocation internal circuit in use, internal components or structure
Breakdown voltage absolute value be greater than p-well and N- diffusion regions junction breakdown voltage, and stay certain surplus.
The present invention is using typical BCDMOS 0.5um technique, port voltage scope -31V~30V of support, ESD energy
Power 4000V.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc., all should be included
Within protection scope of the present invention.
Claims (4)
- A kind of 1. port ESD structures based on the resistance to positive or negative high voltages of HVNMOS, it is characterised in that including the first NBL buried layers (2), 2nd NBL buried layers (38), the first N+ active areas (4), the 2nd N+ active areas (18), the 3rd N+ active areas being connected with power supply (21), the 4th N+ active areas (36) and the first N traps (3), the 2nd N traps (19), the 3rd N traps (22), the 4th N traps (37)；With the first P + active area (5), the first p-well (6) that the 2nd P+ active areas (17) are contact；With the 3rd P+ active areas (23), the 4th P+ active areas (34) it is the second p-well (35) of contact；Connect GND the 5th P+ active areas (20)；Using when, the 5th N+ active areas (12) meet port PAD, the first grid oxygen (10,14) and the first P+ active areas (5), the 8th N+ Active area (8), the 9th N+ active areas (15), the 2nd P+ active areas (17) and the second grid oxygen (27,31) and the 3rd P+ active areas (23), the 6th N+ active areas (25), the 7th N+ active areas (32), the 4th P+ active areas (34) are connected to together, the tenth N+ active areas (29) it is grounded.
- A kind of 2. equivalent circuit of the port ESD structures based on described in claim 1, it is characterised in that including：First metal-oxide-semiconductor N1 and the second metal-oxide-semiconductor N2；The grid of the first metal-oxide-semiconductor N1 is connected with the grid of the second metal-oxide-semiconductor N2, the source electrode of the first metal-oxide-semiconductor N1 with The source electrode connection of the second metal-oxide-semiconductor N2, the grid of the source electrode of the first metal-oxide-semiconductor N1 also with the first metal-oxide-semiconductor N1 are connected, The drain electrode of the first metal-oxide-semiconductor N1 is connected to port PAD, the grounded drain of the second metal-oxide-semiconductor N2.
- 3. equivalent circuit as claimed in claim 2, it is characterised in that by the first grid oxygen (10,14) and the first N-type region domain (11, 12nd, 13 9) it is, drain electrode, with the 8th N+ active areas (8), the 9th N+ active areas (15) for source electrode, with the first p-well (6), first PBASE areas (7), the 2nd PBASE areas (16) are that substrate forms the first HVNMOS structures；By the second grid oxygen (27,31) and the second N-type Region (28,29,30,26) is drain electrode, and the 6th N+ active areas (25), the 7th N+ active areas (32) are source electrode, the second p-well (35), 3rd PBASE areas (24), the 4th PBASE areas (33) are that substrate forms the 2nd HVNMOS structures.
- 4. equivalent circuit as claimed in claim 2 or claim 3, it is characterised in thatWhen port PAD meets ESD forward direction trigger conditions to the voltage between GND, when port voltage reaches p-well and N- diffusion regions Between diode breakdown voltage, diode is breakdown between the first metal-oxide-semiconductor N1 drain terminal and p-well, drain terminal, substrate and source structure Into triode ON release ESD electric currents, pass through the substrate of positively biased in the second metal-oxide-semiconductor N2 and drain terminal diode to GND；When port PAD meets ESD negative sense trigger conditions to the voltage between GND, when port voltage absolute value be more than p-well with Between N- diffusion regions during diode breakdown voltage, diode is breakdown between the second metal-oxide-semiconductor N2 drain terminal and p-well, drain terminal, substrate The triode ON formed with source is released ESD electric currents, passes through the substrate and drain terminal diode of positively biased in the first metal-oxide-semiconductor N1 To port PAD.
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| CN201310695611.8A CN104716134B (en) | 2013-12-17 | 2013-12-17 | A kind of port ESD structures and its equivalent circuit based on the resistance to positive or negative high voltages of HVNMOS |
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| CN201310695611.8A CN104716134B (en) | 2013-12-17 | 2013-12-17 | A kind of port ESD structures and its equivalent circuit based on the resistance to positive or negative high voltages of HVNMOS |
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| CN104716134B true CN104716134B (en) | 2017-11-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1211075A (en) * | 1997-09-05 | 1999-03-17 | 日本电气株式会社 | Protection circuit for discharging large amount of satic charge current through field effect transistors different in break-down voltage |
| CN102754335A (en) * | 2010-01-19 | 2012-10-24 | 高通股份有限公司 | High voltage, high frequency esd protection circuit for RF ICs |
| CN102983133A (en) * | 2012-11-28 | 2013-03-20 | 江南大学 | Bidirectional tri-path turn-on high-voltage ESD protective device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100369361B1 (en) * | 2001-03-30 | 2003-01-30 | 주식회사 하이닉스반도체 | Integration circuit with self-aligned silicided ESD protection transistors |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1211075A (en) * | 1997-09-05 | 1999-03-17 | 日本电气株式会社 | Protection circuit for discharging large amount of satic charge current through field effect transistors different in break-down voltage |
| CN102754335A (en) * | 2010-01-19 | 2012-10-24 | 高通股份有限公司 | High voltage, high frequency esd protection circuit for RF ICs |
| CN102983133A (en) * | 2012-11-28 | 2013-03-20 | 江南大学 | Bidirectional tri-path turn-on high-voltage ESD protective device |
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