CN104714904A

CN104714904A - RapidIO controller adopting window mapping mechanism and control method of RapidIO controller

Info

Publication number: CN104714904A
Application number: CN201310688470.7A
Authority: CN
Inventors: 段小虎; 李鹏; 韩强; 邓豹; 解文涛; 魏巍; 赵小冬; 邹晨; 袁迹; 周啸; 代明清
Original assignee: AVIC No 631 Research Institute
Current assignee: AVIC No 631 Research Institute
Priority date: 2013-12-14
Filing date: 2013-12-14
Publication date: 2015-06-17
Anticipated expiration: 2033-12-14
Also published as: CN104714904B

Abstract

The invention provides a RapidIO controller adopting a window mapping mechanism. The controller comprises a RapidIO IP Core, a parallel local bus interacting with an external processor, an address decoding module, an expansion configuration space, an initiator request packet generating module, an initiator response packet analyzing module and an initiation bus request recording module, wherein the address decoding module decodes read-write operation chip selection on the parallel local bus to later-level accessed resources according to chip selection information of address spaces provided by configured register blocks in the expansion configuration space, the initiator request packet generating module is responsible for constructing request packets when a RapidIO bus request needs to be initiated, the initiator response packet analyzing module analyses a response packet received after the controller initiates the RapidIO bus request, the initiation bus request recording module records the RapidIO bus request which is initiated by the controller and needs the response packet. The RapidIO controller adopting the window mapping mechanism and a control method of the RapidIO controller are good in compatibility and complete in function.

Description

Adopt RapidIO controller and the control method thereof of window mapping mechanism

Technical field

The invention belongs to embedded computing system field, particularly relate to the RapidIO controller and control method thereof that adopt window mapping mechanism.

Background technology

Along with the development of integrated avionics system, on the one hand, system has had higher demand to the speed of the exchanges data between each functional module of its inside and data transmission and scale, and traditional parallel bus can not meet the needs of data transmission due to the restriction of clock frequency and signal lead; On the other hand, because system scale is increasing, based on the higher demand to System Error-tolerance Property and grid reconstruct, conventional tree-shaped bus structure have no longer been suitable as the architecture mode of whole system.Based on application demand so and development trend, avionics system needs to introduce a kind of new connection communication framework mode and solves these problems.

RapidIO technology (ISO/IEC DIS18372) is the crossbar interconnect technology of a kind of high-performance low pin count based on packet switch, is first embedded system interconnection international standard.It has employed high-speed serial bus technology, and bandwidth is high, and time delay is low, is applicable to the connection communication in high performance embedded system, is also very suitable for the tightly coupled working environment of many devices.The many employings of RapidIO interconnect architecture are based on the internet topology of switch, and in system, multiple RapidIO holds the point to point link chain route switch-fabric of equipment together, and each end equipment is all the node of equity in the entire network.Like this, each end equipment room can interconnect arbitrarily and concurrent transmission, the exchanges data that the many groups of real realization are concurrent, and break through old " sharing bandwidth " bottleneck, bandwidth can be multiplied.In addition due to each end equipment of RapidIO equity in the entire network, system configuration is more flexible, scale can increase and decrease, also whole network can not be had influence on, so good technical support can be provided for System Error-tolerance Property and grid reconstruct when certain one end device fails.These advantages of RapidIO can well solve institute's problems faced in integrated avionics system development, so the connection communication adopting RapidIO technology to come in constructing system in integrated avionic system more and more.

PowerPC new at present and High Performance DSP processor chips all have RapidIO controller mostly, and this also provides conveniently for the structure of RapidIO grid and configuration management, but not all processor all provides this support.X86, ARM, with the PowerPC that some are old, dsp processor chip does not all provide RapidIO interface, FPGA is used to realize in the application of simple processor at some in addition, also lack enough RapidIO to support, when using these processors like this in the system taking RapidIO as communication network, just need some means to make these processors can as end equipment connection in RapidIO bus.Feasible method is by a bridge chip, such as, have the bridge chip of PCIE-RapidIO.But due to bridge chip usually only other STD bus corresponding a kind of, it cannot address this is that all types of processor with versatility, and not all processor can search out suitable bridge chip as solution.Towards this demand, we designs and develops out a kind of RapidIO controller of employing window mapping mechanism newly based on fpga chip, can be any processor expansion RapidIO interface.

Along with the development of FPGA technology, the FPGA of a lot of manufacturer all provides multipath high-speed serial transceiver at present, may be used for realizing Ethernet interface, the high speed serial bus interfaces such as PCIE or RapidIO.Based on this FPGA, a lot of design corporation develops the Programmable Analog Circuits IP Core of RapidIO, what conventional RapidIO IP Core realized is the Physical layer that RapidIO holds equipment, the function of transport layer and a part of logical layer, can carry out encoding and decoding to high speed serialization code, thus the parallel data signal being converted to RapidIO packet format operates.

Summary of the invention

In order to solve technical matters existing in background technology, the present invention proposes a kind of the RapidIO controller and the control method thereof that adopt window mapping mechanism, compatible good, function is complete.

Technical solution of the present invention is: the RapidIO controller adopting window mapping mechanism, is characterized in that: comprise RapidIO IP Core, carry out mutual parallel local bus with ppu, address decoding module, expanded configuration space, initiator asks bag generation module, initiator responds Packet analyzing module and initiate the logging modle of bus request; The sheet of each address space that address decoding module provides according to the groups of configuration registers in expanded configuration space selects information that the read-write operation sheet choosing on parallel local bus is decoded to the accessed resource of each rear class; Initiator asks bag generation module to be responsible for building request bag when RapidIO bus request initiated by needs; Initiator responds the response bag received after Packet analyzing module initiates RapidIO bus request to this controller and resolves, and obtains echo message wherein and is supplied to other modules; The logging modle initiating bus request carries out record to the RapidIO bus request that bag responded by the needs that controller is initiated.

Above-mentioned controller also comprises that responder asks Packet analyzing module, responder responds bag generation module and expansion local bus; The responder that responder asks Packet analyzing module to monitor RapidIO IP Core asks packet interface to obtain the operation requests bag that in RapidIO bus, other equipment send this controller, if this request bag is read-write requests, then this read-write requests is converted to the read-write operation on expansion local bus, if this request bag is doorbell/message request, then doorbell/the information parsed is sent in expanded configuration space and process; Expansion local bus realizes the read-write operation that outside RapidIO equipment is asked, all needed carry under expansion local bus by the local resource of far-end RapidIO device access; Responder responds bag generation module and wraps according to the relevant information of request bag and the situation structure response operated and send, thus completes the whole operation response for outside RapidIO bus request.

Above-mentioned controller also comprises exchanges data double port memory, and exchanges data double port memory was both accessed by the parallel local bus of processor end, is accessed again by the expansion local bus of controller responder functional module.

Adopt the RapidIO control method of window mapping mechanism, it is characterized in that: described method comprise controller alongside one another with under type:

1) controller externally RapidIO equipment initiation read-write requests process;

2) controller externally RapidIO equipment initiation doorbell/message request process;

3) the read-write requests process of controller response external RapidIO equipment;

4) doorbell/message request process of controller response external RapidIO equipment;

5) communications and data between controller and outside RapidIO equipment transmits;

6) error handle: 6.1) controller externally RapidIO equipment initiate request time, if made a mistake, such as respond bag and ask package informatin not mate, or do not receive the response bag of expectation for a long time, then initiator responds Packet analyzing module and can find corresponding mistake with the logging modle initiating bus request, and the error handling unit in expanded configuration space is submitted in error message; 6.2) controller response external RapidIO equipment send request time, if request be surrounded by mistake, then responder asks Packet analyzing module can parse corresponding mistake, and the error handling unit in expanded configuration space is submitted in error message; 6.3) the various error message of error handling unit record in expanded configuration space, and inform interrupt processing unit where necessary, interrupt processing unit sends interruption to processor again; Processor is had no progeny in receiving, and read error information from the error handle related register in expanded configuration space, then carries out corresponding fault handling operation according to these information.

Aforesaid way 1) specifically:

1.1) processor is read and write by parallel local bus, and in configuration expanded configuration space, certain maps the groups of configuration registers of window, arranges the address space of this window, the ID of mapping address and RapidIO target device, read-write operation type;

1.2) processor carries out read-write operation to the address space of this mapping window, and this read-write operation carries out after sheet translates code and address maps selectively, sending to initiator to ask bag generation module by address decoding module;

1.3) after initiator asks bag generation module to receive the read-write operation order of this mapping window, according to the configuration information of this window that expanded configuration space provides, build corresponding read-write requests bag, and the initiator of mailing to RapidIOIP Core asks packet interface, if this request bag needs to respond bag, then the information of request bag is issued the logging modle initiating bus request simultaneously allow it carry out recording and timing.It should be noted that if the data volume of this read-write operation requirement is comparatively large in addition, initiator asks bag generation module also can split according to RapidIO specification to be configured to several RapidIO and to ask bag also to send successively;

1.4) RapidIO IP Core is after receiving the RapidIO read-write requests bag that will initiate, and is sent in RapidIO bus by Physical layer high-speed differential signal by this request bag;

1.5) outside RapidIO equipment is after receiving this RapidIO read-write requests bag, carries out corresponding read-write operation, if this request needs to respond, then also returns to this controller and responds bag;

1.6), after RapidIO IP Core is received responded bag by " Physical layer high-speed differential signal ", respond packet interface by initiator after decoding and issue initiator and respond Packet analyzing module;

1.7) initiator responds after Packet analyzing module receives and respond bag, mailing to and initiates the logging modle of bus request, allowing it record the performance of this read-write operation by responding package informatin; Simultaneously initiator responds Packet analyzing module and the response bag return data of read operation or the complement mark of write operation are mail to initiator asks bag generation module;

1.8) initiator asks bag generation module after the return data receiving read operation or the complement mark receiving write operation, complete this read-write operation of this mapping window, and feed back the corresponding read-write operation on address decoding module and parallel local bus step by step.

Aforesaid way 2) specifically:

2.1) processor is read and write by parallel local bus, and in configuration expanded configuration space, the groups of configuration registers of doorbell/message, arranges doorbell/type of message, load data, the ID of RapidIO target device, the mailbox number content of Message Transmission; After request bag related content is provided with, the command register that certain initiates doorbell/message request write by processor, thus initiates this request;

2.2) doorbell/message control unit in expanded configuration space, after the order receiving the request of initiation, obtains the information of doorbell/message request from each configuration register, and mails to initiator and ask bag generation module;

2.3) initiator asks bag generation module to build doorbell/message request according to corresponding information and the initiator of mailing to RapidIO IP Core asks packet interface, the information of request bag is issued the logging modle initiating bus request simultaneously and allows it carry out recording and timing;

2.4) RapidIO IP Core is after receiving the RapidIO doorbell/message request that will initiate, and is sent in RapidIO bus by Physical layer high-speed differential signal by this request bag;

2.5) outside RapidIO equipment is after receiving this RapidIO doorbell/message request, and record doorbell/message, completes corresponding operating, then returns response bag to this controller;

2.6), after RapidIO IP Core is received responded bag by Physical layer high-speed differential signal, respond packet interface by initiator after decoding and issue initiator and respond Packet analyzing module;

2.7) initiator responds after Packet analyzing module receives and respond bag, wherein information had both been fed back to the doorbell/message control unit in expanded configuration space, has also mail to the logging modle initiating bus request, allow it record the performance of this read-write operation;

2.8) after the doorbell/message control unit in expanded configuration space receives the response package informatin of feedback, then represent this doorbell/message request and complete, and complement mark is recorded in related register; If do not receive for a long time and respond bag, then see whether will take to retransmit by demand; Retransmit and then re-start step 2.2) to step 2.8).

Aforesaid way 3) specifically:

3.1) after outside RapidIO equipment initiates read-write requests by RapidIO bus to this controller, RapidIO IP Core receives the read-write requests bag in bus by Physical layer high-speed differential signal, ask packet interface to issue responder ask Packet analyzing module after decoding by responder;

3.2) responder asks after Packet analyzing module receives read-write requests bag, to parse the action type of wherein read-write operation, address, byte enable, the data of write, then go out to expand the read-write operation on local bus with these information architectures; Responder asks Packet analyzing module also some information of read-write requests bag will be supplied to responder and responds bag generation module simultaneously;

3.3) expand local bus and carry out the read-write operation required by read-write requests bag to the resource of carry under it, then the return data of read operation or the complement mark of write operation being mail to responder responds bag generation module;

3.4) responder responds bag generation module after the complement mark of the return data or write operation that receive read operation, according to the request package informatin that responder asks Packet analyzing module to provide, construct and respond bag accordingly, the responder of then mailing to RapidIO IP Core responds packet interface;

3.5) RapidIO IP Core is after receiving this RapidIO response bag that will send, and is sent in RapidIO bus by Physical layer high-speed differential signal by this response bag;

3.6) outside RapidIO equipment receives by RapidIO bus the response bag that this controller beams back, then complete its this time read-write requests to this controller.

Aforesaid way 4) specifically:

4.1) after outside RapidIO equipment initiates doorbell/message request by RapidIO bus to this controller, RapidIO IP Core receives the doorbell/message request in bus by Physical layer high-speed differential signal, ask packet interface to issue responder ask Packet analyzing module after decoding by responder;

4.2) responder asks after Packet analyzing module receives doorbell/message request, parse the information of doorbell/message and the doorbell/message control unit mail in expanded configuration space, some information of request bag is supplied to responder simultaneously and responds bag generation module;

4.3) responder responds doorbell/message request package informatin that bag generation module asks Packet analyzing module to provide according to responder, constructs and responds bag accordingly, and the responder of then mailing to RapidIO IP Core responds packet interface;

4.4) RapidIO IP Core is after receiving this RapidIO response bag that will send, and is sent in RapidIO bus by Physical layer high-speed differential signal by this response bag;

4.5) outside RapidIO equipment receives by RapidIO bus the response bag that this controller beams back, then complete its this time doorbell/message request to this controller;

4.6) doorbell/message control unit in expanded configuration space is after receiving doorbell/message request package informatin, be placed in corresponding register and message data buffer zone, then inform interrupt processing unit, interrupt processing unit sends interruption to processor again;

4.7) processor is had no progeny in receiving, and reads the doorbell/message request information received, then process operation accordingly according to these information from the doorbell/message related register in expanded configuration space.

Aforesaid way 5) specifically:

If mass data will be mail to outside RapidIO equipment from this controller, both write operation can be carried out by this controller directly to outside RapidIO equipment, the data write exchanges data double port memory that also can first these will be sent, then reads these data by RapidIO bus from this storer by outside RapidIO equipment; If mass data will be mail to this controller from outside RapidIO equipment, both directly read operation can be carried out to outside RapidIO equipment by this controller, also by RapidIO bus, these data can first be write exchanges data double port memory by outside RapidIO equipment, then native processor reads these data from this storer again.

Advantage of the present invention is:

1) compatibility of this controller is fine, its external interface is respectively " parallel local bus " for processor end, can follow the interface " Physical layer high-speed differential signal " of physical link for carry for " the expansion local bus " of the local resource of remote access and RapidIO FPGA (Field Programmable Gate Array) IP Core.The first two bus has expansibility, and a rear RapidIO IP Core has convertibility, and this three determines the outstanding part of the compatibility of this controller:

1.1) extensibility of " the parallel local bus " of the use of processor end, determine this controller and in the mode of " other buses-parallel local bus-RapidIO controller-RapidIO bus ", other buses any and high speed RapidIO bus can be carried out interconnected expansion, which provides a kind of new computing system framework mode.Because this controller can be expanded in any bus, thus also just can carry out expanded application on any one processor, this just make those do not have the use of processor chips in RapidIO network of integrated RapidIO controller to become possibility.Such one side can be use those not support the processor of RapidIO in the embedded system that builds of connection communication means with RapidIO in a new generation, employing legacy bus can also be carried out the new system that interconnected system upgrade changes to RapidIO framework on the other hand;

1.2) extensibility of " expansion local bus ", make any type local resource can easily carry under responder's functional module of this controller.Like this, for the different resource access demand of outside RapidIO equipment, can be realized very easily by this bus;

1.3) for system to the different linear speeds (1.25/2.5/3.125/..Gbps) of this controller and different lane number (1x/4x/ ...) demand, RapidIO IP Core can carry out customizing and changing, then in this controller, carry out simple optimum configurations and the replacing of net table, just can reach requirement.So this controller all can facilitate compatibility for the different linear speed of RapidIO bus and lane number;

Because this Controller gain variations has these good compatibility, so be applicable to the application scenario of many types, the application that faces the future also can be researched and developed according to this FPGA design, forms the asic chip of fixed function;

2) this controller employs window mapping mechanism to realize the initiation of RapidIO read-write requests, has the outstanding software compatibility, easy-to-use flexibly for various application and development.This mechanism is after carrying out suitable window configuration, just common read-write operation can be converted to the initiation of the read-write requests bag in RapidIO bus and respond the parsing of bag, so just can go to access outside RapidIO equipment as the common memory headroom of access, also convenient the different Address space mappinDs of different outside RapidIO equipment each address space to this locality by such mode, easy to be easy-to-use, the various application demands of user can be met.The very important point is in addition, can go to access outside RapidIO equipment as the local memory headroom of access by window mapping mechanism, and this is also for the application of DMA (direct memory access (DMA)) provides convenience and feasibility;

3) this controller function is complete, read-write can be supported, message, the various function such as doorbell, and the most important thing is, the initiation of this controller support maintenance read-write requests bag, this just means that this controller can initiate the read-write of the configuration space for other RapidIO equipment, thus can as the supvr of the RapidIO network of whole system and guardian.So, only need this controller, just can the whole RapidIO network of configure and maintenance, this also presents the powerful and complete of this controller function;

4) burst type (burst) read-write operation supported by this controller, can support that DMA transmits, thus can utilize the high bandwidth characteristic of RapidIO substantially.And this controller has carried out the work of subpackage and group bag in inside, so the burst read-write operation width on front end " parallel local bus " is not subject to the restriction of the data load length of wrapping in RapidIO specification.Specify in RapidIO specification that the maximum data load that a RapidIO wraps is 256 bytes, and this controller is done by realizing inner subpackage and organize job contract in " initiator asking bag generation module ", the burst read-write operation width on front end " parallel local bus " is supported that scope is up to 4095 bytes.

Accompanying drawing explanation

Fig. 1 is the hardware block diagram of this controller invention;

Fig. 2 is the schematic diagram of the window mapping mechanism of this controller invention;

Fig. 3 is that this controller is as address space distribution diagram during bus request initiator;

Fig. 4 is that this controller is as address space distribution diagram during bus request responder;

Fig. 5 is the subpackage of this controller when carrying out burst read operation and group bag schematic diagram;

Fig. 6 is the subpackage schematic diagram of this controller when carrying out burst write operation;

Embodiment

This controller uses the FPGA with high speed serialization transceiver as platform, the basis of the RapidIO FPGA (Field Programmable Gate Array) IP Core of routine carries out secondary development to realize, the front end of controller is a parallel local bus, rear end is the HSSI High-Speed Serial Interface of RapidIO interface, the mechanism adopting address window to map, achieves the mutual conversion between the operation of parallel local bus and RapidIO bus operation.

The hardware composition of this controller as shown in Figure 1.This controller carries out secondary development gained on the RapidIO FPGA (Field Programmable Gate Array) IP Core of routine, the square modules of accompanying drawing 1 right side central is RapidIOIP Core, it achieves the mutual conversion between high speed serialization code on physical link and the parallel data signal of RapidIO packet format.RapidIO IP Core mainly contains six external interfaces, is respectively " configuration space access interface ", " Physical layer high-speed differential signal ", " initiator asks packet interface ", " initiator responds packet interface ", " responder asks packet interface ", " responder responds packet interface ".According to RapidIO specification, each RapidIO equipment has a configuration space, " configuration space access interface " is the interface conducted interviews to the configuration space of RapidIO IP Core, can read and write 0x0 to the 0xFFFF configuration space address field of RapidIO IP Core." Physical layer high-speed differential signal " is the high speed serialization code on physical link, is connected with the RapidIO bus of outside via the high speed serialization transceiver of FPGA, is typically connected to a RapidIO switch.The RapidIO of a complete function holds equipment both can initiate request in bus, also the request of equipment can be held to respond to other RapidIO in bus.As the initiator of this controller as bus request, it sends operation requests bag by IP Core " initiator asks packet interface " in bus, then monitor the response bag that " initiator responds packet interface " obtains the request of initiation, thus complete whole bus request operations.As the responder of this controller as bus request, it is monitored " responder asks packet interface " and obtains the operation requests bag that in bus, other equipment send this controller, after complete operation request, to be sent to the initiator device of this operation requests by " responder responds packet interface " again and respond bag accordingly, thus complete the operation of whole bus acknowledge.Except above-described primary interface, RapidIO IP Core also has some to be used to indicate the marking signal of current link conditions.

This controller is also mainly divided into initiator's functional module and responder's functional module two large divisions of bus request around the secondary development that RapidIO IP Core carries out.Initiator's functional module is the left part of accompanying drawing 1, by " parallel local bus ", " address decoding module ", " expanded configuration space ", " initiator asks bag generation module ", the collaborative composition of " initiator responds Packet analyzing module " and " initiating the logging modle of bus request " six major part.Wherein, " parallel local bus " carries out mutual interface with ppu, and ppu is by controlling whole RapidIO controller to the read-write operation of parallel local bus.The sheet of each address space (each mapping window addressing space, data exchange storage addressing space) that the groups of configuration registers in " address decoding module " basis " expanded configuration space " provides selects information that the read-write operation sheet choosing on " parallel local bus " is decoded to the accessed resource of each rear class." expanded configuration space " is the expansion (namely in RapidIO specification, Equipments Setting space realizes the 0x10000-0xFFFFFF address field that retains for embody rule) of this RapidIO controller configuration space, the mapping window configuration of this controller is achieved in this space, doorbell/Message Processing, error monitoring, interrupt processing, Version Control, the register that the various functions such as Link State monitoring are relevant, and be integrated with error handling unit around these registers, doorbell/message control unit and interrupt processing unit etc." initiator asks bag generation module " is responsible for building request bag when RapidIO bus request initiated by needs, and request bag is mainly divided into read-write requests and the large type of doorbell/message request two.Read-write requests is realized by window mapping mechanism, by " expanded configuration space ", " address decoding module ", " initiator asks bag generation module " and " initiator responds Packet analyzing module " completes jointly, comparatively complicated, describe in detail again in " workflow of each function of the present invention " and " embodiment " chapters and sections later.Doorbell/message request is relatively simple, is the content according to related register in " expanded configuration space ", constructs the relevant information of request bag and be supplied to " initiator asks bag generation module " by doorbell/message control unit.The response bag that " initiator responds Packet analyzing module " receives after initiating RapidIO bus request to this controller is resolved, and obtains echo message wherein and is supplied to other modules.The groundwork " initiating the logging modle of bus request " carries out record to the RapidIO bus request of the needs response bag that this controller is initiated, check on the one hand and respond bag and ask to wrap whether mate and report relevant error, timing to be carried out on the other hand to the bus request that need respond, if do not receive the response bag of expectation for a long time, then report that bus request time-out does not respond mistake.

Responder's functional module of this controller is the lower right-most portion of accompanying drawing 1, comprises " responder asks Packet analyzing module ", " responder responds bag generation module " and " expansion local bus " three assemblies." responder asks packet interface " that " responder asks Packet analyzing module " monitors RapidIO IP Core obtains the operation requests bag that in RapidIO bus, other equipment send this controller, if this request bag is read-write requests, then this read-write requests is converted to the read-write operation on " expansion local bus ", if this request bag is doorbell/message request, then doorbell/the information parsed is sent in " expanded configuration space " and process." expansion local bus " realizes the read-write operation that outside RapidIO equipment is asked, all can be needed carry under " expansion local bus " by the local resource of far-end RapidIO device access.After the operation of external request completes, " responder responds bag generation module " then builds response according to the relevant information of request bag with situation about having operated and wraps and send, thus completes the whole operation response for outside RapidIO bus request.

Accompanying drawing 1 lower left corner is one " exchanges data double port memory ", this storer both by " parallel local bus " access of processor end, can be accessed (thus by outside RapidIO device access) by " the expansion local bus " of controller responder functional module again.So exchanges data can be carried out by this storer between native processor and outside RapidIO equipment.This storer can realize in FPGA inside, if want extended storage capacity, also can realize at FPGA outside memory chip.

Above-mentioned RapidIO FPGA (Field Programmable Gate Array) IP Core, initiator's functional module, responder's functional module and exchanges data double port memory organically combine, and collaborative work together form the hardware components of this RapidIO controller invention.Coordinated relation between each comprising modules, can see the related content in hereinafter " workflow of each function of the present invention " and " embodiment " chapters and sections.

The workflow of each function of the present invention is:

This RapidIO controller can externally initiate bus request, also can respond the bus request of other RapidIO equipment by RapidIO equipment, can be transmitted with carrying out between external unit communicate by RapidIO bus with data.Bus request is divided into read-write requests and doorbell/message request two type.The workflow of the several major function of this controller is as follows:

1) controller externally RapidIO equipment initiation read-write requests process: 1.1) processor is read and write by parallel local bus, in configuration expanded configuration space, certain maps the groups of configuration registers of window, the address space of this window is set, the ID of mapping address and RapidIO target device, read-write operation type;

2) controller externally RapidIO equipment initiation doorbell/message request process:

3) the read-write requests process of controller response external RapidIO equipment:

4) doorbell/message request process of controller response external RapidIO equipment:

5) communications and data between controller and outside RapidIO equipment transmits; If mass data will be mail to outside RapidIO equipment from this controller, both write operation can be carried out by this controller directly to outside RapidIO equipment, the data write exchanges data double port memory that also can first these will be sent, then reads these data by RapidIO bus from this storer by outside RapidIO equipment; If mass data will be mail to this controller from outside RapidIO equipment, both directly read operation can be carried out to outside RapidIO equipment by this controller, also by RapidIO bus, these data can first be write exchanges data double port memory by outside RapidIO equipment, then native processor reads these data from this storer again.

6) error handle: controller externally RapidIO equipment initiate request time, if made a mistake, such as respond bag and ask package informatin not mate, or do not receive the response bag of expectation for a long time, then " initiator responds Packet analyzing module " and " initiating the logging modle of bus request " can find corresponding mistake, and the error handling unit in " expanded configuration space " is submitted in error message.Controller response external RapidIO equipment send request time, if request be surrounded by mistake, then " responder asks Packet analyzing module " can parse corresponding mistake, and the error handling unit in " expanded configuration space " is submitted in error message.The various error message of error handling unit record in " expanded configuration space ", and inform interrupt processing unit where necessary, interrupt processing unit sends interruption to processor again.Processor is had no progeny in receiving, and read error information from the error handle related register in " expanded configuration space ", then carries out corresponding fault handling operation according to these information.

Below the present invention is described in further details.

Because this design comparison is complicated, so need to be described from two aspects hardware design of the present invention: Part I sets forth the implementation strategy of some complex mechanism of this controller from the angle of entirety, and Part II introduces each hardware comprising modules implementation separately respectively.

1) the overall implementation strategy of some complex mechanism

1.1) window mapping mechanism

The realization mechanism of window mapping mechanism is: for certain sector address of each outside RapidIO equipment that will access opens up a sector address space in this locality, this section of home address space is referred to as to map window, then by the parsing mapping the read and write access of window and be converted into initiation to the read-write requests bag of outside RapidIO equipment and corresponding response bag, thus the read and write access to outside RapidIO equipment is reached.By such mode, at every attribute (plot, space size, target device ID by mapping window, mapping address, read and write access type, priority etc.) configure after, just can go to access outside RapidIO equipment as the local storage space of access, correspondence is used, simply, flexibly, conveniently, transparent, and can support that DMA transmits, utilize the high bandwidth characteristic of RapidIO substantially.

Window mapping mechanism realize principle as shown in Figure 2.Each maps the configuration information of window, can be arranged by the related register group in read-write " expanded configuration space ", then each information mapping window is supplied to " address decoding module " and " initiator asks bag generation module " by " expanded configuration space ".In accompanying drawing 2, the window plot mapping window 2 is arranged in order to 0x1300_0000, window size is 0x10_0000, mapping plot is 0x8000_0000, this represents that the local address scope mapping window 2 is 0x1300_0000 to 0x130F_FFFF, and correspondence mappings has arrived 0x8000_0000 to the 0x800F_FFFF address realm of outside RapidIO equipment.Like this, when processor end is when reading address 0x1300_8C40, " address decoding module ", after address decoding, finds that it has hit mapping window 2, just the read operation of Front Side Bus conversion in order to the read operation of window 2 is penetrated in mapping, and be 0x8000_8C40 by address maps." initiator asks bag generation module " is after receiving the read access to the address 0x8000_8C40 mapping window 2, according to other information (object device id of this mapping window, read-write type, priority etc.), generate state machine by the request bag of inside construct a read request packet and mail to RapidIO IP Core, the every terms of information after this read request packet generates as shown in Figure 2.By such mode, this controller, just a read access to local 0x1300_8C40 address, is changed in order to a NREAD to the 0x8000_8C40 address of the outside RapidIO equipment that ID is 0x1 asks bag.

Be that the outside RapidIO equipment of 0x1 responds to the read request packet received and after returning and responding bag, RapidIO IP Core receives and responds bag, and it is issued " initiator responds Packet analyzing module " at ID.Respond the every terms of information of bag as shown in Figure 2, return data is wherein 0x55AA_55AA." initiator responds Packet analyzing module " feeds back to " initiator asks bag generation module " and " address decoding module " after the Data Analysis responding bag is gone out step by step, and finally as the return data of the read operation to 0x1300_8C40.This completes whole read operation process.

As mentioned above, after mapping window is configured, for the read access of the address 0x1300_8C40 in window 2, the structure of NREAD request bag of 0x8000_8C40 address of outside RapidIO equipment and the parsing of corresponding response bag of final conversion in order to ID be 0x1, and obtain the read data 0x55AA_55AA that returns, Here it is window mapping mechanism.In this way, just can remove the different address spaces of the distinct device of accessing in RapidIO bus as the local storage space of access, bring the maximum convenience of user and the transparency.

What also should be noted that is a bit, owing to safeguarding that the read-write requests of read-write requests bag (Maintenance read/write) and other types wraps in form, information and inter-process mode and has more difference, so the mapping window of this controller inside being divided into two types: a kind of for safeguarding that read-write maps window, can only being converted to such read and write access mapping window and having safeguarded read-write (Maintenance read/write) request bag; Another kind is that common read-write maps window, common read-write (NREAD/NWRITE/NWRITE_R/SWRITE) request bag or atom read-write (ATOMICinc/dec/ can be converted to such read and write access mapping window ...) request bag, the translation type of common read-write map pane mouthpiece body is determined according to the content of the related register of the configuration read-write operation type of this window.Be provided with altogether 1 in this controller and safeguard that read-write maps window and 16 common read-writes map window.In RapidIO specification, common read-write requests bag and the access of atom read-write requests bag be the bus space of RapidIO equipment, what safeguard that read-write requests bag accesses is the configuration space of RapidIO equipment.So, when needing the configuration space of accessing other RapidIO equipment (when such as carrying out the configure and maintenance of RapidIO exchange network), the maintenance read-write of this controller should be used to map window; When needing the bus space of accessing other RapidIO equipment (exchanges data such as between RapidIO equipment is with when communicating), the common read-write of this controller should be used to map window.

1.2) address space distributes

This controller both can as the initiator that RapidIO bus is asked, also can responsively side, so the distribution of its address space is also to there being such two kinds of situations.

As the initiator of this controller as RapidIO bus request, normally carry is by its access under the address space of a processor for it, and the allocation scheme of its address space is shown in accompanying drawing 3.Processor is that whole RapidIO controller distributes a sector address space, when this address space bias internal amount of processor access is the address of 0x0 to 0xFFFF, access be 0x0 to the 0xFFFF address field of the configuration space of this RapidIO controller, when this address space bias internal amount of processor access is the address of 0x10000 to 0xFFFFFF, access be " the expanded configuration space " of this RapidIO controller as shown in Figure 1, i.e. each mapping window configuration, doorbell/Message recover signature, error handle, interrupt processing, the register of Version Control etc. function.By to the configuration mapping window related register, each can be specified further to map the address space (dotted portion see accompanying drawing 3) of window.In addition, the reference address space of processor to exchanges data double port memory is also that the mode configured by corresponding registers is determined.Finally, each mapping window again according to the content map of its configuration register to the RapidIO device id of specifying separately and address field thereof.

As the responder of this controller as RapidIO bus request, it has two parts address space.As shown in Figure 4, when outside RapidIO equipment to this controller carry out maintenance read-write (Maintenanceread/write) ask time, 0x0 to the 0xFFFF address field of this controller configuration space can be had access to; When carrying out common read-write requests, access be " the expansion local bus " of responder's functional module of this controller.Under " expansion local bus ", the resource of carry is exchanges data double port memory and each local resource for outside RapidIO device access.

1.3) initiator asks to wrap and respond the matching check wrapped

As the initiator of this controller as RapidIO bus request, externally RapidIO equipment initiates request bag, and according to the difference of request Packet type, the request bag of some type needs counterpart device to return to respond bag accordingly.In order to ensure correctness and the reliability of bus request operations, controller needs to ask bag to initiator and respond bag to carry out matching check one to one.

In RapidIO specification, request bag and its respond in bag accordingly, have some customizing messages to be consistent and one to one, this controller carries out the matching check of asking bag and responding bag according to these customizing messages.For read-write requests and doorbell request, carry out asking bag and responding the correspondence of wrapping with the Transaction ID in wrapping; For message request, jointly carry out the correspondence of asking bag and responding bag with the letter of message, mbox and msgseg/xmbox.Here, these specific corresponding informances of RapidIO request bag and response bag are referred to as " match index ".

When " initiator asks bag generation module " builds and send a RapidIO request bag, if this request bag needs to respond bag accordingly, then the information that this request is wrapped is submitted to " logging modle initiating bus request "." initiate the logging modle of bus request " asking the information of bag with " match index " for address is deposited in an internal storage, and carry out timing for each request bag maintenance internal counter.This controller is provided with 32 such internal counters, so initiator's functional module can have at most simultaneously 32 request bags to be responded.

When " initiator responds Packet analyzing module " receives a RapidIO response bag, the information that this response is wrapped is submitted to " logging modle initiating bus request ".The logging modle of bus request " initiate " is to respond " match index " information in bag for address, related data in inquiry request package informatin storer, asked package informatin accordingly, then request package informatin and response package informatin are analyzed, check whether coupling, if coupling, by the erasing of information of this request bag in request package informatin storer, and its corresponding internal counter is closed, if do not mate, reporting errors.

By above mechanism, can check on the one hand and respond bag and ask to wrap whether can correctly mate, if do not mate, reporting errors, if certain request bag does not receive for a long time after initiating and responds bag on the other hand, can be monitored by aforesaid internal counter, if counter is overtime, then report time-out error.The timeouts of this counter can be configured by the corresponding registers of configuration space.

1.4) initiator's burst type (burst) realization of reading and writing and subpackage and group bag

In order to the high bandwidth characteristic of maximum using RapidIO high-speed serial bus, this controller achieves burst type (burst) read-write, and burst read-write will transmit many beat of data in a read-write operation.Because the data load length of RapidIO read-write requests bag is specified by RapidIO specification, and the data volume of a burst read-write is determined by processor and bus thereof, so there is the problem be fitted to each other between both.When the data load length of processor end to the read-write requests bag that the data length of the burst read-write of " parallel local bus " and RapidIO specification specify is inconsistent, " initiator asks bag generation module " of this controller has carried out the process of subpackage and group bag, asks bag to complete a burst read-write operation with multiple RapidIO.

For read request packet, specify in RapidIO specification its length can for 1-8,16,32,64,96,128,160,192,224,256 bytes.When the data length of front end burst read operation is not these length, just carry out a point package operation.When " initiator asks bag generation module " to receive certain burst length mapping window 0x8000_0000 mapping address be the read operation of 300 bytes, the flow process of its subpackage and group bag as shown in Figure 5.Building initiator asks the state machine wrapped first to build and to send first address be the read request length of 0x8000_0000 is the read request packet of 256 bytes, after treating that its data response bag receives, building second address is again that the read request length of 0x8000_0100 is the read request packet of 32 bytes and sends, the like continue the read request packet of transmission the 3rd 8 bytes and the read request packet of the 4th 4 bytes, finally complete the read operation of 300 bytes.In this process, the data of each data response bag return to Front Side Bus successively, complete whole burst read operation.

For write request bag, specify in RapidIO specification its length can for 1-8,16,32,64,128,256 bytes.When the data length of front end burst write operation is not these length, just carry out a point package operation.When " initiator asks bag generation module " to receive certain burst length mapping window 0x8000_0000 mapping address be the write operation of 300 bytes, its subpackage flow process as shown in Figure 6.Building initiator asks the state machine wrapped build successively and send four write request bags, its " data length/address " is followed successively by 256/0x8000_0000,32/0x8000_0100,8/0x8000_0120,4/0x8000_0128, what all have corresponding length in each write request bag writes data load, finally completes the write operation of 300 bytes.

2) specific implementation of each comprising modules

2.1) expanded configuration space

0x10000 to the 0xFFFFFF address field of the configuration space of RapidIO controller and the read-write capability to this part address is achieved in " expanded configuration space ".The configuration register of each function of controller realizes all in this section, comprise and map window configuration register, doorbell/messaging control register, error handle register, interrupt processing register, exchanges data double port memory configuration register, version management register, Link State control register etc." expanded configuration space " also more integrated functional realiey relevant with each register in addition, such as the information mapping window configuration register is supplied to other modules, the process of doorbell/message, error message record, interrupt the configuration etc. of enable and shielding, exchanges data double port memory reference address.Several larger word functional module integrated in " expanded configuration space " has:

2.1.1) doorbell/message control unit

" doorbell/message control unit " is responsible for this controller external device on the one hand and initiates doorbell/message request, will process on the other hand to doorbell/message that external unit is sent.

When initiating doorbell/message, control module, according to the information in corresponding configuration register and data buffer, mails to " initiator asks bag generation module " the information of doorbell/message request and allows it build respective request bag and to send.Then control module starts the response bag waiting for this request bag, respond bag time-out error occurs or have received respond bag but respond bag when representing that this solicit operation is unsuccessful and complete if do not received for a long time, control module initiates this doorbell/message request again, until request is successfully completed or reaches the sending times of restriction.If reach the sending times upper limit but still do not complete this doorbell/message request, then recording-related information sends interruption to " interrupt processing unit " and carrys out notification processor to corresponding registers and carry out subsequent treatment.

When receiving doorbell/message that external unit is sent, control module leaves in the information of these doorbell/message in corresponding register and data buffer, then sends to " interrupt processing unit " and interrupts the information content that notification processor reads away doorbell and message from register and data buffer.In addition, the message due to RapidIO is mailbox, and each RapidIO equipment can have multiple mailbox, so will safeguard a message data buffer area for each mailbox number of this control.

2.1.2) error handling unit

" error handling unit " gets off to be stored in register and buffer zone to the error message book of final entry that whole RapidIO controller functions module occurs, and refers to the error handle part in the chapters and sections introducing this controller workflow above.Then " error handling unit " is according to the danger classes made a mistake and number of times, and judging whether needs the mode by interrupting to carry out notification processor.If need produce interrupt, then to " interrupt processing unit " send interrupt come notification processor from register and buffer zone, read away current error message record.

2.1.3) interrupt processing unit

" interrupt processing unit " summarizes the various processor that needs and carries out the interrupt event responded, and such as this controller makes a mistake, physical link is reached the standard grade and roll off the production line, send doorbell/message failure, receives outside doorbell/message etc." interrupt processing unit " can carry out enable and shielding according to interrupting arranging of related register to these interrupt events, if there is certain unscreened interrupt event there occurs, then look-at-me is set to and effectively carrys out notification processor and carry out corresponding operating by " interrupt processing unit ".Processor is had no progeny in receiving, and can read and represent the register of Current interrupt state judges to there occurs which kind of interrupt event, and be for further processing.

2.2) address decoding module

" address decoding module " obtains from " expanded configuration space " the reference address segment information that each maps window and exchanges data double port memory, is used as the foundation of address decoding.

When processor end carries out read and write access to " parallel local bus ", address decoding is carried out in the address that " address decoding module " accesses: the access access of 0x0 to 0xFFFF being decoded as the configuration space to RapidIO IP Core; The access of 0x10000 to 0xFFFFFF is decoded as the access to each register in " expanded configuration space "; The access of exchanges data double port memory reference address section will be decoded as to the read-write to this storer; Be transmitted to " initiator asks bag generation module " after row address of going forward side by side to the access decoding of each mapping window is mapped.

2.3) initiator asks bag generation module

" initiator asks bag generation module " using state machine carries out the structure of asking bag.When receive the initiation request of the read and write access of window or doorbell/message is mapped to certain time, starting state machine, then state machine is according to the address of read and write access, data, the mapping configuration information of window and the solicited message of doorbell/message build request bag, and send to " initiator asks packet interface " of RapidIO IP Core.If the request bag sent needs to respond bag, also need the information that this request is wrapped to be presented " logging modle initiating bus request " and allow its record in order to carrying out response bag matching check.

When to map the read and write access of window be burst type (burst) access time, " initiator asks bag generation module " may also need to carry out subpackage and group job contract work, this part operational detail above " realization that initiator's burst type (burst) is read and write and subpackage and group bag " chapters and sections describe in detail, repeat no more.

2.4) initiator responds Packet analyzing module

" initiator responds Packet analyzing module " resolves the response bag received after initiation bus request.If the response bag of doorbell/message, doorbell/message elements echo message need being issued " expanded configuration space " processes to allow it, if the band data response bag that read request returns, the data parsed need be issued " initiator's request module " and allow it complete the read operation mapping window.

When resolving response bag, if find that there is the mistakes such as form, need error handling unit error message being reported to " expanded configuration space ".In addition, " initiator responds Packet analyzing module " also needs to be transmitted to the logging modle of bus request " initiate " to allow it carry out response bag matching check responding a package informatin.

2.5) logging modle of bus request is initiated

Achieve a request package informatin storer and 32 internal counters in " initiating the logging modle of bus request ", and request is wrapped and responds the matching check of bag to have used these storer sum counters to carry out.Request package informatin storer is for storing the information of the request bag of the bag that awaits a response, after response bag returns, matching check is carried out according to it, internal counter carries out timing for the request bag treating response, to judge whether to there occurs the mistake that bus request time-out does not receive response.If found mistake, need error handling unit error message being reported to " expanded configuration space ".The realization of these functions above " initiator asks to wrap and respond the matching check wrapped " chapters and sections describe in detail, repeat no more.

2.6) responder asks Packet analyzing module

" responder asks Packet analyzing module ", after the request bag receiving outside RapidIO equipment, is resolved the content of request bag, is done different operations according to different request Packet type.If doorbell/message request, then information analysis wherein to be gone out and the doorbell/message control unit mailing to " expanded configuration space " is further processed.If read-write requests bag, then by address wherein, data, byte enable, the information analysis such as visit data length (burst length) go out, and then construct corresponding read and write access operation and mail to " expansion local bus " and go to allow it access the rear class resource of its carry.

When resolving request bag, if find that there is the mistakes such as form, need error handling unit error message being reported to " expanded configuration space ".In addition, " responder asks Packet analyzing module " also needs request package informatin needs being responded bag to forward toward " responder responds bag generation module ", allows it build and responds bag.

2.7) responder responds bag generation module

After the request bag that outside RapidIO equipment is sent, if this request bag needs to respond bag, then " responder responds bag generation module " is responded accordingly to wrap and mail to RapidIO IPCore according to the information architecture of request bag and is allowed it send.

For the response bag not with data load, only need can build according to the information of request bag to respond bag; For the response bag of band data load, except the information of request bag, also need to use the return data of " expansion local bus " upper read operation to build and respond bag.

2.8) exchanges data double port memory

" exchanges data double port memory " comprises two access ports, both can by " parallel local bus " access of processor end, also can be accessed by " the expansion local bus " of responder's functional module end, reach the exchanges data of native processor and outside RapidIO equipment like this.Introduce in the chapters and sections of this controller workflow above, the access mode using this storer to reach data communication is introduced.

" exchanges data double port memory " can realize in FPGA inside, but memory capacity can limit to some extent, if need larger capacity, also special memory chip can be used to realize in FPGA outside.

2.9) parallel local bus and expansion local bus

This controller comprises Liang Ge local bus interface, is respectively " the parallel local bus " of processor end and " the expansion local bus " of responder's functional module end." parallel local bus " visits this controller by processor, and " expansion local bus " is the rear class resource that this controller visits other carries, and both access sides are to difference.

Two cover parallel buss are except the clock of routine, reset, sheet choosing, reading and writing, address, data, byte enable, also increase burst access flag newly, burst access width, read response of shaking hands, write the signals such as response of shaking hands, use these signals to complete burst read-write operation.

Claims

1. adopt the RapidIO controller of window mapping mechanism, it is characterized in that: comprise RapidIO IP Core, carry out mutual parallel local bus with ppu, address decoding module, expanded configuration space, initiator asks bag generation module, initiator responds Packet analyzing module and initiate the logging modle of bus request; The sheet of each address space that address decoding module provides according to the groups of configuration registers in expanded configuration space selects information that the read-write operation sheet choosing on parallel local bus is decoded to the accessed resource of each rear class; Initiator asks bag generation module to be responsible for building request bag when RapidIO bus request initiated by needs; Initiator responds the response bag received after Packet analyzing module initiates RapidIO bus request to this controller and resolves, and obtains echo message wherein and is supplied to other modules; The logging modle initiating bus request carries out record to the RapidIO bus request that bag responded by the needs that controller is initiated.

2. the RapidIO controller of employing window mapping mechanism according to claim 1, is characterized in that: described controller also comprises that responder asks Packet analyzing module, responder responds bag generation module and expansion local bus; The responder that responder asks Packet analyzing module to monitor RapidIO IP Core asks packet interface to obtain the operation requests bag that in RapidIO bus, other equipment send this controller, if this request bag is read-write requests, then this read-write requests is converted to the read-write operation on expansion local bus, if this request bag is doorbell/message request, then doorbell/the information parsed is sent in expanded configuration space and process; Expansion local bus realizes the read-write operation that outside RapidIO equipment is asked, all needed carry under expansion local bus by the local resource of far-end RapidIO device access; Responder responds bag generation module and wraps according to the relevant information of request bag and the situation structure response operated and send, thus completes the whole operation response for outside RapidIO bus request.

3. the RapidIO controller of employing window mapping mechanism according to claim 2, it is characterized in that: described controller also comprises exchanges data double port memory, exchanges data double port memory was both accessed by the parallel local bus of processor end, was accessed again by the expansion local bus of controller responder functional module.

4. adopt the RapidIO control method of window mapping mechanism, it is characterized in that: described method comprise controller alongside one another with under type:

5. the RapidIO control method of employing window mapping mechanism according to claim 4, is characterized in that: described mode 1) specifically:

6. the RapidIO control method of employing window mapping mechanism according to claim 4, is characterized in that: described mode 2) specifically:

7. the RapidIO control method of employing window mapping mechanism according to claim 4, is characterized in that: described mode 3) specifically:

8. the RapidIO control method of employing window mapping mechanism according to claim 4, is characterized in that: described mode 4) specifically:

9. the RapidIO control method of employing window mapping mechanism according to claim 4, it is characterized in that: described mode 5) specifically: if mass data will be mail to outside RapidIO equipment from this controller, both write operation can be carried out by this controller directly to outside RapidIO equipment, the data write exchanges data double port memory that also can first these will be sent, then reads these data by RapidIO bus from this storer by outside RapidIO equipment; If mass data will be mail to this controller from outside RapidIO equipment, both directly read operation can be carried out to outside RapidIO equipment by this controller, also by RapidIO bus, these data can first be write exchanges data double port memory by outside RapidIO equipment, then native processor reads these data from this storer again.