CN104714832A - Buffer management method used for airborne data network asynchronous data interaction area - Google Patents
Buffer management method used for airborne data network asynchronous data interaction area Download PDFInfo
- Publication number
- CN104714832A CN104714832A CN201310688821.4A CN201310688821A CN104714832A CN 104714832 A CN104714832 A CN 104714832A CN 201310688821 A CN201310688821 A CN 201310688821A CN 104714832 A CN104714832 A CN 104714832A
- Authority
- CN
- China
- Prior art keywords
- data
- empty
- dpram
- management method
- network asynchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention relates to a buffer management method used for an airborne data network asynchronous data interaction area. The buffer management method used for the airborne data network asynchronous data interaction area includes the steps of receiving data frames. The steps of receiving the data frames includes the following steps that 1, a FPGA module in a link layer detects whether receive buffer FIFO is empty or not all the time, and if the receive buffer FIFO is not empty, data in the receive buffer FIFO on the ES end are read out and sent to outside receive DPRAM; if the receive buffer FIFO is empty, the receiving of the data frames is abandoned; 2, a transport layer software operating in a CPU polls and visits the outside receive DPRAM in real time to judge whether all DPRAM spaces are empty or not, and if all DPRAM spaces are empty, the CPU reads data in the DPRAM; and if not, the receiving of the data frames is abandoned. According to the buffer management method used for the airborne data network asynchronous data interaction area, the data buffer management is perfect, the data addressing is convenient and fast, and the accessing is high efficient.
Description
Technical field
The invention belongs to the airborne computer communication technology, relate to a kind of data interaction amortization management method, particularly relate to a kind of amortization management method for the network asynchronous data interaction district of on-board data.
Background technology
Network terminal system is connected to aviation electronics application subsystem main frame by the PMC interface of standard, and the buffering providing communication interface to complete data to host application, sends and reception.
In data transmit-receive process, due to FPGA with run on the otherness of transport layer software in processing power and speed etc. on CPU, the two needs asynchronous to carry out interactive access to meet determinacy and the performance index such as reception, transmission technology time delay of the transmission of onboard networks data to buffered data district.
Summary of the invention
In order to solve the above-mentioned technical matters existed in background technology, the invention provides that a kind of data buffering is well-managed, addressing data is convenient and access efficiently for the amortization management method in the network asynchronous data interaction district of on-board data.
Technical solution of the present invention is: the invention provides a kind of amortization management method for the network asynchronous data interaction district of on-board data, its special character is: described method comprises the step of receiving data frames; The step of described receiving data frames comprises following sub-step:
1) FPGA module being in link layer detects whether its reception buffering FIFO is empty always, if be not empty, then the data reading that ES termination is received in buffer memory FIFO is delivered to external reception DPRAM; If fruit is empty, then abandon receiving data frames;
2) operating in the transport layer software poll of CPU and real time access external reception DPRAM, whether be empty, if so, then CPU reads the data in DPRAM if judging that DPRAM has living space; If not, then receiving data frames is abandoned.
Above-mentioned steps 2) specific implementation be:
2.1) tail pointer pr and head pointer pw is set; Described tail pointer pr and head pointer pw forms buffer circle; Described CPU and FPGA be control head pointer pw and tail pointer pr respectively; Described tail pointer pr points to the position of data reading buffer zone; Described head pointer pw points to the position of the write of data;
2.2) whether have living space according to the position judgment DPRAM of head pointer pw and tail pointer pr is empty; If empty, then CPU reads the data in DPRAM, and the value of the register corresponding to head pointer adds 1; If not empty, then abandon receiving data frames.
Above-mentioned DPRAM have living space that to be whether empty basis for estimation be:
Circle queue length is M, then team's empty condition is: pr=pw; The condition of non-NULL is [(pw+1) modM]==pr.
The above-mentioned amortization management method for the network asynchronous data interaction district of on-board data also comprises the step sending Frame, and the described step of transmission Frame is contrary with the step of receiving data frames.
Advantage of the present invention is:
The present invention utilizes transport layer software interface and link layer FPGA respectively to manage one end of dual-ported memory, both realizations are to the asynchronous access of data in buffer area and access, while equalization processor and FPGA data processing speed difference, avoid the two to access same buffer zone at synchronization, and the uncertain factor caused.Data buffering adopts ping-pong buffers, loop buffer etc. usually, and ping-pong buffers adopts two buffer areas alternately to deposit the cleanliness process (as 1553B bus system) of data, is characterized in succinct efficient, the saving storage space of process; Adopt multiple buffer zone then can looping queue to manage, be applicable to the network service of the high amount of traffic amounts such as AFDX, FC and TTE, and reach the highest in transfer efficiency.Therefore, consider that when designing airborne data communication system between FPGA and the CPU running transport layer software, introduce dual-ported memory (DPRAM) carrys out looping buffering, and introduce a set of cache management mechanism and coordinate CPU and FPGA asynchronous, mutual access is carried out to this loop buffer.The management method of loop buffer proposed by the invention, ensure access dual-ported memory efficient, asynchronous between transport layer and link layer in onboard networks system, the performances such as the determinacy of guarantee data end-to-end time delay and treatment technology time delay meet the requirement of particular network.
Embodiment
The invention provides a kind of amortization management method for the network asynchronous data interaction district of on-board data, comprise the step of receiving data frames; The step of this receiving data frames comprises following sub-step:
1) FPGA module being in link layer detects whether its reception buffering FIFO is empty always, if be not empty, then the data reading that ES termination is received in buffer memory FIFO is delivered to external reception DPRAM; If fruit is empty, then abandon receiving data frames;
2) operating in the transport layer software poll of CPU and real time access external reception DPRAM, whether be empty, if so, then CPU reads the data in DPRAM if judging that DPRAM has living space; If not, then receiving data frames is abandoned:
2.1) tail pointer pr and head pointer pw is set; Described tail pointer pr and head pointer pw forms buffer circle; Described CPU and FPGA be control head pointer pw and tail pointer pr respectively; Described tail pointer pr points to the position of data reading buffer zone; Described head pointer pw points to the position of the write of data;
2.2) whether have living space according to the position judgment DPRAM of head pointer pw and tail pointer pr is empty; If empty, then CPU reads the data in DPRAM, and the value of the register corresponding to head pointer adds 1; If not empty, then abandon receiving data frames.
DPRAM have living space that to be whether empty basis for estimation be:
Circle queue length is M, then team's empty condition is: pr=pw; The condition of non-NULL is [(pw+1) modM]==pr.
Meanwhile, the amortization management method for the network asynchronous data interaction district of on-board data also comprises the step sending Frame, and sending the step of Frame is contrary with the step of receiving data frames.
Perfect cache management:
The asynchronous controlling strategy of loop buffer: for the difference characteristic of the aspects such as CPU and FPGA access speed, design annular data buffering and make CPU and FPGA control team's head (pw) and tail of the queue (pr) respectively, the two asynchronous operation thus the rate-matched that cooperated when transceiving data frame;
Loop buffer judges the method that team is empty, team is full: conventional method establishes label method, forbidding elements method, team leader's counter process etc.Consider the order integrality of asynchronous controlling strategy and Frame, if label method and team leader's counter process be not suitable for the design's method.Assuming that circle queue length is M, then team's empty condition is: pr==pw; The full condition of team is [(pw+1) mod M]==pr;
Circle queue length dynamic and configurable: queue length can configure and be loaded in system before system initialization, also the reconfiguring of dynamic when system cloud gray model.
Addressing data is convenient:
If AFDX data frame length scope is 64 ~ 1518B, therefore data interaction district DPRAM can be divided into the buffer zone of 2KB size according to Frame maximum length, every frame takies a buffer zone.Such access data frame can simply by the mode addressing of buffer zone start address (pointer).
Access is efficient:
This loop buffer can carry out data parallel, asynchronous access efficiently, and namely CPU and FPGA can access this data interaction district from team's head and tail of the queue respectively, improves the concurrency of data access.
The invention provides a kind of amortization management method for the network asynchronous data interaction district of on-board data, terminal system is connected to main frame aviation electronics application subsystem in data transmit-receive process by standard P MC interface, due to FPGA with run on the otherness of transport layer software in processing power and speed etc. on CPU, the two needs asynchronous to carry out interactive access to meet determinacy and the performance index such as reception, transmission technology time delay of the transmission of onboard networks data to buffered data district.
Data buffering adopts ping-pong buffers, loop buffer etc. usually, and ping-pong buffers adopts two buffer areas alternately to deposit the cleanliness process (as 1553B bus system) of data, is characterized in succinct efficient, the saving storage space of process; Adopt multiple buffer zone then can looping queue to manage, be applicable to the network service of the high amount of traffic amounts such as AFDX, FC and TTE, and reach the highest in transfer efficiency.
Example (transmit operation treatment scheme is also similar) is operating as with receiving data frames, the FPGA module being in link layer detects whether its reception buffering FIFO is empty always, if be not empty, just the data reading that ES termination is received in buffer memory FIFO is delivered to external reception DPRAM.
Operate in the transport layer software poll of CPU and real time access external reception DPRAM, judged whether that data exist.Top priority is idle condition in inquiry storage area.Adopt inquiry mode to use sequential search, flag register also can be adopted to characterize store status.Are FPGA controls DPRAM owing to storing data, reading data is CPU control DPRAM, be therefore reception data to the storage of data and reading manner is particularly important.
Therefore tail pointer and head pointer should be set, use tail pointer to point to the position of data reading buffer zone, head pointer points to the position of the write of data.The processing speed of CPU, much larger than the clock frequency of FPGA, can cause at a time, and data are stored in while buffer area, and CPU also just in time reads this position, and this should be avoided.In order to avoid writing and reading same storage space, after receiving data, head pointer register value adds 1.And according to pointer end to end, judge that buffer memory DPRAM have living space is as sky.For reception data, buffer memory DPRAM should ensure have living space as sky.
End system concordance list is made up of the register resources of FPGA, and CPU can conduct interviews to these registers, obtains pointer end to end according to these registers, and then judges whether receive DPRAM is empty.If be not empty, receive DPRAM by head pointer access, read the corresponding data received in buffer zone.
Claims (4)
1. for the amortization management method in the network asynchronous data interaction district of on-board data, it is characterized in that: described method comprises the step of receiving data frames; The step of described receiving data frames comprises following sub-step:
1) FPGA module being in link layer detects whether its reception buffering FIFO is empty always, if be not empty, then the data reading that ES termination is received in buffer memory FIFO is delivered to external reception DPRAM; If fruit is empty, then abandon receiving data frames;
2) operating in the transport layer software poll of CPU and real time access external reception DPRAM, whether be empty, if so, then CPU reads the data in DPRAM if judging that DPRAM has living space; If not, then receiving data frames is abandoned.
2. the amortization management method for the network asynchronous data interaction district of on-board data according to claim 1, is characterized in that: described step 2) specific implementation be:
2.1) tail pointer pr and head pointer pw is set; Described tail pointer pr and head pointer pw forms buffer circle; Described CPU and FPGA be control head pointer pw and tail pointer pr respectively; Described tail pointer pr points to the position of data reading buffer zone; Described head pointer pw points to the position of the write of data;
2.2) whether have living space according to the position judgment DPRAM of head pointer pw and tail pointer pr is empty; If empty, then CPU reads the data in DPRAM, and the value of the register corresponding to head pointer adds 1; If not empty, then abandon receiving data frames.
3. the amortization management method for the network asynchronous data interaction district of on-board data according to claim 2, is characterized in that: described DPRAM have living space that to be whether empty basis for estimation be:
Circle queue length is M, then team's empty condition is: pr=pw; The condition of non-NULL is [(pw+1) modM]==pr.
4. the amortization management method for the network asynchronous data interaction district of on-board data according to claim 1 or 2 or 3, it is characterized in that: the described amortization management method for the network asynchronous data interaction district of on-board data also comprises the step sending Frame, and the described step of transmission Frame is contrary with the step of receiving data frames.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310688821.4A CN104714832A (en) | 2013-12-14 | 2013-12-14 | Buffer management method used for airborne data network asynchronous data interaction area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310688821.4A CN104714832A (en) | 2013-12-14 | 2013-12-14 | Buffer management method used for airborne data network asynchronous data interaction area |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104714832A true CN104714832A (en) | 2015-06-17 |
Family
ID=53414202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310688821.4A Pending CN104714832A (en) | 2013-12-14 | 2013-12-14 | Buffer management method used for airborne data network asynchronous data interaction area |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104714832A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120922A (en) * | 2019-05-14 | 2019-08-13 | 中国核动力研究设计院 | A kind of data interaction Network Management System and method based on FPGA |
| CN110704355A (en) * | 2019-09-23 | 2020-01-17 | 天津津航计算技术研究所 | Method for receiving and processing 1553B bus data by using dual-port RAM |
| CN110727402A (en) * | 2019-09-12 | 2020-01-24 | 中航光电科技股份有限公司 | High-speed FC data real-time receiving and frame loss-free storage method |
| CN110798734A (en) * | 2018-08-02 | 2020-02-14 | 广州视源电子科技股份有限公司 | Video frame caching and forwarding method and device and computer equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1353523A (en) * | 2000-11-07 | 2002-06-12 | 华为技术有限公司 | Switch network card tester and method |
| US20060005087A1 (en) * | 2003-09-25 | 2006-01-05 | Ristau Randall D | System and method for built-in testing of a gps receiver |
| CN101527658A (en) * | 2009-04-13 | 2009-09-09 | 重庆重邮东电通信技术有限公司 | Portable gigabit Ethernet network performance tester and manufacturing method thereof |
| CN101692214A (en) * | 2009-09-17 | 2010-04-07 | 中国电子科技集团公司第四十一研究所 | High speed indirect access device and method between CPU and FPGA |
| CN101771598A (en) * | 2008-12-31 | 2010-07-07 | 中国航空工业第一集团公司第六三一研究所 | Communication dispatching method of real-time Ethernet |
| US20100262754A1 (en) * | 2009-04-10 | 2010-10-14 | Victor Mamontov | Cpu data bus pld/fpga interface using dual port ram structure built in pld |
-
2013
- 2013-12-14 CN CN201310688821.4A patent/CN104714832A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1353523A (en) * | 2000-11-07 | 2002-06-12 | 华为技术有限公司 | Switch network card tester and method |
| US20060005087A1 (en) * | 2003-09-25 | 2006-01-05 | Ristau Randall D | System and method for built-in testing of a gps receiver |
| CN101771598A (en) * | 2008-12-31 | 2010-07-07 | 中国航空工业第一集团公司第六三一研究所 | Communication dispatching method of real-time Ethernet |
| US20100262754A1 (en) * | 2009-04-10 | 2010-10-14 | Victor Mamontov | Cpu data bus pld/fpga interface using dual port ram structure built in pld |
| CN101527658A (en) * | 2009-04-13 | 2009-09-09 | 重庆重邮东电通信技术有限公司 | Portable gigabit Ethernet network performance tester and manufacturing method thereof |
| CN101692214A (en) * | 2009-09-17 | 2010-04-07 | 中国电子科技集团公司第四十一研究所 | High speed indirect access device and method between CPU and FPGA |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110798734A (en) * | 2018-08-02 | 2020-02-14 | 广州视源电子科技股份有限公司 | Video frame caching and forwarding method and device and computer equipment |
| CN110120922A (en) * | 2019-05-14 | 2019-08-13 | 中国核动力研究设计院 | A kind of data interaction Network Management System and method based on FPGA |
| CN110120922B (en) * | 2019-05-14 | 2022-09-20 | 中核控制系统工程有限公司 | FPGA-based data interaction network management system and method |
| CN110727402A (en) * | 2019-09-12 | 2020-01-24 | 中航光电科技股份有限公司 | High-speed FC data real-time receiving and frame loss-free storage method |
| CN110727402B (en) * | 2019-09-12 | 2022-03-15 | 中航光电科技股份有限公司 | High-speed FC data real-time receiving and frame loss-free storage method |
| CN110704355A (en) * | 2019-09-23 | 2020-01-17 | 天津津航计算技术研究所 | Method for receiving and processing 1553B bus data by using dual-port RAM |
| CN110704355B (en) * | 2019-09-23 | 2022-10-28 | 天津津航计算技术研究所 | Method for receiving and processing 1553B bus data by using dual-port RAM |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20200174953A1 (en) | Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link | |
| US10705974B2 (en) | Data processing method and NVME storage device | |
| US20160132541A1 (en) | Efficient implementations for mapreduce systems | |
| WO2015197027A1 (en) | Method for accessing nvme storage device, and nvme storage device | |
| CN105376129B (en) | One kind 1394 bus transaction layers-link layer data packet transmission circuit and method | |
| CN101420720A (en) | Schedule and data caching for wireless tranmission | |
| CN102841869B (en) | Multi-channel I2C controller based on FPGA | |
| CN102314400B (en) | Method and device for dispersing converged DMA (Direct Memory Access) | |
| CN104714832A (en) | Buffer management method used for airborne data network asynchronous data interaction area | |
| CN103746938A (en) | Method and device for transmitting data packet | |
| CN103150427A (en) | RAID design method based on SSD caching acceleration and backup | |
| US11500541B2 (en) | Memory system and controlling method | |
| CN101237415A (en) | A method for realizing IP core of ARP protocol | |
| CN101478462B (en) | Apparatus and method for storage data reading and writing, solid hard disk | |
| US9116881B2 (en) | Routing switch apparatus, network switch system, and routing switching method | |
| CN106662895A (en) | Computer device and data read-write method for computer device | |
| CN102843435A (en) | Access and response method and access and response system of storing medium in cluster system | |
| CN114706531A (en) | Data processing method, device, chip, equipment and medium | |
| CN108614792B (en) | 1394 transaction layer data packet storage management method and circuit | |
| US9288163B2 (en) | Low-latency packet receive method for networking devices | |
| CN115904259B (en) | Processing method and related device of nonvolatile memory standard NVMe instruction | |
| CN104317747A (en) | Data caching and sending device and method of network receiver | |
| CN113691466A (en) | Data transmission method, intelligent network card, computing device and storage medium | |
| CN103442091A (en) | Data transmission method and device | |
| CN103701865A (en) | Data transmission method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150617 |
|
| WD01 | Invention patent application deemed withdrawn after publication |