CN104701371B - radio frequency LDMOS device and manufacturing method - Google Patents
radio frequency LDMOS device and manufacturing method Download PDFInfo
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- CN104701371B CN104701371B CN201310659228.7A CN201310659228A CN104701371B CN 104701371 B CN104701371 B CN 104701371B CN 201310659228 A CN201310659228 A CN 201310659228A CN 104701371 B CN104701371 B CN 104701371B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 267
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 267
- 239000010703 silicon Substances 0.000 claims abstract description 267
- 238000000407 epitaxy Methods 0.000 claims abstract description 214
- 230000015556 catabolic process Effects 0.000 claims abstract description 22
- 230000000694 effects Effects 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 102
- 229920005591 polysilicon Polymers 0.000 claims description 98
- 238000000034 method Methods 0.000 claims description 50
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 31
- 150000002500 ions Chemical class 0.000 claims description 30
- 238000005468 ion implantation Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 27
- 229910021332 silicide Inorganic materials 0.000 claims description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 229910052787 antimony Inorganic materials 0.000 claims description 8
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical group [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- 238000004151 rapid thermal annealing Methods 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 230000005684 electric field Effects 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000001934 delay Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000265 homogenisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention discloses a kind of radio frequency LDMOS device, silicon epitaxy layer is formed by stacking by the first silicon epitaxy layer, the second silicon epitaxy layer and third silicon epitaxy layer for being sequentially formed in surface of silicon；Drift region and channel region are formed in third silicon epitaxy layer, and the second silicon epitaxy layer is formed in drift region and the bottom of channel region, by the doping concentration of the second silicon epitaxy layer be more than first and three silicon epitaxy layer doping concentration.By adjusting the conducting resistance and drain terminal junction breakdown voltage of the doping concentration adjusting means of third silicon epitaxy layer, the second silicon epitaxy layer forms an internal RESURF structures and for reducing the surface field of drift region, the reliability for reducing hot carrier's effect, improving the radio frequency LDMOS device；First silicon epitaxy layer can make drain terminal junction breakdown voltage maintain or improve.The invention discloses a kind of manufacturing methods of radio frequency LDMOS device.The present invention can reduce the source and drain parasitic capacitance of device, reduce source and drain conducting resistance, increase driving current, improve the radiofrequency characteristics of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly to a kind of radio frequency LDMOS device；The present invention is also
It is related to a kind of manufacturing method of radio frequency LDMOS device.
Background technology
Radio frequency lateral fet（RF LDMOS）It is the common device applied to RF base station and broadcasting station.High strike
Wear voltage, low source and drain conducting resistance（RDSON）With low source and drain parasitic capacitance（Coss）It is the prerequisite device of RF LDMOS institutes
Characteristic.As shown in Figure 1, be the structural schematic diagram of existing radio frequency LDMOS device, by taking N-type device as an example, existing radio frequency LDMOS devices
Part includes：The silicon substrate 101 of p-type heavy doping, that is, P+ doping, the doping concentration of silicon substrate 101 are more than 1e20cm-3；P-type is lightly doped
Silicon epitaxy layer 102, the doping concentration and thickness of silicon epitaxy layer 102 depend on the drain terminal operating voltage of device, drain terminal work electricity
Pressure is higher, and the doping of silicon epitaxy layer 102 is lower, thickness is thicker；N-type drift region 103 is formed in silicon epitaxy layer 102；P-type is adulterated
Channel region 104, channel region 104 and drift region 103 are adjacent in the horizontal；Gate dielectric layer 107 and polysilicon gate 108；N-type weight
Doping is the source region 105 of N+ doping, drain region 106；It is formed with metal on the surface of source region 105, drain region 106 and polysilicon gate 108
Silicide 112；Shield dielectric layer 109 and faraday shield layer（G-shield）110, it is covered in the drain terminal of polysilicon gate 108
On side and top surface；Deep contact hole 111 is made of the metal such as tungsten being filled in deep trouth, and deep trouth passes through source region 105, channel region
It 104 and silicon epitaxy layer 102 and enters in silicon substrate 101, deep contact hole 111 is by source region 105, channel region 104, silicon epitaxy layer
102 and silicon substrate 101 be electrically connected.
In order to reduce the conducting resistance of device most possibly and increase the driving current of device, drift need to be increased as much as possible
The doping concentration in area 103 is moved, and high-breakdown-voltage and low parasitic capacitance require the concentration of drift region 103 cannot be too high.It is existing
RF LDMOS devices cover layer 110 using metal Faraday, and metal Faraday covers the part drift that layer 110 is placed on channel terminal
A surface RESURF (Reduced Surface Field reduce surface field) structure is formed in area 103, utilizes metal farad
The RESURF effects that shielded layer 110 generates reduce surface field, improve device reliability.But depend merely on G-shield be difficult by
103 concentration of drift region of RF LDMOS devices is increased to high level because the surface field at 108 edge of polysilicon gate still compared with
By force, it is easier to that hot carrier's effect occurs.
Invention content
Technical problem to be solved by the invention is to provide a kind of radio frequency LDMOS device, the source and drain that can reduce device is parasitic
Capacitance reduces source and drain conducting resistance, increases driving current, improves the radiofrequency characteristics of device.For this purpose, the present invention also provides one kind to penetrate
The manufacturing method of frequency LDMOS device.
In order to solve the above technical problems, radio frequency LDMOS device provided by the invention includes：
The silicon substrate of first conduction type heavy doping.
The silicon epitaxy layer of first conduction type doping, the silicon epitaxy layer is by being sequentially formed in the of the surface of silicon
One silicon epitaxy layer, the second silicon epitaxy layer and third silicon epitaxy layer are formed by stacking.
District's groups are injected in drift region by the second conductive type ion being formed in the selection area of the third silicon epitaxy layer
At the top surface of the drift region is less than with the depth of equal, the described drift region of the top surface of third silicon epitaxy layer
The thickness of the third silicon epitaxy layer.
Channel region injects district's groups by the first conductive type ion being formed in the selection area of the third silicon epitaxy layer
At the channel region and the drift region are adjacent in the horizontal, the top surface of the channel region and the third silicon epitaxy
The depth of equal, the described channel region of top surface of layer is less than or equal to the depth of the drift region.
Polysilicon gate is formed in above the channel region, and the polysilicon gate and the third silicon epitaxy zone isolation have
Gate dielectric layer, channel region described in the polysilicon gate covering part simultaneously extends to above the drift region, by the polysilicon gate
The channel region surface of covering is used to form raceway groove.
Source region is made of the second conduction type heavily doped region being formed in the channel region, the source region and described more
First side autoregistration of crystal silicon grid.
Drain region is made of the second conduction type heavily doped region being formed in the drift region, the drain region and described more
The second side of crystal silicon grid is separated by a lateral distance.
Faraday shield layer, the faraday shield layer cover side and top surface and the institute of the second side of the polysilicon gate
The second side for stating faraday shield layer extends to above the drift region；Between the faraday shield layer and the polysilicon gate
And all isolation has shielding dielectric layer between the faraday shield layer and the drift region.
Deep contact hole is made of the metal being filled in deep trouth, and the deep trouth passes through the source region, the channel region and institute
It states third silicon epitaxy layer and enters in the silicon substrate, the depth contact hole is by the source region, the channel region, the third
Silicon epitaxy layer and silicon substrate electrical connection.
The doping concentration of second silicon epitaxy layer is more than the doping concentration of first silicon epitaxy layer, outside second silicon
The doping concentration for prolonging layer is more than the doping concentration of the third silicon epitaxy layer.
The channel region and the drift region are all located in the third silicon epitaxy layer, by adjusting the third silicon epitaxy
The doping concentration of layer adjusts the conducting resistance and drain terminal junction breakdown voltage of radio frequency LDMOS device, the drain terminal junction breakdown voltage
For the breakdown voltage of the PN junction between the drift region and the silicon epitaxy layer in the drain region；The third silicon epitaxy layer
The conducting resistance of lower, the described radio frequency LDMOS device of doping concentration is lower, the drain terminal junction breakdown voltage is higher.
Second silicon epitaxy layer is located at below the channel region and the drift region, and second silicon epitaxy layer is formed
One internal RESURF structures and for reducing the surface field of the drift region, reduce hot carrier's effect, improve the radio frequency
The reliability of LDMOS device, second silicon epitaxy layer and the faraday shield layer constitute double RESURF structures；Described second
The thickness of silicon epitaxy layer gets over Bao Yuehao；Ensureing the impurity of second silicon epitaxy layer not to the third silicon epitaxy layer
Doping has an impact before not increasing the conducting resistance of the radio frequency LDMOS device and reducing the drain terminal junction breakdown voltage
It puts, the thickness of higher, the described third silicon epitaxy layer of doping concentration of second silicon epitaxy layer is thinner, the table of the drift region
The reliability of lower, the described radio frequency LDMOS device of face electric field is higher.
First silicon epitaxy layer is used to provide after crossing over second silicon epitaxy layer for the depletion region of the drift region
Further expansive space makes the drain terminal junction breakdown voltage maintain or improve.
A further improvement is that the doping concentration of second silicon epitaxy layer is the doping concentration of the third silicon epitaxy layer
2 times~10 times.
A further improvement is that the thickness of the third silicon epitaxy layer is 1 micron~2 microns.
A further improvement is that first silicon epitaxy layer and the third silicon epitaxy layer are all adulterated using extension in place；
Second silicon epitaxy layer is adulterated in place using extension or second silicon epitaxy layer uses and delays ion implantation doping outside.
A further improvement is that when second silicon epitaxy layer delays ion implantation doping and first conduction using outer
When type is p-type, the impurity of the ion implantation doping of second silicon epitaxy layer is indium；When second silicon epitaxy layer is using outer
When to delay ion implantation doping and first conduction type be N-type, the ion implantation doping of second silicon epitaxy layer it is miscellaneous
Matter is antimony.
A further improvement is that the radio frequency LDMOS device is N-type device, first conduction type is p-type, described
Second conduction type is N-type；Alternatively, the radio frequency LDMOS device is P-type device, first conduction type is N-type, described
Second conduction type is p-type.
In order to solve the above technical problems, the method for manufacture radio frequency LDMOS device provided by the invention includes the following steps：
Step 1: carrying out being epitaxially-formed first silicon epitaxy layer on the silicon substrate；First silicon epitaxy
Layer is adulterated in place using extension.
Step 2: being doped to form described second to first silicon epitaxy layer surface using full sheet ion implantation technology
Silicon epitaxy layer.
Step 3: the implanted dopant to second silicon epitaxy layer carries out rapid thermal annealing.
Step 4: carrying out being epitaxially-formed the third silicon epitaxy layer on second silicon epitaxy layer；The third
Silicon epitaxy layer is adulterated in place using extension.
Step 5: defining the forming region of the drift region using photoetching process, the second conductive type ion note is carried out
Enter to form the drift region.
Step 6: growing the gate dielectric layer on the third silicon epitaxy layer surface for being formed with the drift region.
Step 7: in the gate dielectric layer surface deposition polysilicon.
Step 8: carrying out first time etching to the polysilicon using lithographic etch process, this is etched for the first time by source
The polysilicon of side removes, and the boundary after the first time etching is the first side of the polysilicon gate being subsequently formed.
Step 9: the forming region of the channel region is defined using photoetching process, the formation Qu Hesuo of the channel region
The first side autoregistration of polysilicon gate is stated, the first conductive type ion is carried out and injects to form the channel region.
Step 10: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate.
Step 11: in the silicon substrate front deposition dielectric layer, the shielding dielectric layer covers the polysilicon
The silicon epitaxy layer surface outside the top surface of grid and side surface and the polysilicon gate.
Step 12: depositing faraday shield layer in the shielding dielectric layer surface.
Step 13: being performed etching to the faraday shield layer using dry etch process.
It injects to form the source region and the drain region Step 14: carrying out the second conduction type heavy doping ion, the source
The first side autoregistration in area and the polysilicon gate；The second side of the drain region and the polysilicon gate is separated by a lateral distance.
Step 15: deposit metal silicide and annealed alloy, the metal silicide is formed in the source region, described
Drain region and the polycrystalline silicon gate surface not covered by the faraday shield layer.
Step 16: carrying out the deep etching, metal is filled in the deep trouth and forms the deep contact hole.
In order to solve the above technical problems, the method for manufacture radio frequency LDMOS device provided by the invention includes the following steps：
Step 1: carrying out being epitaxially-formed first silicon epitaxy layer on the silicon substrate；First silicon epitaxy
Layer is adulterated in place using extension.
Step 2: being doped to form described second to first silicon epitaxy layer surface using full sheet ion implantation technology
Silicon epitaxy layer.
Step 3: the implanted dopant to second silicon epitaxy layer carries out rapid thermal annealing.
Step 4: carrying out being epitaxially-formed the third silicon epitaxy layer on second silicon epitaxy layer；The third
Silicon epitaxy layer is adulterated in place using extension.
Step 5: growing the gate dielectric layer on third silicon epitaxy layer surface.
Step 6: in the gate dielectric layer surface deposition polysilicon.
Step 7: carrying out first time etching to the polysilicon using lithographic etch process, this is etched for the first time by source
The polysilicon of side removes, and the boundary after the first time etching is the first side of the polysilicon gate being subsequently formed.
Step 8: the forming region of the channel region is defined using photoetching process, the formation Qu Hesuo of the channel region
The first side autoregistration of polysilicon gate is stated, the first conductive type ion is carried out and injects to form the channel region.
Step 9: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate.
Step 10: defining the forming region of the drift region using photoetching process, the second conductive type ion note is carried out
Enter to form the drift region.
Step 11: in the silicon substrate front deposition dielectric layer, the shielding dielectric layer covers the polysilicon
The silicon epitaxy layer surface outside the top surface of grid and side surface and the polysilicon gate.
Step 12: depositing faraday shield layer in the shielding dielectric layer surface.
Step 13: being performed etching to the faraday shield layer using dry etch process.
It injects to form the source region and the drain region Step 14: carrying out the second conduction type heavy doping ion, the source
The first side autoregistration in area and the polysilicon gate；The second side of the drain region and the polysilicon gate is separated by a lateral distance.
Step 15: deposit metal silicide and annealed alloy, the metal silicide is formed in the source region, described
Drain region and the polycrystalline silicon gate surface not covered by the faraday shield layer.
Step 16: carrying out the deep etching, metal is filled in the deep trouth and forms the deep contact hole.
A further improvement is that the doping concentration of second silicon epitaxy layer is the doping concentration of the third silicon epitaxy layer
2 times~10 times；The thickness of the third silicon epitaxy layer is 1 micron~2 microns.
A further improvement is that the radio frequency LDMOS device is N-type device, first conduction type is p-type, described
Second conduction type is N-type, and the impurity for forming the full sheet ion implanting of second silicon epitaxy layer is indium；Alternatively, the radio frequency
LDMOS device is P-type device, and first conduction type is N-type, and second conduction type is p-type, forms second silicon
The impurity of the full sheet ion implanting of epitaxial layer is antimony.
RF LDMOS devices of the present invention replace the epitaxial layer of existing Uniform Doped using the epitaxial layer of sandwich structure, on
Lower layer i.e. the first silicon epitaxy layer and third silicon epitaxy layer are all low-doped epitaxial layer, middle layer i.e. the second silicon epitaxy layer be then compared with
High concentration can not influence device drain terminal by the setting of the doping concentration of thickness and intermediate epitaxial layers to upper layer epitaxial layer
Under the premise of junction breakdown voltage and device on-resistance, higher concentration intermediate epitaxial layers can form internal RESURF structures and real
Now there are preferable RESURF effects to drift region, is constituted together with the surface RESURF structures that faraday shield layer is formed double
RESURF structures, by effect faraday shield layer to the surface RESURF effects and intermediate epitaxial layers of drift region to drift region
Internal RESURF effects, can be so that drift region surface field homogenization, increases the breakdown voltage of device, and reduction drift region is especially
The electric field strength of the drift region of trench edges, so as to reduce hot carrier's effect, improve device reliability.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the structural schematic diagram of existing radio frequency LDMOS device；
Fig. 2 is the structural schematic diagram of radio frequency LDMOS device of the embodiment of the present invention；
Fig. 3 A- Fig. 3 K are the structural schematic diagrams of radio frequency LDMOS device in each step of one method of the embodiment of the present invention.
Specific implementation mode
As shown in Fig. 2, being the structural schematic diagram of radio frequency LDMOS device of the embodiment of the present invention；Radio frequency of the embodiment of the present invention
LDMOS device includes：
The silicon substrate 1 of first conduction type heavy doping.Preferably, the doping concentration of the silicon substrate 1 is more than 1e20cm-3。
The silicon epitaxy layer of first conduction type doping, the silicon epitaxy layer is by being sequentially formed in 1 surface of the silicon substrate
First silicon epitaxy layer 2, the second silicon epitaxy layer 3 and third silicon epitaxy layer 4 are formed by stacking.
Drift region 5, by the second conductive type ion injection region being formed in the selection area of the third silicon epitaxy layer 4
Composition, the top surface of the drift region 5 is equal with the top surface of the third silicon epitaxy layer 4, the depth of the drift region 5
Less than the thickness of the third silicon epitaxy layer 4.
Channel region 6, by the first conductive type ion injection region being formed in the selection area of the third silicon epitaxy layer 4
Composition, the channel region 6 and the drift region 5 are adjacent in the horizontal, the top surface of the channel region 6 and the third silicon
The top surface of epitaxial layer 4 is equal, the depth of the channel region 6 is less than or equal to the depth of the drift region 5.
Polysilicon gate 10 is formed in 6 top of the channel region, between the polysilicon gate 10 and the third silicon epitaxy layer 4
Isolation has gate dielectric layer 9, and preferably, the material of gate dielectric layer 5 is silica.Raceway groove described in 10 covering part of the polysilicon gate
Area 6 simultaneously extends to 5 top of the drift region, and raceway groove is used to form by 6 surface of the channel region that the polysilicon gate 10 covers.
Source region 8 is made of the second conduction type heavily doped region being formed in the channel region 6, the source region 8 and described
First side autoregistration of polysilicon gate 10.
Drain region 7 is made of the second conduction type heavily doped region being formed in the drift region 5, the drain region 7 and described
The second side of polysilicon gate 10 is separated by a lateral distance.
Faraday shield layer 13, the faraday shield layer 13 cover the side and top of the second side of the polysilicon gate 10
The second side of face and the faraday shield layer 13 extends to 5 top of the drift region；The faraday shield layer 13 and described
All isolation has shielding dielectric layer 11 between polysilicon gate 10 and between the faraday shield layer 13 and the drift region 5.This
The shielding dielectric layer 13 and metal silicide 12 in inventive embodiments on the top surface of the polysilicon gate 8 contact.Compared with
Good to be, the material of the shielding dielectric layer 13 is silica, silicon nitride or silicon oxynitride.
Deep contact hole 14 is made of the metal being filled in deep trouth, and the deep trouth passes through the source region 8, the channel region 6
With the third silicon epitaxy layer 4 and enter in the silicon substrate 1, the depth contact hole 14 is by the source region 8, the channel region
6, the third silicon epitaxy layer 4 and the silicon substrate 1 are electrically connected.
The doping concentration of second silicon epitaxy layer 3 is more than the doping concentration of first silicon epitaxy layer 2, second silicon
The doping concentration of epitaxial layer 3 is more than the doping concentration of the third silicon epitaxy layer 4, the first silicon epitaxy described in the embodiment of the present invention
Layer 2 is identical with the doping concentration of the third silicon epitaxy layer 4.
The channel region 6 and the drift region 5 are all located in the third silicon epitaxy layer 4, by adjusting the third silicon
The doping concentration of epitaxial layer 4 adjusts the conducting resistance and drain terminal junction breakdown voltage of radio frequency LDMOS device, the drain terminal junction breakdown
Voltage is the breakdown voltage of the PN junction between the drift region 5 and the silicon epitaxy layer in the drain region 7；Outside the third silicon
The conducting resistance of prolonging lower, the described radio frequency LDMOS device of doping concentration of layer 4 is lower, the drain terminal junction breakdown voltage is higher.
Second silicon epitaxy layer 3 is located at 5 lower section of the channel region 6 and the drift region, second silicon epitaxy layer 3
Form an internal RESURF structures and for reducing described in the surface field of the drift region 5, reduction hot carrier's effect, raising
The reliability of radio frequency LDMOS device, second silicon epitaxy layer 3 and the faraday shield layer 13 constitute double RESURF structures；
The thickness of second silicon epitaxy layer 3 gets over Bao Yuehao；Ensureing the impurity of second silicon epitaxy layer 3 not to the third
The doping of silicon epitaxy layer 4 has an impact not increase the conducting resistance of the radio frequency LDMOS device and reduces the drain terminal knot
Under the premise of breakdown voltage, the doping concentration of second silicon epitaxy layer 3 is higher, the thickness of the third silicon epitaxy layer 4 is thinner,
The reliability of lower, the described radio frequency LDMOS device of surface field of the drift region 5 is higher.Preferably, second silicon epitaxy
The doping concentration of layer 3 is 2 times~10 times of the doping concentration of the third silicon epitaxy layer 4.The thickness of the third silicon epitaxy layer 4
It is 1 micron~2 microns.
First silicon epitaxy layer 2 is used to carry after crossing over second silicon epitaxy layer 3 for the depletion region of the drift region 5
For further expansive space, the drain terminal junction breakdown voltage is made to maintain or improve.
First silicon epitaxy layer 2 and the third silicon epitaxy layer 4 are all adulterated using extension in place；Second silicon epitaxy
Layer 3 is adulterated in place using extension or second silicon epitaxy layer 3 uses and delays ion implantation doping outside.When second silicon
Epitaxial layer 3 use it is outer delay ion implantation doping and when first conduction type is N-type, second silicon epitaxy layer 3 from
The impurity of son injection doping is antimony.
The structure of radio frequency LDMOS device of the embodiment of the present invention is suitable for N-type device, is also applied for P-type device.When this hair
When bright embodiment radio frequency LDMOS device is N-type device, first conduction type is p-type, and second conduction type is N-type,
When second silicon epitaxy layer 3 using ion implantation doping is delayed outside, the ion implantation doping of second silicon epitaxy layer 3
Impurity is indium, implantation dosage 1e12cm-3~1e13cm-3.Alternatively, when radio frequency LDMOS device of the embodiment of the present invention is p-type device
When part, first conduction type is N-type, and second conduction type is p-type, when second silicon epitaxy layer 3 uses extension
Afterwards when ion implantation doping, the impurity of the ion implantation doping of second silicon epitaxy layer 3 is antimony.
It is the structural representation of radio frequency LDMOS device in each step of one method of the embodiment of the present invention as shown in Fig. 3 A to Fig. 3 K
Figure, one method of the embodiment of the present invention manufacture radio frequency for manufacturing present example device as shown in Figure 2, the embodiment of the present invention one
The method of LDMOS device includes the following steps：
Step 1: as shown in Figure 3A, carrying out being epitaxially-formed first silicon epitaxy layer 2 on the silicon substrate 1；Institute
The first silicon epitaxy layer 2 is stated to adulterate in place using extension.
Step 2: as shown in Figure 3B, being doped to 2 surface of the first silicon epitaxy layer using full sheet ion implantation technology
Form second silicon epitaxy layer 3.
Step 3: the implanted dopant to second silicon epitaxy layer 3 carries out rapid thermal annealing, the temperature of the rapid thermal annealing
More than 1000 DEG C, the time is more than 10 seconds.
Step 4: as shown in Figure 3 C, carrying out being epitaxially-formed the third silicon epitaxy on second silicon epitaxy layer 3
Layer 4；The third silicon epitaxy layer 4 is adulterated in place using extension.Preferably, the doping concentration of second silicon epitaxy layer 3 is institute
State the doping concentration of third silicon epitaxy layer 42 times~10 times；The thickness of the third silicon epitaxy layer 4 is 1 micron~2 microns.
Step 5: as shown in Figure 3D, the forming region of the drift region 5 is defined using photoetching process, carries out second and lead
Electric types of ion injects to form the drift region 5.
Step 6: as shown in FIGURE 3 E, described in 4 surface of the third silicon epitaxy layer growth for being formed with the drift region 5
Gate dielectric layer 9.
Step 7: as shown in FIGURE 3 E, in 9 surface deposition polysilicon of the gate dielectric layer.
Step 8: as shown in FIGURE 3 E, carrying out first time etching to the polysilicon using lithographic etch process, this is for the first time
Etching removes the polysilicon of source side, and the boundary after the first time etching is the polysilicon gate being subsequently formed
10 the first side.
Step 9: as illustrated in Figure 3 F, the forming region of the channel region 6, the channel region 6 are defined using photoetching process
Formation area and the polysilicon gate 10 the first side autoregistration, carry out the first conductive type ion inject to form the channel region
6。
Step 10: as shown in Figure 3 G, being carried out described in second of etching formation to the polysilicon using lithographic etch process
Polysilicon gate 10.
As shown in figure 3h, it carries out the second conduction type heavy doping ion to inject to form the source region 8 and the drain region 7, institute
State the first side autoregistration of source region 8 and the polysilicon gate 10；The second side of the drain region 7 and the polysilicon gate 10 is separated by one
Lateral distance.
As shown in fig. 31, deposit metal silicide 12 and annealed alloy, the metal silicide 12 are formed in the source
Area 8, the drain region 7 and 10 surface of the polysilicon gate not covered by the faraday shield layer 13.
The formation process of source region 9 described above, the drain region 7 and the metal silicide 12 is located in subsequent screen
It covers before dielectric layer 11 is formed and carries out, the formation process of the source region 9, the drain region 7 and the metal silicide 12 also can
It places after the shielding dielectric layer 11 is formed and carries out, i.e., form the source region 9 and the drain region in subsequent step 14
7, the metal silicide 12 is formed in subsequent step 15.
Step 11: as shown in figure 3j, in the positive deposition dielectric layer 11 of the silicon substrate 1, the shielding dielectric layer
11 cover the top surface of the polysilicon gate 10 and the silicon epitaxy layer surface outside side surface and the polysilicon gate 10.
Step 12: as shown in Fig. 3 K, in the 11 surface deposition faraday shield layer 13 of shielding dielectric layer.
Step 13: as shown in Fig. 3 K, the faraday shield layer 13 is performed etching using dry etch process.
It injects to form the source region 8 and the drain region 7 Step 14: carrying out the second conduction type heavy doping ion, it is described
First side autoregistration of source region 8 and the polysilicon gate 10；The second side of the drain region 7 and the polysilicon gate 10 is separated by a cross
To distance.
Step 15: deposit metal silicide 12 and annealed alloy, the metal silicide 12 are formed in the source region
8, the drain region 7 and 10 surface of the polysilicon gate not covered by the faraday shield layer 13.
Step 16: as shown in Fig. 2, carrying out the deep etching, filling metal forms the depth and connects in the deep trouth
Contact hole 14.
The structure of the radio frequency LDMOS device of the embodiment of the present invention of one method of embodiment of the present invention manufacture is suitable for N-type device
Part is also applied for P-type device.When radio frequency LDMOS device be N-type device when, first conduction type be p-type, described second
Conduction type is N-type, when second silicon epitaxy layer 3 using ion implantation doping is delayed outside, second silicon epitaxy layer 3
The impurity of ion implantation doping is indium, implantation dosage 1e12cm-3~1e13cm-3.Alternatively, when radio frequency LDMOS device is p-type
When device, first conduction type is N-type, and second conduction type is p-type, when second silicon epitaxy layer 3 is using outer
When delaying ion implantation doping, the impurity of the ion implantation doping of second silicon epitaxy layer 3 is antimony.
Two method of the embodiment of the present invention is also used for manufacturing device of the embodiment of the present invention as shown in Figure 2, the embodiment of the present invention
It is the drift region 5 to be formed using photoetching process rather than self-registered technology, and be in one method in two method of the embodiment of the present invention
The drift region 5 is formed using self-registered technology, as shown in Fig. 2, the manufacturing method of two radio frequency LDMOS device of the embodiment of the present invention
Include the following steps：
Step 1: carrying out being epitaxially-formed first silicon epitaxy layer 2 on the silicon substrate 1；Outside first silicon
Prolong layer 2 to adulterate in place using extension.
Step 2: being doped to form described to 2 surface of the first silicon epitaxy layer using full sheet ion implantation technology
Two silicon epitaxy layers 3.
Step 3: the implanted dopant to second silicon epitaxy layer 3 carries out rapid thermal annealing.
Step 4: carrying out being epitaxially-formed the third silicon epitaxy layer 4 on second silicon epitaxy layer 3；Described
Three silicon epitaxy layers 4 are adulterated in place using extension.The doping concentration of second silicon epitaxy layer 3 is the third silicon epitaxy layer 4
2 times of doping concentration~10 times；The thickness of the third silicon epitaxy layer 4 is 1 micron~2 microns.
Step 5: growing the gate dielectric layer 9 on 4 surface of third silicon epitaxy layer.
Step 6: in 9 surface deposition polysilicon of the gate dielectric layer.
Step 7: carrying out first time etching to the polysilicon using lithographic etch process, this is etched for the first time by source
The polysilicon of side removes, and the boundary after the first time etching is the first of the polysilicon gate 10 being subsequently formed
Side.
Step 8: define the forming region of the channel region 6 using photoetching process, the formation area of the channel region 6 and
First side autoregistration of the polysilicon gate 10 carries out the first conductive type ion and injects to form the channel region 6.
Step 9: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate 10.
Step 10: defining the forming region of the drift region 5 using photoetching process, the second conductive type ion note is carried out
Enter to form the drift region 5.
It carries out the second conduction type heavy doping ion to inject to form the source region 8 and the drain region 7, the source region 8 and institute
State the first side autoregistration of polysilicon gate 10；The second side of the drain region 7 and the polysilicon gate 10 is separated by a lateral distance.
Metal silicide 12 and annealed alloy are deposited, the metal silicide 12 is formed in the source region 8, the drain region
7 and 10 surface of the polysilicon gate that is not covered by the faraday shield layer 13.
The formation process of source region 9 described above, the drain region 7 and the metal silicide 12 is located in subsequent screen
It covers before dielectric layer 11 is formed and carries out, the formation process of the source region 9, the drain region 7 and the metal silicide 12 also can
It places after the shielding dielectric layer 11 is formed and carries out, i.e., form the source region 9 and the drain region in subsequent step 14
7, the metal silicide 12 is formed in subsequent step 15.
Step 11: in the positive deposition dielectric layer 11 of the silicon substrate 1, the shielding dielectric layer 11 covers described more
The silicon epitaxy layer surface outside the top surface of crystal silicon grid 10 and side surface and the polysilicon gate 10.
Step 12: in the 11 surface deposition faraday shield layer 13 of shielding dielectric layer.
Step 13: being performed etching to the faraday shield layer 13 using dry etch process.
It injects to form the source region 8 and the drain region 7 Step 14: carrying out the second conduction type heavy doping ion, it is described
First side autoregistration of source region 8 and the polysilicon gate 10；The second side of the drain region 7 and the polysilicon gate 10 is separated by a cross
To distance.
Step 15: deposit metal silicide 12 and annealed alloy, the metal silicide 12 are formed in the source region
8, the drain region 7 and 10 surface of the polysilicon gate not covered by the faraday shield layer 13.
Step 16: carrying out the deep etching, metal is filled in the deep trouth and forms the deep contact hole 14.
The structure of the radio frequency LDMOS device of the embodiment of the present invention of two method of embodiment of the present invention manufacture is suitable for N-type device
Part is also applied for P-type device.When radio frequency LDMOS device be N-type device when, first conduction type be p-type, described second
Conduction type is N-type, when second silicon epitaxy layer 3 using ion implantation doping is delayed outside, second silicon epitaxy layer 3
The impurity of ion implantation doping is indium, implantation dosage 1e12cm-3~1e13cm-3.Alternatively, when radio frequency LDMOS device is p-type
When device, first conduction type is N-type, and second conduction type is p-type, when second silicon epitaxy layer 3 is using outer
When delaying ion implantation doping, the impurity of the ion implantation doping of second silicon epitaxy layer 3 is antimony.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (7)
1. a kind of radio frequency LDMOS device, which is characterized in that including：
The silicon substrate of first conduction type heavy doping；
The silicon epitaxy layer of first conduction type doping, the silicon epitaxy layer is by being sequentially formed in the first silicon of the surface of silicon
Epitaxial layer, the second silicon epitaxy layer and third silicon epitaxy layer are formed by stacking；
Drift region is made of the second conductive type ion injection region being formed in the selection area of the third silicon epitaxy layer,
The top surface of the drift region is less than described with the depth of equal, the described drift region of the top surface of third silicon epitaxy layer
The thickness of third silicon epitaxy layer；
Channel region is made of the first conductive type ion injection region being formed in the selection area of the third silicon epitaxy layer,
The channel region and the drift region are adjacent in the horizontal, the top surface of the channel region and the third silicon epitaxy layer
The depth of equal, the described channel region of top surface is less than or equal to the depth of the drift region；
Polysilicon gate is formed in above the channel region, and the polysilicon gate and the third silicon epitaxy zone isolation have grid Jie
Matter layer, channel region described in the polysilicon gate covering part are simultaneously extended to above the drift region, are covered by the polysilicon gate
The channel region surface be used to form raceway groove；
Source region is made of, the source region and the polysilicon the second conduction type heavily doped region being formed in the channel region
First side autoregistration of grid；
Drain region is made of, the drain region and the polysilicon the second conduction type heavily doped region being formed in the drift region
The second side of grid is separated by a lateral distance；
Faraday shield layer, the faraday shield layer cover side and top surface and the method for the second side of the polysilicon gate
The second side of shielded layer is drawn to extend to above the drift region；Between the faraday shield layer and the polysilicon gate and
All isolation has shielding dielectric layer between the faraday shield layer and the drift region；
Deep contact hole is made of the metal being filled in deep trouth, and the deep trouth passes through the source region, the channel region and described the
Three silicon epitaxy layers simultaneously enter in the silicon substrate, and the depth contact hole will be outside the source region, the channel region, the third silicon
Prolong layer and silicon substrate electrical connection；
The doping concentration of second silicon epitaxy layer is more than the doping concentration of first silicon epitaxy layer, second silicon epitaxy layer
Doping concentration be more than the third silicon epitaxy layer doping concentration；
The channel region and the drift region are all located in the third silicon epitaxy layer, by adjusting the third silicon epitaxy layer
Doping concentration adjust radio frequency LDMOS device conducting resistance and drain terminal junction breakdown voltage, the drain terminal junction breakdown voltage be by
The breakdown voltage of PN junction between the drift region and the silicon epitaxy layer in the nearly drain region；The doping of the third silicon epitaxy layer
The conducting resistance of lower, the described radio frequency LDMOS device of concentration is lower, the drain terminal junction breakdown voltage is higher；
Second silicon epitaxy layer is located at below the channel region and the drift region, and second silicon epitaxy layer forms one
Interior RESURF structures and for reducing the surface field of the drift region, reduce hot carrier's effect, improve the radio frequency LDMOS
The reliability of device, second silicon epitaxy layer and the faraday shield layer constitute double RESURF structures；Outside second silicon
The thickness for prolonging layer gets over Bao Yuehao；In the impurity not doping to the third silicon epitaxy layer for ensureing second silicon epitaxy layer
Have an impact the conducting resistance for not increasing the radio frequency LDMOS device and the premise for reducing the drain terminal junction breakdown voltage
Under, the thickness of higher, the described third silicon epitaxy layer of doping concentration of second silicon epitaxy layer is thinner, the surface of the drift region
The reliability of lower, the described radio frequency LDMOS device of electric field is higher；
First silicon epitaxy layer is used to provide into one after crossing over second silicon epitaxy layer for the depletion region of the drift region
The expansive space of step makes the drain terminal junction breakdown voltage maintain or improve；
The doping concentration of second silicon epitaxy layer is 2 times~10 times of the doping concentration of the third silicon epitaxy layer；
The thickness of the third silicon epitaxy layer is 1 micron~2 microns.
2. radio frequency LDMOS device as described in claim 1, it is characterised in that：Outside first silicon epitaxy layer and the third silicon
Prolong layer all to adulterate in place using extension；Second silicon epitaxy layer is adulterated in place using extension or second silicon epitaxy layer
Using delaying ion implantation doping outside.
3. radio frequency LDMOS device as claimed in claim 2, it is characterised in that：When second silicon epitaxy layer using outside delay from
When son injection is adulterated and first conduction type is p-type, the impurity of the ion implantation doping of second silicon epitaxy layer is indium；
When second silicon epitaxy layer use it is outer delay ion implantation doping and when first conduction type is N-type, second silicon
The impurity of the ion implantation doping of epitaxial layer is antimony.
4. radio frequency LDMOS device as described in claim 1, it is characterised in that：The radio frequency LDMOS device is N-type device, described
First conduction type is p-type, and second conduction type is N-type；Alternatively, the radio frequency LDMOS device is P-type device, it is described
First conduction type is N-type, and second conduction type is p-type.
5. a kind of method of manufacture radio frequency LDMOS device as described in claim 1, which is characterized in that include the following steps：
Step 1: carrying out being epitaxially-formed first silicon epitaxy layer on the silicon substrate；First silicon epitaxy layer is adopted
It is adulterated in place with extension；
Step 2: being doped to be formed outside second silicon to first silicon epitaxy layer surface using full sheet ion implantation technology
Prolong layer；
Step 3: the implanted dopant to second silicon epitaxy layer carries out rapid thermal annealing；
Step 4: carrying out being epitaxially-formed the third silicon epitaxy layer on second silicon epitaxy layer；Outside the third silicon
Prolong layer to adulterate in place using extension；
Step 5: defining the forming region of the drift region using photoetching process, carries out the second conductive type ion and inject shape
At the drift region；
Step 6: growing the gate dielectric layer on the third silicon epitaxy layer surface for being formed with the drift region；
Step 7: in the gate dielectric layer surface deposition polysilicon；
Step 8: carrying out first time etching to the polysilicon using lithographic etch process, this is etched for the first time by source side
Polysilicon removal, the boundary after first time etching is the first side of the polysilicon gate being subsequently formed；
Step 9: define the forming region of the channel region using photoetching process, the formation area of the channel region and described more
First side autoregistration of crystal silicon grid carries out the first conductive type ion and injects to form the channel region；
Step 10: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate；
Step 11: in the silicon substrate front deposition dielectric layer, the shielding dielectric layer covers the polysilicon gate
The silicon epitaxy layer surface outside top surface and side surface and the polysilicon gate；
Step 12: depositing faraday shield layer in the shielding dielectric layer surface；
Step 13: being performed etching to the faraday shield layer using dry etch process；
Step 14: carry out the second conduction type heavy doping ion inject to form the source region and the drain region, the source region and
First side autoregistration of the polysilicon gate；The second side of the drain region and the polysilicon gate is separated by a lateral distance；
Step 15: deposit metal silicide and annealed alloy, the metal silicide are formed in the source region, the drain region
The polycrystalline silicon gate surface not covered by the faraday shield layer；
Step 16: carrying out the deep etching, metal is filled in the deep trouth and forms the deep contact hole.
6. a kind of method of manufacture radio frequency LDMOS device as described in claim 1, which is characterized in that include the following steps：
Step 1: carrying out being epitaxially-formed first silicon epitaxy layer on the silicon substrate；First silicon epitaxy layer is adopted
It is adulterated in place with extension；
Step 2: being doped to be formed outside second silicon to first silicon epitaxy layer surface using full sheet ion implantation technology
Prolong layer；
Step 3: the implanted dopant to second silicon epitaxy layer carries out rapid thermal annealing；
Step 4: carrying out being epitaxially-formed the third silicon epitaxy layer on second silicon epitaxy layer；Outside the third silicon
Prolong layer to adulterate in place using extension；
Step 5: growing the gate dielectric layer on third silicon epitaxy layer surface；
Step 6: in the gate dielectric layer surface deposition polysilicon；
Step 7: carrying out first time etching to the polysilicon using lithographic etch process, this is etched for the first time by source side
Polysilicon removal, the boundary after first time etching is the first side of the polysilicon gate being subsequently formed；
Step 8: define the forming region of the channel region using photoetching process, the formation area of the channel region and described more
First side autoregistration of crystal silicon grid carries out the first conductive type ion and injects to form the channel region；
Step 9: carrying out second of etching to the polysilicon using lithographic etch process forms the polysilicon gate；
Step 10: defining the forming region of the drift region using photoetching process, carries out the second conductive type ion and inject shape
At the drift region；
Step 11: in the silicon substrate front deposition dielectric layer, the shielding dielectric layer covers the polysilicon gate
The silicon epitaxy layer surface outside top surface and side surface and the polysilicon gate；
Step 12: depositing faraday shield layer in the shielding dielectric layer surface；
Step 13: being performed etching to the faraday shield layer using dry etch process；
Step 14: carry out the second conduction type heavy doping ion inject to form the source region and the drain region, the source region and
First side autoregistration of the polysilicon gate；The second side of the drain region and the polysilicon gate is separated by a lateral distance；
Step 15: deposit metal silicide and annealed alloy, the metal silicide are formed in the source region, the drain region
The polycrystalline silicon gate surface not covered by the faraday shield layer；
Step 16: carrying out the deep etching, metal is filled in the deep trouth and forms the deep contact hole.
7. such as method described in claim 5 or 6, it is characterised in that：The radio frequency LDMOS device be N-type device, described first
Conduction type is p-type, and second conduction type is N-type, forms the impurity of the full sheet ion implanting of second silicon epitaxy layer
For indium；Alternatively, the radio frequency LDMOS device is P-type device, first conduction type is N-type, and second conduction type is
P-type, the impurity for forming the full sheet ion implanting of second silicon epitaxy layer are antimony.
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| CN101036231A (en) * | 2004-09-16 | 2007-09-12 | 飞兆半导体公司 | Enhanced RESURF HVPMOS device with stacked hetero-doping rim and gradual drift region |
| CN102376570A (en) * | 2010-08-19 | 2012-03-14 | 上海华虹Nec电子有限公司 | Manufacturing method of N-type radio frequency lateral double-diffused metal-oxide semiconductor (LDMOS) |
| CN103050541A (en) * | 2013-01-06 | 2013-04-17 | 上海华虹Nec电子有限公司 | Radio frequency LDMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof |
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| US8623732B2 (en) * | 2010-06-17 | 2014-01-07 | Freescale Semiconductor, Inc. | Methods of making laterally double diffused metal oxide semiconductor transistors having a reduced surface field structure |
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| CN101036231A (en) * | 2004-09-16 | 2007-09-12 | 飞兆半导体公司 | Enhanced RESURF HVPMOS device with stacked hetero-doping rim and gradual drift region |
| CN102376570A (en) * | 2010-08-19 | 2012-03-14 | 上海华虹Nec电子有限公司 | Manufacturing method of N-type radio frequency lateral double-diffused metal-oxide semiconductor (LDMOS) |
| CN103050541A (en) * | 2013-01-06 | 2013-04-17 | 上海华虹Nec电子有限公司 | Radio frequency LDMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof |
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