CN104682981A - Decoding board of ADS-B (automatic dependent surveillance broadcast) receiver - Google Patents

Abstract

The invention relates to a decoding board of an ADS-B (automatic dependent surveillance broadcast) receiver. A digital logic circuit of the decoding board comprises an AD (analog-digital) conversion module and an FPGA (field programmable gate array) digital logic module; a baseband digital processing part of the FPGA digital logic module mainly comprises an input signal synchronization module, a preamble detection module, a code bit pickup and confidence analysis module, a CRC (cyclic redundancy check) error detection and correction module and a ping-pong FIFO (first in and first out) access data module. With the adoption of a dynamic detection threshold method, a problem of high possibility of data loss in a decoding process is solved; compared with an original method, the data size after decoding is increased; by improving a logic time sequence in a baseband data processing process, a problem of non-aligned transmission of decoding data by accident is solved, and a situation of transmission data dislocation is eliminated; after a test, the decoding board is stable in working and reliable in performance.

Description

Automatic dependent surveillance broadcast ADS-B receiver decoding plate

Technical field

The present invention relates to airmanship, particularly a kind of Automatic dependent surveillance broadcast ADS-B receiver decoding plate.

Technical background

In the scientific research of digital communication product and in producing, the base-band digital processing section of ADS-B receiver decoding plate in the past, due to usually use when signal amplitude filtering controls segmented thresholding control current can the power bracket of processing signals, but segment threshold is often not easily chosen, and easily choose improper due to thresholding and cause signal correctly to resolve near segment threshold, thus the discontinuous problem of dropout is caused to occur.How to address this problem the problem just becoming those skilled in the art and will study and solve.

Summary of the invention

Object of the present invention is exactly for overcoming the deficiencies in the prior art, for the problem that obliterated data easy in the decode procedure of existing receiver decoding plate and data do not line up, a kind of design of Automatic dependent surveillance broadcast ADS-B receiver decoding plate is provided, by adopting detection of dynamic gate method, solve the problem of easy obliterated data in decode procedure, add decoded data volume compared with former method, by improving the logical sequence in base band data processing procedure, solve decoded data and transmit the problem do not lined up once in a while, eliminate the situation of transmission data dislocation, concrete technical scheme is, a kind of Automatic dependent surveillance broadcast ADS-B receiver decoding plate, its Digital Logical Circuits is by AD analog-to-digital conversion module, FPGA digital logic module forms, it is characterized in that: the base-band digital process of described FPGA part mainly comprises input signal synchronization module, detection of preamble module, code bit pickup and Confidence Analysis module, CRC check error-detection error-correction module, Ping-pong FIFO access data module, systems baseband digital process mainly comprises the following steps,

Step 1, signal amplitude filtering control, adopt detection of dynamic threshold algorithm, namely current detection threshold is dynamically determined according to the header reference power detected, this needs synchronous with thresholding for digital video signal time delay a period of time, this process eliminates some signal that segmented thresholding control method causes and correctly cannot resolve problem;

Step 2, detection of preamble, these needs extract effective impulse position, signal rising edge and signal trailing edge three information from the signal through step 1, and when detecting that 4 have a pulse at S mode preamble time interval, then carry out subsequent packet and resolve, examination criteria is

1) 4 pulses have the sequential of 0-1.0-3.5-4.5 μ s,

2) rising edge >=2,

3) all the other are effective impulse position VPP,

Then the steps such as the calculating of header reference power, power consistency check, 1um/3.5us/4.5us test, DF certification are carried out, header computing reference power again after these checkings, for resolving, in 13us simultaneously after header being detected, continue to find header, if this header is equally by above-mentioned all tests, its header reference value is compared with present header reference frame angle value, if this new signal 3dB at least higher than old signal amplitude, so abandon old signal, process new signal, otherwise, ignore new signal, continue the old signal of process;

The pickup of step 3, code bit and Confidence Analysis, adopt the correlation method of multi-parameter and multisampling to carry out code pickup and the Confidence Analysis of ADS-B;

Step 4, CRC check error-detection error-correction, after the judgement of the extraction of completion code position and confidence level, error-detection error-correction to be carried out to them, adopt the strong error-detection error-correction method of confidence declaration, first the judgement of wrong patterns is carried out, equal zero, error detection is passed through, and inerrancy occurs, no, carry out the corresponding syndrome of low confidence bit with 112 bit correction of storage inside to combine, then carry out whether with wrong patterns matching judgment, be, the error correction of corresponding bit bit reversal completes, no, error correction failure, jumps out error-detection error-correction module;

Step 5, Ping-pong FIFO access data, will eventually pass the data that verified stored in Ping-pong FIFO, by data that bus transfer calculates in the interruption of Fixed Time Interval.

The invention has the beneficial effects as follows and the per second data volume that is correctly decoded is added more than 20%, solve simultaneously originally in detection of preamble process near segment threshold data correctly cannot resolve thus cause the problem of loss of data, solve decoded data import FIFO into before the problem that do not line up of data, eliminate the situation of transmission data dislocation, after solving CRC check error bit simultaneously, the problem of data modification mistake.Working stability after tested, dependable performance.

Accompanying drawing explanation

Fig. 1 is hardware configuration sketch of the present invention.

Fig. 2 is the digital signal processing module of baseband portion of the present invention.

Fig. 3 is ADS-B message header of the present invention.

Fig. 4 is the strong error-detection error-correction handling process of confidence declaration of the present invention.

Embodiment

As shown in Figure 1,2,3, 4, a kind of Automatic dependent surveillance broadcast ADS-B receiver decoding plate, its Digital Logical Circuits is made up of AD analog-to-digital conversion module, FPGA digital logic module, it is characterized in that: the base-band digital process of described FPGA part mainly comprises input signal synchronization module, detection of preamble module, code bit pickup and Confidence Analysis module, CRC check error-detection error-correction module, Ping-pong FIFO access data module, systems baseband digital process mainly comprises the following steps

Step 1, signal amplitude filtering control, adopt detection of dynamic threshold algorithm, namely current detection threshold is dynamically determined according to the header reference power detected, this needs synchronous with thresholding for digital video signal time delay a period of time, this process eliminates some signal that segmented thresholding control method causes and correctly cannot resolve problem;

Step 2, detection of preamble, these needs extract effective impulse position, signal rising edge and signal trailing edge three information from the signal through step 1, and when detecting that 4 have a pulse at S mode preamble time interval, then carry out subsequent packet and resolve, examination criteria is

1) 4 pulses have the sequential of 0-1.0-3.5-4.5 μ s,

2) rising edge >=2,

3) all the other are effective impulse position VPP,

Then the steps such as the calculating of header reference power, power consistency check, 1um/3.5us/4.5us test, DF certification are carried out, header computing reference power again after these checkings, for resolving, in 13us simultaneously after header being detected, continue to find header, if this header is equally by above-mentioned all tests, its header reference value is compared with present header reference frame angle value, if this new signal 3dB at least higher than old signal amplitude, so abandon old signal, process new signal, otherwise, ignore new signal, continue the old signal of process;

The pickup of step 3, code bit and Confidence Analysis, the correlation method of multi-parameter and multisampling is adopted to carry out code pickup and the Confidence Analysis of ADS-B, the method makes full use of the reference power value in the information of 10 sampled values of each code bit and detection of preamble, determines code and confidence level by contrast;

Step 4, CRC check error-detection error-correction, after the judgement of the extraction of completion code position and confidence level, will carry out error-detection error-correction to them, adopt the strong error-detection error-correction method of confidence declaration, first carry out the judgement of wrong patterns, equal zero, error detection is passed through, and inerrancy occurs, no, carry out the corresponding syndrome of low confidence bit with 112 bit correction of storage inside to combine, carry out again whether with wrong patterns matching judgment, be that the error correction of corresponding bit bit reversal completes, no, error correction failure;

Step 5, Ping-pong FIFO access data, will eventually pass the data that verified stored in Ping-pong FIFO, by data that bus transfer calculates in the interruption of Fixed Time Interval.

Technical indicator of the present invention:

(1) input signal feature:

AD frequency acquisition: 10MHZ

AD gathers figure place: 12bit

Receiving video signals input range: 0 ~ 4V, input impedance ∞

Signal form: ADS-B 1090 ES

(2) sensitivity :-88dBm

(3) target disposal ability: 500 sorties/second.

Claims (1)

1. an Automatic dependent surveillance broadcast ADS-B receiver decoding plate, its Digital Logical Circuits is made up of AD analog-to-digital conversion module, FPGA digital logic module, it is characterized in that: the base-band digital processing section of described FPGA digital logic module mainly comprises input signal synchronization module, detection of preamble module, code bit pickup and Confidence Analysis module, CRC check error-detection error-correction module, Ping-pong FIFO access data module, systems baseband digital process mainly comprises the following steps

Step 1, signal amplitude filtering control, adopt detection of dynamic threshold algorithm, namely current detection threshold is dynamically determined according to the header reference power detected, by synchronous with thresholding for digital video signal time delay a period of time, this process eliminate some signal that segmented thresholding control method causes and correctly cannot resolve problem;

Step 2, detection of preamble, extract effective impulse position, signal rising edge and signal trailing edge three information from the signal through step 1, and when detecting that 4 have a pulse at S mode preamble time interval, then carry out subsequent packet and resolve, examination criteria is

1) 4 pulses have the sequential of 0-1.0-3.5-4.5 μ s,

2) rising edge >=2,

3) all the other are effective impulse position VPP,

Then the steps such as the calculating of header reference power, power consistency check, 1um/3.5us/4.5us test, DF certification are carried out, header computing reference power again after these checkings, for resolving, in 13us simultaneously after header being detected, continue to find header, if this header is equally by above-mentioned all tests, its header reference value is compared with present header reference frame angle value, if this new signal 3dB at least higher than old signal amplitude, so abandon old signal, process new signal, otherwise, ignore new signal, continue the old signal of process;

The pickup of step 3, code bit and Confidence Analysis, adopt the correlation method of multi-parameter and multisampling to carry out code pickup and the Confidence Analysis of ADS-B;

Step 4, CRC check error-detection error-correction, after the judgement of the extraction of completion code position and confidence level, error-detection error-correction to be carried out to them, adopt the strong error-detection error-correction method of confidence declaration, first the judgement of wrong patterns is carried out, equal zero, error detection is passed through, and inerrancy occurs, no, carry out the corresponding syndrome of low confidence bit with 112 bit correction of storage inside to combine, then carry out whether with wrong patterns matching judgment, be, the error correction of corresponding bit bit reversal completes, no, error correction failure, jumps out error-detection error-correction module;

Step 5, Ping-pong FIFO access data, will eventually pass the data that verified stored in Ping-pong FIFO, by data that bus transfer calculates in the interruption of Fixed Time Interval.