CN104660220B - Signal generator and signal generation method for generating integer frequency pulses - Google Patents
Signal generator and signal generation method for generating integer frequency pulses Download PDFInfo
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- CN104660220B CN104660220B CN201510058501.XA CN201510058501A CN104660220B CN 104660220 B CN104660220 B CN 104660220B CN 201510058501 A CN201510058501 A CN 201510058501A CN 104660220 B CN104660220 B CN 104660220B
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Abstract
The invention discloses a signal generator and a signal generation method for generating integer frequency pulses. The signal generator comprises a detection module, a division module and a waveform generation module which are connected in sequence. The signal generation method comprises the following steps: detecting the state of an input frequency value according to the frequency of a system clock through the signal generator, according to change of the input frequency value, outputting a division enabling signal, after the division module receives the division enabling signal, implementing division calculation on the system clock frequency and the input frequency value, generating the integer frequency pulses which are uniformly distributed within unit time according to the quotient and the remainder, and determining whether the integer frequency pulse signal is output or not according to a pulse output enabling signal. By adopting the signal generator and the signal generation method, conversion of a non-integer period to an integer period can be completed, the problem that non-integer periodic counting can be caused by integer frequency input values under the condition that the frequency of the system clock is fixed can be solved, and the signal generator and the signal generation method have the characteristics of high precision and high easiness in realization.
Description
Technical field
The invention belongs to field of signal processing, more particularly, to a kind of signal generator of generation integer frequency pulse
And signal generating method.
Background technology
Current pulse number modulator on the market, is carried out point with the cumulative thinking of frequency multiplication or counter according to weight coefficient more
The mode of frequency output is produced.Although the former design is simple, can not be divided exactly by frequency summary counter in frequency control word
When, can there is irregular waveform at each clearing moment of frequency accumulator in waveform, can affect the pulse square wave in the unit interval
Number；Although the design of the latter can export the impulse wave of non-integer clock cycle count, its precision is affected by reference frequency
It is larger, by taking sixteen bit signal generator as an example, if crystal oscillator is 50MHz, it is difficult accurately to produce 216=65536Hz is accurately
Reference frequency.
The content of the invention
For the disadvantages described above or Improvement requirement of prior art, the invention provides a kind of produce integer frequency pulses generation
Signal generator and signal generating method, its object is to carry out non-integer to the conversion of number of cycles, thus solve
Integer frequency input value can cause to export the problem that pulse non-integer is counted in the case that system clock frequency is fixed.
For achieving the above object, according to one aspect of the present invention, there is provided a kind of signal of generation integer frequency pulse
Generator, the signal generator includes detection module, dividing module and the waveform generation module being sequentially connected, the detection mould
Block, dividing module and waveform generation module receive same system clock signal；
Detection module is used to detect incoming frequency value, incoming frequency value and preset value is compared, according to comparative result
Output division enables signal and pulse output enables signal；
Dividing module is used for the frequency values of clock signal of system and incoming frequency value in the case where division enables the triggering of signal
Division arithmetic is carried out, output business, remainder and division complete to enable signal；
Waveform generation module is used to generate integer frequency according to the quotient and the remainder in the case where division completes the triggering for enabling signal
Rate pulse signal, and determine whether to export the integer frequency pulse signal according to pulse output enable signal；When what is received
When pulse output enable signal is high level, output pulse signal；When it is low level that the pulse output for receiving enables signal,
Stop output pulse signal.
Preferably, it is that high level is effective that the division of detection module output enables signal and pulse output enable signal.
Preferably, detection module is preset with maximum allowable incoming frequency value fmax；If the incoming frequency that detection module is received
Value is zero, then pulse output enables signal and division enables signal for low level；If incoming frequency value is more than 0 and is less than or equal to
fmax, then pulse output enables signal and division enables signal and is high level.
If it is further preferred that the incoming frequency value that detection module is received is more than fmax, pulse output enables and signal and removes
Method enables signal and is high level and incoming frequency value is considered as into invalid input, by fmaxAs incoming frequency value and system clock
The frequency values of signal carry out division arithmetic.
It is further preferred that default maximum allowable incoming frequency value f of detection modulemaxIt is less than system clock frequency
Integer value.
It is further preferred that waveform generation module is concrete such as according to the integer frequency pulse signal that the quotient and the remainder are generated
Under：Business is represented with Q, remainder is represented with R, generated with the R pulse that (Q+1) is the counting cycle in the unit interval, with Q to count week
(f-R) individual pulse of phase, the integer frequency pulse in two kinds of counting cycles is uniformly distributed.
To realize the object of the invention, according to another aspect of the present invention, there is provided a kind of generation integer frequency pulse
Signal generating method, the signal generator of the generation integer frequency pulse that the signal generating method is provided using the present invention, tool
Body is as follows：
(1) judge whether incoming frequency value f is zero, if so, then pulse output is enabled into signal and set low；If it is not, then by arteries and veins
Punching output enables signal and puts height, and into step (2)；
(2) whether incoming frequency value f is judged beyond default maximum allowable incoming frequency value, if it is not, then generate division making
Energy signal, into step (3)；If so, then incoming frequency value f is considered as into invalid input, using maximum allowable incoming frequency value as
Incoming frequency value, and division enable signal is generated, into step (3)；
(3) receive the division to enable after signal, the frequency values of clock signal of system are removed with incoming frequency value f
Method computing, the frequency values of the clock signal of system make dividend, obtain business Q, remainder R and division and complete to enable signal；
(4) receive the division to complete to enable after signal, integer frequency pulse is produced according to the business Q and remainder R value
Signal：The pulse signal generated in unit interval is divided into two parts, wherein R pulse using (Q+1) as the counting cycle, (f-R)
Using Q as the cycle of counting, the pulse in two kinds of counting cycles is uniformly distributed for individual pulse；If it is high level that pulse output enables signal,
The integer frequency output of pulse signal that then will be produced；If pulse output enables signal for low level, stop pulse signal output；
(5) detect whether incoming frequency value f changes, if it is not, all to count with (Q+1) in then continuing the output unit time
The R pulse of phase, with Q as (f-R) the individual pulse in counting cycle, the pulses in two kinds of counting cycles are uniformly distributed；If so, then enter
Step (1).
Preferably, in the step (5), in the rising edge time or trailing edge moment detection input frequency of clock signal of system
Whether rate value changes, if the rising edge time in clock signal of system detects incoming frequency value f and changes, in system clock
The next rising edge time of signal produces input value and changes flag bit and enter step (1)；If under clock signal of system
Drop detects incoming frequency value f and changes along the moment, then in generation of the next trailing edge moment input value of clock signal of system
Change flag bit and enter step (1).
It is further preferred that in the case where incoming frequency value f is changed, it is defeated by the pulse that the division enables signal
Go out to enable signal carries out logical AND operation acquisition with input value change flag bit.
In general, by the contemplated above technical scheme of the present invention compared with prior art, can obtain down and show
Beneficial effect：
(1) because the signal generator that the present invention is provided has carried out non-integer to integer according to the result of division arithmetic
The conversion in cycle, therefore no matter can incoming frequency pass through system clock frequency integral frequency divisioil, can be continuous at uniform intervals
The number pulse equal with incoming frequency numerical value in the output unit time；
(2) under system clock frequency fixing situation, integer frequency input value can cause non-integer to effectively solving of the present invention
The problem of cycle count, with high precision, it is easy to accomplish the characteristics of.
Description of the drawings
Fig. 1 is a kind of overall structure block diagram of the signal generator of generation integer frequency pulse signal that the present invention is provided；
Fig. 2 is a kind of each module of the signal generator of generation integer frequency pulse signal that the embodiment of the present invention 1 is provided
Between the main input/output relation connection figure of signal；
Fig. 3 is a kind of flow process of the signal generating method of generation integer frequency pulse signal that the embodiment of the present invention 2 is provided
Figure.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, and
It is not used in the restriction present invention.As long as additionally, technical characteristic involved in invention described below each embodiment
Not constituting conflict each other just can be mutually combined.
As shown in figure 1, the signal generator of the present invention includes that the detection module, dividing module and the waveform that are sequentially connected are produced
Module；Three modules receive same system clock signal input；
Detection module receives input frequency values f, detects to incoming frequency value f, if incoming frequency value is detected for 0
The pulse for being sent to waveform generation module is exported into enable signal to set low；Waveform generation module receives low level pulse output and enables
Stop pulse is exported after signal；Such as detect incoming frequency value not being 0 and change, then pulse output is enabled into signal and put
Height, and export division enable signal；
Detection module is preset with maximum allowable incoming frequency value, if incoming frequency value f is more than the maximum allowable input frequency
Rate value, then be considered as invalid input, and incoming frequency value f is processed according to maximum allowable incoming frequency value；The maximum allowable input
Frequency values are the integer value less than system clock frequency；
For example, when system clock frequency is 50MHz, if it is 500KHz to preset maximum allowable incoming frequency value, when input frequency
When rate value is more than 500KHz, incoming frequency value is considered as into invalid input, division arithmetic is carried out equal to 500KHz according to f, produced whole
Number frequency pulse signal.
The dividing module receives division and enables signal, and the division of the frequency and incoming frequency value that carry out system clock is transported
Calculate, output business Q, remainder R and division complete to enable signal；
The waveform generation module is completed enable signal and is triggered by division, and according to the quotient and the remainder pulse letter is generated
Number, the pulse signal generated in the unit interval is divided into two parts, and wherein R pulse is (f-R) individual using (Q+1) as the cycle of counting
Pulse is using Q as the cycle of counting.
As shown in Fig. 2 wherein, Clk is clock signal of system to each intermodule signal annexation of embodiment 1, and Rst_n is
Systematic reset signal, Div_en is that division enables signal, and Div_done completes enabling pulse signal for division, and Run is that pulse is defeated
Go out and enable signal, pnm is pulse output end mouth；
F is incoming frequency, and incoming frequency value f is with can arrange according to demand；The division of detection module output enables signal
Div_en, the driving as dividing module enables signal；
After dividing module receives division enables signal Div_en, carry out in the rising edge of next system clock cycle
Division calculation, dividend is the frequency values of the clock signal of system for writing dividing module, and divisor is incoming frequency value f；
After dividing module completes division calculation, complete to enable letter in next system clock cycle rising edge output division
Number Div_done, business Q, remainder R；These three signals are input into waveform generation module, are removed whenever waveform generation module is received
Method completes enabling pulse signal Div_done, then produce integer frequency pulse signal according to corresponding Q, R value for receiving；Work as waveform
It is when the pulse output enable signal that generation module is received is high level, the integer frequency pulse signal Jing pnm ports for generating is defeated
Go out；When it is low level that the pulse output for receiving enables signal, then stop pulse signal output.
As shown in figure 3, the flow process of the signal generating method of the embodiment of the present invention 2 is specific as follows：
(1) judge whether incoming frequency value f is zero, if so, then pulse output is enabled into signal and set low；If it is not, then by arteries and veins
Punching output enables signal and puts height, and into step (2)；
(2) whether incoming frequency value f is judged beyond default maximum allowable incoming frequency value, if it is not, then generate division making
Energy signal, into step (3)；If so, then incoming frequency value f is considered as into invalid input, using maximum allowable incoming frequency value as
Incoming frequency value, and division enable signal is generated, into step (3)；
(3) receive the division to enable after signal, the frequency values of clock signal of system are removed with incoming frequency value f
Method computing, the frequency values of the clock signal of system make dividend, obtain business Q, remainder R and division and complete to enable signal；
(4) receive the division to complete to enable after signal, integer frequency pulse is produced according to the business Q and remainder R value
Signal：The pulse signal generated in unit interval is divided into two parts, wherein R pulse using (Q+1) as the counting cycle, (f-R)
Using Q as the cycle of counting, the pulse in two kinds of counting cycles is uniformly distributed for individual pulse；If it is height that pulse output enables signal, will
The integer frequency output of pulse signal of generation；If it is low, stop pulse signal output that pulse output enables signal；
(5) detect whether incoming frequency value f changes, if it is not, all to count with (Q+1) in then continuing the output unit time
The R pulse of phase, with Q as (f-R) the individual pulse in counting cycle, the pulses in two kinds of counting cycles are uniformly distributed；If so, then enter
Step (1).
Below in conjunction with specific embodiment 1 and embodiment 2, the operation principle of the present invention is specifically described as follows：
When remainder R is non-zero, the counting cycle for showing the pulse corresponding to incoming frequency should be more than Q, less than (Q+1)
Decimal, is set to A；The purpose of the present invention is that the decimal A is converted into into R integer (Q+1) and (f-R) individual integer Q mean values, i.e.,
A=[R* (Q+1)+(f-R) Q]/f；With the R pulse that (Q+1) is the counting cycle in the output unit time, with Q to count the cycle
(f-R) individual pulse, the pulse signals in two kinds of output counting cycles are uniformly distributed；
When remainder R is zero, export in the unit interval with the R pulse that (Q+1) is the counting cycle, with Q to count the cycle
(f-R) individual pulse, the pulse signal in two kinds of counting cycles of output is uniformly distributed；
If system for use in carrying clock frequency is fclk, the clock cycle is Tclk；, then the cycle of integer frequency pulse signal is exported
For：The cycle of R pulse is (Q+1) * Tclk, (f-R) cycle of individual pulse is Q*Tclk。
In the case that effectively solving system clock signal frequency of the present invention is fixed, integer frequency input value can cause non-integer
The problem of cycle count.
As it will be easily appreciated by one skilled in the art that the foregoing is only presently preferred embodiments of the present invention, not to
The present invention, all any modification, equivalent and improvement made within the spirit and principles in the present invention etc. are limited, all should be included
Within protection scope of the present invention.
Claims (8)
1. it is a kind of produce integer frequency pulse signal generator, it is characterised in that the signal generator include be sequentially connected
Detection module, dividing module and waveform generation module, the detection module, dividing module and waveform generation module are received together
One clock signal of system；
The detection module is used to detect incoming frequency value, incoming frequency value and preset value is compared, according to comparative result
Output division enables signal and pulse output enables signal；
The dividing module is used for the frequency values of clock signal of system and incoming frequency value in the case where division enables the triggering of signal
Division arithmetic is carried out, output business, remainder and division complete to enable signal；
The waveform generation module is used to generate integer frequency according to the quotient and the remainder in the case where division completes the triggering for enabling signal
Rate pulse signal, and determine whether to export the integer frequency pulse signal according to pulse output enable signal；
The waveform generation module is specific as follows according to the integer frequency pulse signal that the quotient and the remainder are generated：Business is represented with Q,
Remainder is represented with R, is generated with the R pulse that (Q+1) is the counting cycle in the unit interval, with Q as (f-R) the individual arteries and veins in counting cycle
Punching, the integer frequency pulse in two kinds of counting cycles is uniformly distributed；Wherein, f refers to incoming frequency value.
2. signal generator as claimed in claim 1, it is characterised in that the division enables signal and pulse output enables letter
Number it is that high level is effective.
3. signal generator as claimed in claim 2, it is characterised in that the detection module is preset with maximum allowable input frequency
Rate value fmax；If incoming frequency value is zero, pulse output enables signal and division enables signal for low level；If incoming frequency
Value is more than 0 and less than or equal to fmax, then pulse output enables signal and division enables signal and is high level.
4. signal generator as claimed in claim 3, it is characterised in that if incoming frequency value is more than fmax, pulse output enable
Signal and division enable signal and are high level and incoming frequency value is considered as into invalid input, by fmaxAs incoming frequency value with
The frequency values of clock signal of system carry out division arithmetic.
5. the signal generator as described in claim 3 or 4, it is characterised in that maximum allowable incoming frequency value fmaxFor little
In the integer value of system clock frequency.
6. a kind of signal generating method of the signal generator described in any one of employing claim 1 to 5, it is characterised in that institute
State method specific as follows：
(1) judge whether incoming frequency value f is zero, if so, then pulse output is enabled into signal and set low；If it is not, then that pulse is defeated
Go out to enable signal and put height, and into step (2)；
(2) whether incoming frequency value f is judged beyond default maximum allowable incoming frequency value, if it is not, then generating division enables letter
Number, into step (3)；If so, then incoming frequency value f is considered as into invalid input, using maximum allowable incoming frequency value as input
Frequency values, and division enable signal is generated, into step (3)；
(3) receive the division to enable after signal, the frequency values of clock signal of system and incoming frequency value f are carried out into division fortune
Calculate, the frequency values of the clock signal of system make dividend, obtain business Q, remainder R and division and complete to enable signal；
(4) receive the division to complete to enable after signal, integer frequency pulse signal is produced according to the business Q and remainder R value：
The pulse signal generated in unit interval is divided into two parts, and wherein R pulse is using (Q+1) as the cycle of counting, (f-R) individual pulse
Using Q as the cycle of counting, the pulse in two kinds of counting cycles is uniformly distributed；If it is high level that pulse output enables signal, will produce
Raw integer frequency output of pulse signal；If pulse output enables signal for low level, stop pulse signal output；
(5) detect whether incoming frequency value f changes, if it is not, it is the counting cycle with (Q+1) then to continue the output unit time interior
R pulse, with Q as (f-R) the individual pulse in counting cycle, the pulses in two kinds of counting cycles are uniformly distributed；If so, step is then entered
(1)。
7. signal generating method as claimed in claim 6, it is characterised in that in the step (5), in clock signal of system
Whether rising edge time or trailing edge moment detection incoming frequency value change, if the rising edge time in clock signal of system is detected
Change to incoming frequency value f, then the next rising edge time in clock signal of system produces input value change flag bit simultaneously
Into step (1)；If detecting incoming frequency value f at the trailing edge moment of clock signal of system to change, in system clock
The next trailing edge moment of signal produces input value and changes flag bit and enter step (1).
8. signal generating method as claimed in claim 7, it is characterised in that in the case where incoming frequency value f is changed, institute
State division enable signal is carried out logical AND and is operated acquisition by pulse output enable signal and input value change flag bit.
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| CN105549681A (en) * | 2015-12-22 | 2016-05-04 | 武汉华中数控股份有限公司 | Method and system for accurately outputting pulse number in clock domain crossing manner |
| CN107153352A (en) * | 2017-04-25 | 2017-09-12 | 华南理工大学 | A kind of pulse generation method based on digital frequency synthesis technology |
| CN108055006A (en) * | 2017-12-29 | 2018-05-18 | 成都锐成芯微科技股份有限公司 | A kind of digital frequency multiplier |
| CN109327210A (en) * | 2018-09-29 | 2019-02-12 | 深圳市新川电气技术有限公司 | Pulse signal production method and device |
| CN110635854A (en) * | 2019-10-24 | 2019-12-31 | 深圳市富满电子集团股份有限公司 | Transmission protocol self-adaptive decoding system and method |
| CN111257628B (en) * | 2020-03-05 | 2022-05-06 | 成都飞机工业（集团）有限责任公司 | Anti-interference method for converting alternating current signal into pulse signal |
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| CN1773980A (en) * | 2004-11-09 | 2006-05-17 | 华为技术有限公司 | Orthogonal frequency division multiplexing integer frequency synchronizing method |
| CN103731145A (en) * | 2013-12-31 | 2014-04-16 | 中国国土资源航空物探遥感中心 | Time scale signal generator based on standard time pulse signals |
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| EP1507378B1 (en) * | 2003-08-14 | 2012-10-24 | Sony Deutschland GmbH | Frame and frequency synchronization for OFDM |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773980A (en) * | 2004-11-09 | 2006-05-17 | 华为技术有限公司 | Orthogonal frequency division multiplexing integer frequency synchronizing method |
| CN103731145A (en) * | 2013-12-31 | 2014-04-16 | 中国国土资源航空物探遥感中心 | Time scale signal generator based on standard time pulse signals |
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