CN104658601A - PUF (physically unclonable function) authentication method based on STT-RAM (spin-torque transfer RAM) storage unit error rate distribution - Google Patents
PUF (physically unclonable function) authentication method based on STT-RAM (spin-torque transfer RAM) storage unit error rate distribution Download PDFInfo
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Abstract
The invention discloses a PUF (physically unclonable function) authentication method based on STT-RAM (spin-torque transfer RAM) storage unit error rate distribution. The physical un-clonable authentication method comprises a pretreatment stage, a registration stage and a verification stage, and comprises the following steps of firstly, recording the positions of all EDPs (error-rate differential pairs) in an STT-RAM array in the pretreatment stage; then inputting a plurality of positions of the EDPs at the registration stage, and outputting reference output by a chip circuit by utilizing the relative size of two unit error rates in the EDPs at the registration stage; reproducing the registration stage at the verification stage; and finally, verifying whether given equipment and equipment at the registration stage are the same according to the output at the verification stage and the registration stage, thereby authenticating the genuine and sham of the chip. With the method provided by the invention, the authentication problem of the equipment is solved at very small hardware cost and time cost, and the authentication reliability is improved.
Description
Technical field
The invention belongs to information security field, relate to a kind of physics and can not clone (PUF) authentication method, particularly relate to a kind of physics based on the distribution of STT-RAM storage unit error rate and can not clone authentication method.
Background technology
Spin-transfer torque random read-write device (STT-RAM) is a kind of novel non-volatile (Non-volatile) storer.The advantages such as STT-RAM is considered to one of substitute of following SRAM, has high density, low speed paper tape reader static power disspation, the low memory access time.Meanwhile, physics clone technology (PUF) just can not be widely proposed and is being applied to device authentication, and other non-volatile memories have been proposed for and make PUF, but ubiquity hardware spending is large or postpone the problems such as high.
2011, the people such as the Prabhu of the U.S. proposed to utilize NAND Flash to carry out device authentication.First they extract in Flash, and each bit is to the sensitivity of interference mistake (disturb error), and programmed delays etc., the way then calculating related coefficient is distinguished and trusted authentication chip.This way postpones long (15s), and may lose efficacy under environmental impact.
2012, the people such as the Rajendran of the U.S. proposed to utilize memristor (Memristor) to carry out device authentication.First they use inductor (sensor) to gather the voltage of each cell node, then utilizes information of voltage to carry out trusted authentication chip.This way uses inductor to gather each node voltage due to needs, and additional circuit expense is comparatively large, and environmental change also can affect stability.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the invention provides the physics that one utilizes spin-transfer torque random read-write device (STT-RAM) storage unit error rate to distribute and can not clone authentication method, under very little hardware costs and time cost, solve the problem of device authentication, improve the reliability of certification.
Be defined as follows term herein:
(1) Error-Least-State: represent in working environment of the present invention, the environment that STT-RAM cell error rate is minimum.Such as, under the environment of operating voltage 0.9V-1.1V, working temperature 275K-325K, Error-Least-State represents the environment of maximum operating voltage, minimum operating temperature, i.e. the environment of (1.1V, 275K).
(2) Error-Most-State: represent in working environment of the present invention, the environment that STT-RAM cell error rate is the highest.Such as, under operating voltage 0.9V-1.1V, working temperature 275K-325K environment, Error-Most-State represents the environment of minimum operating voltage, maximum operating temperature, i.e. the environment of (0.9V, 325K).
(3) RWR test: namely reading test, is a kind of method of detecting unit error rate.The method is reading unit data first, write back after reversal data, more whether sense data detects data and successfully change and detect read-write error.
(4) EDP: i.e. error rate differential pair (Error-rate Differential Pair), represent two adjacent cells meeting following relationship in STT-RAM array: take turns in RWR test at N, the difference of the number of times that two unit make a mistake is more than or equal to a given times N
th.By carrying out emulation experiment to the STT-RAM storage array of 1MB size 1T1J, prove N and N
thvalue should meet N=N
th>=3, N=N in the embodiment of the present invention
th=3.
Principle of the present invention is, the physics that the present invention is based on the distribution of STT-RAM storage unit error rate can not be cloned authentication method and comprised three phases: pretreatment stage, registration phase and Qualify Phase.First the position of all EDP in STT-RAM array is recorded at pretreatment stage (Pre-process), then multiple EDP position is inputted at registration phase (Enrollment Phase), chip circuit utilizes two cell error rate relative sizes in these EDP to export with reference to exporting (Reference Response), again reappear registration phase at Qualify Phase (Evaluation Phase), finally judge the true and false of chip according to the output of Qualify Phase and registration phase.
Technical scheme provided by the invention is:
Physics based on the distribution of STT-RAM storage unit error rate can not clone an authentication method, in turn includes the following steps:
1) perform following operation at pretreatment stage, obtain the address of multiple EDP unit:
1.1 respectively under Error-Least-State and Error-Most-State environment, and for each odd address unit, the address setting this unit is Addr, takes turns RWR test judge address is whether Addr and Addr+1 two unit form EDP by N;
If 1.2 said two units form EDP, then obtain address EDP_Addr and EDP_Addr+1 of this EDP;
EDP_Addr output is saved in database by 1.3;
2) performing following operation at registration phase, obtaining with reference to exporting:
2.1 obtain N
seceDP in the individual database obtained at pretreatment stage, counter is set to 0; Wherein, N
secfor even number; N
secvalue should be more than or equal to 128, N in embodiment in the present invention
secvalue is 128;
2.2 for each EDP, and judge that two unit of EDP_Addr and EDP_Addr+1 address are taken turns in RWR test at R, the number of times which unit makes a mistake is more; If EDP_Addr+1 makes a mistake often than EDP_Addr, counter adds 1; By carrying out emulation experiment to the STT-RAM storage array of 1MB size 1T1J, prove that the value of R should meet R>=4, R=4 in the embodiment of the present invention.
2.3 as traversal N
secafter individual EDP, by the number in counter and N
sechalf than size, when being more than or equal to export 1 otherwise export 0;
2.4 using 2.3 Output rusults as with reference to exporting, deposit in the database of a safety;
3) set the different number of times of result as 0, perform following operation at Qualify Phase, obtain the total degree that result is different, whether identical with the equipment of registration phase for verifying to locking equipment:
3.1 obtain N
seceDP in the individual database obtained at pretreatment stage, is set to 0 by counter; Guarantee this N
secindividual EDP is previously used at registration phase as the input of Integratively; This N
secn in value and step 2.1
secvalue is identical, and in the embodiment of the present invention, value is 128;
3.2 for each EDP, and judge that two unit of EDP_Addr and EDP_Addr+1 address are taken turns in RWR test at R, the number of times which unit makes a mistake is more; If EDP_Addr+1 makes a mistake often than EDP_Addr, counter adds 1; This R value is identical with the R value in step 2.2, and in the embodiment of the present invention, value is 4;
3.3 as traversal N
secafter individual EDP_Addr, by the number in counter and N
sechalf than size, when being more than or equal to export 1 otherwise export 0;
The reference Output rusults of the Output rusults of 3.3 and registration phase step 2.4 is made comparisons by 3.4, if the two result difference, the different number of times of result adds 1;
Repeat step 3.1 to 3.4, obtain the total degree that result is different for more than 3.5 time;
Whether the total degree that in 3.6 determining steps 3.5, result is different is greater than setting threshold value, and as being greater than then, judgment device is not by certification, otherwise equipment passes through certification.
In embodiments of the present invention, the above-mentioned physics based on the distribution of STT-RAM storage unit error rate can not be cloned authentication method and be carried out under operating voltage 0.9V-1.1V, working temperature 275K-325K environment, wherein, Error-Most-State in step 1.1 represents the environment of minimum operating voltage, maximum operating temperature, the i.e. environment of (0.9V, 325K); Error-Least-State represents the environment of maximum operating voltage, minimum operating temperature, i.e. the environment of (1.1V, 275K).
The above-mentioned physics based on the distribution of STT-RAM storage unit error rate can not be cloned in authentication method, and through emulation experiment, step 1.1 is whether the difference of the number of times made a mistake by two unit is more than or equal to N
thjudge whether the unit of two positions forms EDP; N and N in step 1.1
thvalue should meet N=N
th>=3, N=N in the embodiment of the present invention
th=3; R value in step 2.2 should meet R>=4, R=4 in the embodiment of the present invention; R value in step 3.2 is identical with step 2.2; In step 3.5 is repeatedly 128 times, and the threshold value in step 3.6 is 23.In embodiments of the present invention, the N in step 2.1 and step 3.1
secvalue is 128.
Compared with prior art, the invention has the beneficial effects as follows:
Authentication method can not be cloned by the physics based on the distribution of STT-RAM storage unit error rate provided by the present invention, in the EDP utilizing Qualify Phase and registration phase to export, two cell error rate relative sizes carry out certification to hardware device, improve the reliability of certification, accelerate certification speed, save hardware spending.
Accompanying drawing explanation
Fig. 1 is the FB(flow block) of pretreatment stage in the embodiment of the present invention.
Fig. 2 is the FB(flow block) of registration phase in the embodiment of the present invention.
Fig. 3 is the FB(flow block) of Qualify Phase in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, further describe the present invention by embodiment, but the scope do not limited the present invention in any way.
The present embodiment carries out certification for the STT-RAM of 1 1MB size 1T1J, specifies its working environment to be voltage range 0.9V-1.1V, temperature range 275K to 325K.Utilize the physics based on the distribution of STT-RAM storage unit error rate provided by the invention to clone authentication method, the certification work of the present embodiment is divided into three phases---pretreatment stage, registration phase, Qualify Phase.
A. at pretreatment stage, perform and operate as follows:
A1. respectively under Error-Least-State and Error-Most-State, for each odd address Addr, judge whether the unit of Addr and Addr+1 two positions forms EDP.Judge that the method for EDP is, take turns in RWR test at N, the difference of the number of times that two unit make a mistake is more than or equal to N
th, in the present embodiment, N and N
thequal value is 3;
If A2. form the value that EDP exports Addr, otherwise whether two unit continuing to detect next odd address corresponding form EDP.；
A3. the EDP of output is preserved for using after a while;
B. at registration phase, perform and operate as follows:
B1. the EDP_Addr that 128 pretreatment stages obtain is inputted;
B2. for each EDP_Addr, judge that two unit of EDP_Addr and EDP_Addr+1 address are taken turns in RWR test 4, which unit makes a mistake often, if the latter is many, counter adds 1, otherwise does not add;
B3. when after traversal 128 EDP_Addr, by the number in counter with 64 than size, export 1 otherwise 0 when being more than or equal to;
B4. Output rusults is deposited in the database of a safety and export as the reference of authentication phase after a while;
C. at Qualify Phase, perform and operate as follows:
C1. input 128 EDP_Addr, guarantee to be previously used as the input of Integratively at these 128 EDP_Addr of registration phase;
C2. for each EDP_Addr, judge that two unit of EDP_Addr and EDP_Addr+1 address are taken turns in RWR test at R, which unit makes a mistake often, if the latter is many, counter adds 1, otherwise does not add;
C3. when after traversal 128 EDP_Addr, by the number in counter with 64 than size, export 1 otherwise 0 when being more than or equal to;
C4. the result of Output rusults and registration phase is made comparisons;
C5. repeat C1 to C4 step certain number of times, see that finally to have how many times output different, if different number of times is greater than 23, then judges chip not by certification, otherwise pass through certification.
Fig. 1 is the FB(flow block) of pretreatment stage in the embodiment of the present invention.With reference to accompanying drawing 1, at pretreatment stage, first the working environment of STT-RAM is set to Error-Most-State, i.e. the environment of (0.9V, 325K); Then verify that the unit of odd address Addr and Addr+1 position is taken turns during RWR tests 3 one by one, whether the difference of number of times Err1 and the Err2 made a mistake in odd address Addr and Addr+1 position is more than or equal to N
th, N
thvalue is 3, if it is by Addr stored in database.Such as take turns RWR through 3 and test the unit difference mistake of discovery 1 and 2 position 3 times and 0 time, so 1 will be stored into database.And then, the working environment of STT-RAM is set to Error-Least-State, i.e. (1.1V, environment 275K), the unit whether Addr then tested in above-mentioned database still meets Addr and Addr+1 position is in such a case more than or equal to N in the difference of 3 errors number Err1 and the Err2 taken turns in RWR test
th, N
thvalue is 3, if met, retains Addr, if do not met, from database, rejects Addr.The unit such as issuing current address 1 and address 2 at Error-Least-State 3 take turns RWR test in the difference of errors number be less than 3, so 1 will reject from database.
Fig. 2 is the FB(flow block) of registration phase in the embodiment of the present invention.With reference to accompanying drawing 2, at registration phase, first counter Intermediate is set to 0, then input 128 pretreatment stage obtain, Addr in database.For each Addr, compare the errors number of Addr and Addr+1 position units under R (R value is 4) takes turns RWR test, if the errors number of Addr is greater than Addr+1, so counter Intermediate adds 1.After having traveled through 128 Addr again, namely during Counter=128, compare the size of the value and 64 (half of 128) of counter Intermediate, if be greater than, export 1, otherwise export 0.Finally the database stored in a safety will be exported.Such as 128 Addr, suppose wherein have 67 Addr all to meet Addr more in 4 errors number of taking turns under RWR test than Addr+1 position units, the numerical value of so last counter is 67.Due to 67>64, therefore export 1 in safety database.
Fig. 3 is the FB(flow block) of Qualify Phase in the embodiment of the present invention.With reference to accompanying drawing 3, at Qualify Phase, first counter Intermediate is set to 0, then inputs once at 128 Addrs of registration phase as one group of input.For each Addr, compare Addr and Addr+1 position units 4 take turns RWR test under errors number, if the errors number of Addr is greater than Addr+1, so counter Intermediate adds 1.After having traveled through 128 Addr again, namely during Counter=128, compare the size of counter and 64, if be greater than, export 1, otherwise export 0.Finally corresponding data in output and safety database is compared, if difference, record different number of times HD.Repeatedly carry out above-mentioned steps 128 times, namely during Compare_times=128, by different number of times HD compared with threshold value 23, if be greater than 23, judge authentication failed otherwise success.Such as tested STT-RAM chip, have 25 times and export different if to find that at Qualify Phase it exports by test from corresponding in safety database, so its authentication result is authentication failed, namely can think that this chip block is not the chip of registration phase.
It should be noted that the object publicizing and implementing example is to help to understand the present invention further, but it will be appreciated by those skilled in the art that: in the spirit and scope not departing from the present invention and claims, various substitutions and modifications are all possible.Therefore, the present invention should not be limited to the content disclosed in embodiment, and the scope that the scope of protection of present invention defines with claims is as the criterion.
Claims (8)
1. the physics based on the distribution of STT-RAM storage unit error rate can not clone an authentication method, in turn includes the following steps:
1) perform following operation at pretreatment stage, obtain the address of multiple EDP unit:
1.1 respectively under Error-Least-State and Error-Most-State environment, and for each odd address unit, the address setting this unit is Addr, and whether two unit being Addr and Addr+1 by N wheel RWR test judging unit address form EDP;
If 1.2 said two units form EDP, then obtain address EDP_Addr and EDP_Addr+1 of this EDP;
EDP_Addr output is saved in database by 1.3;
2) performing following operation at registration phase, obtaining with reference to exporting:
2.1 obtain N from database described in step 1.3
secthe individual EDP obtained at pretreatment stage, is set to 0 by counter; Described N
secfor being more than or equal to the even number of 128;
2.2 for each EDP in step 2.1, and judge that two unit of EDP_Addr and EDP_Addr+1 address are taken turns in RWR test at R, the number of times which unit makes a mistake is more; If EDP_Addr+1 makes a mistake often than EDP_Addr, the counter in step 2.1 adds 1;
2.3 as traversal N
secafter individual EDP, by the number in counter and N
sechalf than size, the number in counter is more than or equal to N
secone half export 1, otherwise export 0;
2.3 Output rusults export as reference by 2.4, deposit in the database of a safety;
3) set the different number of times of result as 0, perform following operation at Qualify Phase, obtain the total degree that result is different, whether identical with the equipment of registration phase for verifying to locking equipment:
3.1 obtain N
seceDP in the database that individual pretreatment stage obtains, is set to 0 by counter; Described N
secindividual EDP is previously used at registration phase as the input of Integratively; Described N
secvalue and step 2.1 in N
secidentical;
3.2 for each EDP in step 3.1, and judge that two unit of EDP_Addr and EDP_Addr+1 address are taken turns in RWR test at R, the number of times which unit makes a mistake is more; If EDP_Addr+1 makes a mistake often than EDP_Addr, the counter in step 3.1 adds 1;
3.3 as the described N of traversal
secafter individual EDP_Addr, by the number in counter and N
sechalf than size, the number in counter is more than or equal to N
secone half export 1, otherwise export 0;
The reference Output rusults of the Output rusults of 3.3 and registration phase step 2.4 is made comparisons by 3.4, if the two result difference, the different number of times of result adds 1;
Repeat step 3.1 to 3.4, obtain the total degree that result is different for more than 3.5 time;
Whether the total degree that in 3.6 determining steps 3.5, result is different is greater than setting threshold value, and as being greater than then, judgment device is not by certification, otherwise equipment passes through certification.
2. physics can not clone authentication method as claimed in claim 1, it is characterized in that, Error-Most-State described in step 1.1 represents that minimum operating voltage is 0.9V, and maximum operating temperature is the environment of 325K; Described Error-Least-State represents that maximum operating voltage is 1.1V, and minimum operating temperature is the environment of 275K.
3. physics can not clone authentication method as claimed in claim 1, it is characterized in that, whether the difference whether forming the number of times that EDP makes a mistake particular by two unit that described element address is Addr and Addr+1 described in step 1.1 is more than or equal to N
thjudge, N
thequal with N described in step 1.1, value is for being more than or equal to 3.
4. physics can not clone authentication method as claimed in claim 3, it is characterized in that, N value described in step 1.1 is 3.
5. physics can not clone authentication method as claimed in claim 1, it is characterized in that, the N in step 2.1 and step 3.1
secvalue is 128.
6. physics can not clone authentication method as claimed in claim 1, it is characterized in that, described in step 2.2 and step 3.2, the value of R is 4.
7. physics can not clone authentication method as claimed in claim 1, it is characterized in that, is repeatedly 128 times described in step 3.5.
8. physics can not clone authentication method as claimed in claim 1, it is characterized in that, threshold value described in step 3.6 is 23.
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