CN104657239A - Transient fault restoration system and transient fault restoration method of separated log based multi-core processor - Google Patents
Transient fault restoration system and transient fault restoration method of separated log based multi-core processor Download PDFInfo
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Abstract
The invention discloses a transient fault restoration system and a transient fault restoration method of a separated log based multi-core processor, belongs to the technical field of computer, and aims at solving the problem that the restoration of determinate fault of non-determinate events of a multi-core processor is lack of a high-availability solution. The system comprises a separated log recording module, a separated log controller module and a hardware restoration module, wherein the separated log recording module is used for recording the non-determinate event information of a corresponding inner core, recording the memory competition logs separately by adopting a point-to-point dependence relationship, recording the initially occurring party of the dependence relationship at the response party of a consistency protocol, recording the causey party of the dependency relationship at the request party, and recording the interruption type and the interruption address for the external interruption; the separated log recording module is used for establishing the mapping relationship set between the log recording space and the inspection point; the hardware restoration module is used for completing the determinate restoration after the inspection point of the transient fault by combining the rollback restoration technique of the separated type log and the determinate repeat technique. The transient fault restoration system and the transient fault restoration method of the separated log based multi-core processor are used for the fault restoration of the multi-core processor.
Description
Technical field
The invention belongs to field of computer technology.
Background technology
The technology given priority in current high-effect trusted computer is System Fault Tolerance.Fault recovery eliminates fault recovery and makes system continue the important step run.Only after fault recovery link, the object of System Fault Tolerance just can be achieved.Meanwhile, the polycaryon processor transient fault Restoration Mechanism of High Availabitity, is conducive to widening the application of polycaryon processor chip in numerous high reliability request fields such as rugged surroundings calculating, Industry Control, digital medical, automatic intelligent instrument, mobile computing.
The recovery of polycaryon processor hardware fault is the study hotspot in the fields such as parallel architecture, fault-tolerant calculation, system reliability design.But for the determinacy fault recovery of polycaryon processor non-deterministic event, the technical method Performance And Reliability based on software and hardware recovery proposed is difficult to practical requirement, really effectively can't solve the fault restoration problem of polycaryon processor chip, lack the solution that high availability non-deterministic event transient fault is recovered.
Summary of the invention
The determinacy fault recovery that the object of the invention is to solve polycaryon processor non-deterministic event lacks the problem of high-availability solution, the invention provides a kind of polycaryon processor transient fault recovery system based on separate type daily record and transient fault restoration methods thereof.
Polycaryon processor transient fault recovery system based on separate type daily record of the present invention,
Described system comprises separate type logger module, separate type daily record controller module and recovers hardware module; In each kernel of processor, embed separate type logger module and recover hardware module,
Described separate type logger module, for recording the non-deterministic event information of corresponding kernel, by adopting the dependence of point-to-point, record is separated to memory contention daily record, in the first generation side of the answer party record dependence of consistency protocol, the rear generation side of dependence is recorded, to outside interruption logging interrupt type and interrupt address requesting party;
Described separate type daily record controller module, for setting up the mapping relations in log recording space and checkpointing;
Described recovery hardware module, in conjunction with the rollback recovery technology of separate type daily record and Deterministic Replay technology, completes the determinacy behind the checkpoint of transient fault and recovers.
Described separate type logger module comprises circulation and the sequence first side's of generation register Pred_IIC, blank(ing) instruction counter IIC, circulation occurs the side of generation register Succ_IIC, overflow register OVF after sequence occurs, N number ofly writes signature WF and N number ofly read the RF that signs; Described N is the interior check figure of processor;
There is the sequence first side's of generation register Pred_IIC in circulation, for marking non-deterministic event for the first side of generation;
Blank(ing) instruction counter IIC, for recording the blank(ing) instruction count value of adjacent uncertainty recording events;
The side of generation register Succ_IIC after circulation generation sequence is rear generation side for marking non-deterministic event;
Overflow register OVF, for marking the register size and the non-deterministic event type that determine to select recording events, first place is 0 expression memory contention, and first place is that 1 expression is interrupted, second is that 0 expression adopts 2B register to store, and second is that 1 expression adopts 4B register to store;
N number ofly write signature WF, for recording write conflict address set in N number of kernel memory contention, during N number of kernel interrupts, record interrupts jump address;
N number ofly read the RF that signs, for recording read conflict address set in N number of kernel memory contention, N number of kernel records address, interrupt spot in interrupting.
Separate type daily record controller comprises N number ofly to be read signature address register and N number ofly writes signature address register;
N number ofly reading address register of signing, N number ofly reading the termination address of RF of signing for mapping;
N number ofly write signature address register, for mapping N number of termination address writing signature WF.
Described recovery hardware module comprises N number of CP register, N number of CS register and an IIC register;
N number of CP register, for recording the count value of the wakeup message sending to a certain thread of other kernel;
N number of CS register, for recording the count value of the instruction of blocking because of a certain thread of other kernel;
An IIC register, for recording the blank(ing) instruction count value of adjacent uncertainty recording events.
Based on the transient fault restoration methods of the polycaryon processor transient fault recovery system of separate type daily record, described method comprises the steps:
Described method comprises the steps:
Step 1: when hardware check point starts to store, adopts separate type logger module, reads signature address register and writes signature address register record non-deterministic event information;
Step 2: when recovering from hardware check point module, kernel reads sign address register and the information writing signature address register record, if the information that will read exceedes address, stops, otherwise performs step 3;
Step 3: read 16 information from memory contention daily record, if overflow register OVF has mark, need reading 32 information; In the information that overflow register OVF reads, judge it is competition conflict or external interrupt according to the first, if then compete conflict, perform step 4; If external interrupt, perform step 6;
Step 4: read overflow register OVF second information, according to type type judge be first the side of generation or after the side of generation; If the first side of generation, the count value of the CP register of kernel adds up, and after executing instruction, the count value of CP register is sent to all the other kernels as wakeup message; If after the side of generation, the count value of the CS register of kernel adds up, and performs this instruction again when by the time the wakeup message that sends of all the other kernels is identical with the count value of CS register;
Step 5: the value of the complete rear blank(ing) instruction counter IIC of instruction adds up, when after sending wakeup message or when receiving wakeup message and after executing with it corresponding instruction, kernel repeated execution of steps 2;
Step 6: read signature register and obtain interruption start address, again call the external unit of interruption, continue to perform from writing signature register address; Kernel repeated execution of steps 2.
The process of described step 1 comprises the steps:
Step one: when hardware check point module starts to store, the reading signature register and write signature register and all reset of separate type log control module; Separate type logger module starts to record non-deterministic event information; When conflict being detected for memory contention, perform step 2; When conflict being detected for external interrupt, perform step 5;
Step 2: blank(ing) instruction counter IIC adds 1, when the value of described IIC is not less than 2
14time, select 4B register store and make marks at overflow register OVF, otherwise select 2B register to store; Overflow register OVF store first place be labeled as 0, second as competition conflict type mark described in type comprise first generation side or after the side of generation, proceed to step 3;
Step 3: add address corresponding for the memory block that there is memory contention to all read signature register or write signature register, according to competition conflict type decided there is the sequence first side's of generation register Pred_IIC and circulation in circulation and the side of generation register Succ_IIC after sequence occurs do different marks, proceed to step 4;
Step 4: upgrade separate type log control module and read signature register or write the IIC termination address of signature register record, return step one;
Step 5: blank(ing) instruction counter IIC adds 1, when the value of described IIC is not less than 2
14time, select 4B register store and make marks at overflow register OVF, otherwise select 2B register storage overflow register OVF storage first place to be labeled as 1, proceed to step 6;
Step 6: read the address that signature register preserves external interrupt, writes the address that signature register preserves redirect, proceeds to step 7;
Step 7: upgrade the termination address that separate type log control module is read signature register and write signature register record, return step one.
Beneficial effect of the present invention is, realizes separate type log recording mechanism, reduces non-deterministic event expense, improve concurrent resume speed, and the implementation before the transient fault of determinacy recovery more accurately occurs, improves high availability.
Accompanying drawing explanation
Fig. 1 is the principle schematic of the polycaryon processor transient fault recovery system based on separate type daily record described in embodiment one;
Fig. 2 is the principle schematic of the separate type logger module described in embodiment two;
Fig. 3 is the separate type daily record controller module described in embodiment four.
Fig. 4 is the principle schematic of the recovery hardware module described in embodiment three;
Fig. 5 is in embodiment six, the principle schematic of separate type logger module memory contention recording mechanism.
Embodiment
Embodiment one: composition graphs 1 illustrates present embodiment, the polycaryon processor transient fault recovery system based on separate type daily record described in present embodiment, described system comprises separate type logger module, separate type daily record controller module and recovers hardware module; In each kernel of processor, embed separate type logger module and recover hardware module,
Described separate type logger module, for recording the non-deterministic event information of corresponding kernel, by adopting the dependence of point-to-point, record is separated to memory contention daily record, in the first generation side of the answer party record dependence of consistency protocol, the rear generation side of dependence is recorded, to outside interruption logging interrupt type and interrupt address requesting party;
Described separate type daily record controller module, for setting up the mapping relations in log recording space and checkpointing;
Described recovery hardware module, in conjunction with the rollback recovery technology of separate type daily record and Deterministic Replay technology, completes the determinacy behind the checkpoint of transient fault and recovers.
This embodiment is that example is described in the processor chips of 4 cores, the transient fault restoration methods provided is for the polycaryon processor of frequent interactive information, in processor core, add separate type logger module and recover hardware module, the non-deterministic event realizing transient fault recovers.
Embodiment two: composition graphs 2 illustrates present embodiment, present embodiment is the further restriction to the polycaryon processor transient fault recovery system based on separate type daily record described in embodiment one, and described separate type logger module comprises circulation and the sequence first side's of generation register Pred_IIC, blank(ing) instruction counter IIC, circulation occurs the side of generation register Succ_IIC, overflow register OVF after sequence occurs, N number ofly writes signature WF and N number ofly read the RF that signs; Described N is the interior check figure of processor;
There is the sequence first side's of generation register Pred_IIC in circulation, for marking non-deterministic event for the first side of generation;
Blank(ing) instruction counter IIC, for recording the blank(ing) instruction count value of adjacent uncertainty recording events;
The side of generation register Succ_IIC after circulation generation sequence is rear generation side for marking non-deterministic event;
Overflow register OVF, for marking the register size and the non-deterministic event type that determine to select recording events, first place is 0 expression memory contention, and first place is that 1 expression is interrupted, second is that 0 expression adopts 2B register to store, and second is that 1 expression adopts 4B register to store;
N number ofly write signature WF, for recording write conflict address set in N number of kernel memory contention, during N number of kernel interrupts, record interrupts jump address;
N number ofly read the RF that signs, for recording read conflict address set in N number of kernel memory contention, N number of kernel records address, interrupt spot in interrupting.
Embodiment three: composition graphs 3 illustrates present embodiment, present embodiment is the further restriction to the polycaryon processor transient fault recovery system based on separate type daily record described in embodiment two, and separate type daily record controller comprises N number ofly to be read signature address register and N number ofly writes signature address register;
N number ofly reading address register of signing, N number ofly reading the termination address of RF of signing for mapping;
N number ofly write signature address register, for mapping N number of termination address writing signature WF.
Embodiment four: composition graphs 4 illustrates present embodiment, present embodiment is the further restriction to the polycaryon processor transient fault recovery system based on separate type daily record described in embodiment three,, described recovery hardware module comprises N number of CP register, N number of CS register and an IIC register;
N number of CP register, for recording the count value of the wakeup message sending to a certain thread of other kernel;
N number of CS register, for recording the count value of the instruction of blocking because of a certain thread of other kernel;
An IIC register, for recording the blank(ing) instruction count value of adjacent uncertainty recording events.
Embodiment five: present embodiment is the transient fault restoration methods of the polycaryon processor transient fault recovery system based on separate type daily record described in embodiment four,
Described method comprises the steps:
Described method comprises the steps:
Step 1: when hardware check point starts to store, adopts separate type logger module, reads signature address register and writes signature address register record non-deterministic event information;
Step 2: when recovering from hardware check point module, kernel reads sign address register and the information writing signature address register record, if the information that will read exceedes address, stops, otherwise performs step 3;
Step 3: read 16 information from memory contention daily record, if overflow register OVF has mark, need reading 32 information; In the information that overflow register OVF reads, judge it is competition conflict or external interrupt according to the first, if then compete conflict, perform step 4; If external interrupt, perform step 6;
Step 4: read overflow register OVF second information, according to type type judge be first the side of generation or after the side of generation; If the first side of generation, the count value of the CP register of kernel adds up, and after executing instruction, the count value of CP register is sent to all the other kernels as wakeup message; If after the side of generation, the count value of the CS register of kernel adds up, and performs this instruction again when by the time the wakeup message that sends of all the other kernels is identical with the count value of CS register;
Step 5: the value of the complete rear blank(ing) instruction counter IIC of instruction adds up, when after sending wakeup message or when receiving wakeup message and after executing with it corresponding instruction, kernel repeated execution of steps 2;
Step 6: read signature register and obtain interruption start address, again call the external unit of interruption, continue to perform from writing signature register address; Kernel repeated execution of steps 2.
Embodiment six: present embodiment is the further restriction of the transient fault restoration methods to the polycaryon processor transient fault recovery system based on separate type daily record described in embodiment five, and the process of described step 1 comprises the steps:
Step one: when hardware check point module starts to store, the reading signature register and write signature register and all reset of separate type log control module; Separate type logger module starts to record non-deterministic event information; When conflict being detected for memory contention, perform step 2; When conflict being detected for external interrupt, perform step 5;
Step 2: blank(ing) instruction counter IIC adds 1, when the value of described IIC is not less than 2
14time, select 4B register store and make marks at overflow register OVF, otherwise select 2B register to store; Overflow register OVF store first place be labeled as 0, second as competition conflict type mark described in type comprise first generation side or after the side of generation, proceed to step 3;
Step 3: add address corresponding for the memory block that there is memory contention to all read signature register or write signature register, according to competition conflict type decided there is the sequence first side's of generation register Pred_IIC and circulation in circulation and the side of generation register Succ_IIC after sequence occurs do different marks, proceed to step 4;
Step 4: upgrade separate type log control module and read signature register or write the IIC termination address of signature register record, return step one;
Step 5: blank(ing) instruction counter IIC adds 1, when the value of described IIC is not less than 2
14time, select 4B register store and make marks at overflow register OVF, otherwise select 2B register storage overflow register OVF storage first place to be labeled as 1, proceed to step 6;
Step 6: read the address that signature register preserves external interrupt, writes the address that signature register preserves redirect, proceeds to step 7;
Step 7: upgrade the termination address that separate type log control module is read signature register and write signature register record, return step one.
Wherein, in separate type logger module during memory contention, as shown in Figure 5, concrete steps are as follows for recording mechanism:
Step 1: processor core i and processor core j performs respective operation respectively;
Step 2: when systems axiol-ogy is to conflict j:2wr (x)-> i:3wr (x), consider the reducible subtractive of conflict, actual processor core j is with IIC=2, the first generation side of the corresponding current occurred sequence 2-> 3 of this conflict of the format record of type=0 is in the memory contention daily record of correspondence, wherein 0 represents the first generation side conflicted, and 2 represent the blank(ing) instruction number that distance log recordings last time conflict.Meanwhile, processor core i records the format record of IIC=3, type=1 in the memory contention daily record of i, and wherein 1 represents the rear generation side conflicted.Execute the instruction processing unit core IIC after conflict to reset.
Step 3: when systems axiol-ogy is to conflict i:1rd (m)-> j:4wr (m), processor core i is with IIC=3, type=0, processor > is recorded to the logger module of each self processor respectively with the form of IIC=1, type=1.Execute the instruction processing unit core IIC after conflict to reset.
Step 4: when systems axiol-ogy is to conflict j:4wr (m)-> i:5rd (m), processor core j is with IIC=1, type=0, processor core i is recorded to the logger module of each self processor respectively with the form of IIC=2, type=1.Execute the instruction processing unit core IIC after conflict to reset.
Step 5: when systems axiol-ogy is to conflict i:3wr (x)-> j:6wr (x), processor core i is with IIC=2, type=0, processor core j is recorded to the logger module of each self processor respectively with the form of IIC=1, type=1.Execute the instruction processing unit core IIC after conflict to reset.
The above; be only the present invention's preferably embodiment; these embodiments are all based on the different implementations under general idea of the present invention; and protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.
Claims (6)
1. based on the polycaryon processor transient fault recovery system of separate type daily record, it is characterized in that, described system comprises separate type logger module, separate type daily record controller module and recovers hardware module; In each kernel of processor, embed separate type logger module and recover hardware module,
Described separate type logger module, for recording the non-deterministic event information of corresponding kernel, by adopting the dependence of point-to-point, record is separated to memory contention daily record, in the first generation side of the answer party record dependence of consistency protocol, the rear generation side of dependence is recorded, to outside interruption logging interrupt type and interrupt address requesting party;
Described separate type daily record controller module, for setting up the mapping relations in log recording space and checkpointing;
Described recovery hardware module, in conjunction with the rollback recovery technology of separate type daily record and Deterministic Replay technology, completes the determinacy behind the checkpoint of transient fault and recovers.
2. the polycaryon processor transient fault recovery system based on separate type daily record according to claim 1, it is characterized in that, described separate type logger module comprises circulation and the sequence first side's of generation register Pred_IIC, blank(ing) instruction counter IIC, circulation occurs the side of generation register Succ_IIC, overflow register OVF after sequence occurs, N number ofly writes signature WF and N number ofly read the RF that signs; Described N is the interior check figure of processor;
There is the sequence first side's of generation register Pred_IIC in circulation, for marking non-deterministic event for the first side of generation;
Blank(ing) instruction counter IIC, for recording the blank(ing) instruction count value of adjacent uncertainty recording events;
The side of generation register Succ_IIC after circulation generation sequence is rear generation side for marking non-deterministic event;
Overflow register OVF, for marking the register size and the non-deterministic event type that determine to select recording events, first place is 0 expression memory contention, and first place is that 1 expression is interrupted, second is that 0 expression adopts 2B register to store, and second is that 1 expression adopts 4B register to store;
N number ofly write signature WF, for recording write conflict address set in N number of kernel memory contention, during N number of kernel interrupts, record interrupts jump address;
N number ofly read the RF that signs, for recording read conflict address set in N number of kernel memory contention, N number of kernel records address, interrupt spot in interrupting.
3. the polycaryon processor transient fault recovery system based on separate type daily record according to claim 2, is characterized in that, separate type daily record controller comprises N number ofly to be read signature address register and N number ofly writes signature address register;
N number ofly reading address register of signing, N number ofly reading the termination address of RF of signing for mapping;
N number ofly write signature address register, for mapping N number of termination address writing signature WF.
4. the polycaryon processor transient fault recovery system based on separate type daily record according to claim 3, is characterized in that, described recovery hardware module comprises N number of CP register, N number of CS register and an IIC register;
N number of CP register, for recording the count value of the wakeup message sending to a certain thread of other kernel;
N number of CS register, for recording the count value of the instruction of blocking because of a certain thread of other kernel;
An IIC register, for recording the blank(ing) instruction count value of adjacent uncertainty recording events.
5., based on the transient fault restoration methods of the polycaryon processor transient fault recovery system based on separate type daily record according to claim 4, it is characterized in that, described method comprises the steps:
Step 1: when hardware check point starts to store, adopts separate type logger module, reads signature address register and writes signature address register record non-deterministic event information;
Step 2: when recovering from hardware check point module, kernel reads sign address register and the information writing signature address register record, if the information that will read exceedes address, stops, otherwise performs step 3;
Step 3: read 16 information from memory contention daily record, if overflow register O walks F mark, needs reading 32 information; Walk at overflow register O in the information of F reading and judge it is that competition conflicts or external interrupt according to the first, if then compete conflict, perform step 4; If external interrupt, perform step 6;
Step 4: read overflow register O and walk F second information, according to type type judge be first the side of generation or after the side of generation; If the first side of generation, the count value of the CP register of kernel adds up, and after executing instruction, the count value of CP register is sent to all the other kernels as wakeup message; If after the side of generation, the count value of the CS register of kernel adds up, and performs this instruction again when by the time the wakeup message that sends of all the other kernels is identical with the count value of CS register;
Step 5: the value of the complete rear blank(ing) instruction counter IIC of instruction adds up, when after sending wakeup message or when receiving wakeup message and after executing with it corresponding instruction, kernel repeated execution of steps 2;
Step 6: read signature register and obtain interruption start address, again call the external unit of interruption, continue to perform from writing signature register address; Kernel repeated execution of steps 2.
6. the transient fault restoration methods of the polycaryon processor transient fault recovery system based on separate type daily record according to claim 5, it is characterized in that, the process of described step 1 comprises the steps:
Step one: when hardware check point module starts to store, the reading signature register and write signature register and all reset of separate type log control module; Separate type logger module starts to record non-deterministic event information; When conflict being detected for memory contention, perform step 2; When conflict being detected for external interrupt, perform step 5;
Step 2: blank(ing) instruction counter IIC adds 1, when the value of described IIC is not less than 2
14time, select 4B register to store and make marks at overflow register O step F, otherwise selecting 2B register to store; Overflow register O walk F store first place be labeled as 0, second as competition conflict type mark described in type comprise first generation side or after the side of generation, proceed to step 3;
Step 3: add address corresponding for the memory block that there is memory contention to all read signature register or write signature register, according to competition conflict type decided there is the sequence first side's of generation register Pred_IIC and circulation in circulation and the side of generation register Succ_IIC after sequence occurs do different marks, proceed to step 4;
Step 4: upgrade separate type log control module and read signature register or write the IIC termination address of signature register record, return step one;
Step 5; Blank(ing) instruction counter IIC adds 1, when the value of described IIC is not less than 2
14time, select 4B register to store and make marks at overflow register O step F, otherwise selecting 2B register storage overflow register O step F storage first place to be labeled as 1, proceeding to step 6;
Step 6: read the address that signature register preserves external interrupt, writes the address that signature register preserves redirect, proceeds to step 7;
Step 7: upgrade the termination address that separate type log control module is read signature register and write signature register record, return step one.
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