CN104657108B - A kind of management method and system of the event queue of the software simulator of microprocessor - Google Patents

A kind of management method and system of the event queue of the software simulator of microprocessor Download PDF

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Publication number
CN104657108B
CN104657108B CN201510081271.9A CN201510081271A CN104657108B CN 104657108 B CN104657108 B CN 104657108B CN 201510081271 A CN201510081271 A CN 201510081271A CN 104657108 B CN104657108 B CN 104657108B
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event
list item
pointer
list
linear linked
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CN104657108A (en
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罗浩
林绅文
卫冰洁
吴志刚
贺欣
杜雄杰
张树壮
李应博
王啸
刘成
袁媛
房婧
于贺威
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Beijing University of Posts and Telecommunications
National Computer Network and Information Security Management Center
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Beijing University of Posts and Telecommunications
National Computer Network and Information Security Management Center
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Abstract

The invention discloses a kind of management method and system of the event queue of the software simulator of microprocessor, overcome the shortcomings of that the efficiency of the event queue of the software simulator of microprocessor in the prior art is low.This method includes:Event queue is stored in circulation array;Multiple list items are included in the circulation array, each list item corresponds to a clock cycle of the software simulator;Each list item in the circulation array is corresponded with default linear linked list, the head pointer and tail pointer of each list item are respectively directed to the head element and tail element of corresponding linear linked list;Each linear linked list storage should be in the event of the clock cycle internal trigger representated by corresponding list item;Global Periodic pointer is pointed into the list item corresponding to present clock period;After a clock cycle simulation terminates, by the Global Periodic pointer one list item of advance.Embodiments of the invention all have very high efficiency in terms of event insertion, event query and event rejecting.

Description

A kind of management method and system of the event queue of the software simulator of microprocessor
Technical field
The present invention relates to the analogue technique of microprocessor, more particularly to a kind of event team of the software simulator of microprocessor The management method and system of row.
Background technology
When carrying out microprocessor Design, generally first various alternatives will be commented using software simulator Estimate.By carrying out software modeling to all parts, the function and sequential of accurate simulation microprocessor, can find to set quickly The defects of meter and falsehood.
In simulation process, those need the part of accurate simulated timing diagrams will produce it is substantial amounts of, there is certain trigger delay Operation.For example, memory hierarchy continually sends the operation of data cache accesses, after the operation is sent, reached by 2 cycles Data cache controller.If the data to be accessed, in data buffer storage, the data will return to after 12 clock cycle Memory hierarchy.
Described to simplify, this generic operation can use a four-tuple O<P,T,L,C>Represent.The meaning of the four-tuple For:Type is that T operation requests are produced by part P, and after L cycle, part C will receive the operation requests and carry out corresponding Processing.
For convenience of processing, above-mentioned four-tuple can once be deformed, be transformed into E<P,T,A,C>.New four-tuple Meaning is as follows:Type is that T operation requests are produced by part P, and in clock cycle A, part C will receive the operation requests and go forward side by side Row processing.This four-tuple E can be referred to as one " event ".
The a large amount of four-tuple events generated in simulation process are all stored in one or more event queue.
Simulator first checks for event queue, by comparing present clock period when each cycle simulation process starts Clock cycle A in number and event queue in four-tuple event, find out it is all should be in the event of this cycle internal trigger, and call should The part C of event is handled accordingly.
Caused four-tuple event E quantity in simulation process, with simulation scale and to part timing simulation required precision It is relevant.When carrying out simulating (such as chip multi-core simulation) on a large scale, and requiring higher to each part time sequence precision, each cycle production Event number that is raw and withering away will be very surprising.
To be rapidly found out in a huge event queue it is all should be in the event not a duck soup of some cycle internal trigger. If event queue implementation method is inefficient, then substantial amounts of simulated time will be consumed in the processing to event queue, This will have a strong impact on the operational efficiency of software simulator.
In the prior art, the implementation of event queue is more.
The implementation of the first event queue, it is to use array as event queue.For event insertion method, be by Newly-generated event E<P,T,A,C>It is directly appended to array afterbody.For event lookup method, be since event queue heads, Search whole array backward successively, find out and trigger all events that should be triggered in this cycle.And for event elimination method, then It is that the state-event of triggered mistake is set to engineering noise.
But using array as the mode of event queue, there is some shortcomings.
First, event queue size can not be learnt in advance.If the array opened up in advance is excessive, compares and waste internal memory money Source;If the array opened up in advance is too small, when caused event number exceedes event queue maximum capacity, simulation process will Pause.
Second:Search efficiency is relatively low.When array is very huge, finding out and trigger successively backward since array head should In the event of this cycle internal trigger, the efficiency of this inquiry is very low.For such case, a kind of improved method is fixed Shi Qingli array events, some events having occurred and that are rejected from array, only retain the validity event in array, so Can be with packed array length, but frequently array movement will bring larger overhead.
The implementation of second of event queue, it is to use linear linked list as event queue.For event insertion method, It is newly-generated event E<P,T,A,C>It is inserted directly into linear linked list afterbody.It is from linear chain for event lookup method Gauge outfit starts to search whole chained list backward successively, find out and trigger it is all should be in the event of this cycle internal trigger.And for thing Part elimination method, then it is to reject triggered event from linear linked list.
But using linear linked list as the mode of event queue, there is also some shortcomings.
First:For event rejecting, during due to finding an event every time, this method is just by the event from chained list Middle rejecting, so as to which linear linked list length is less than the array length in first method, the lookup of this method from this view is imitated Rate is higher than the foregoing implementation using array as event queue.But when chained list length is larger, search efficiency is still very It is low.
Second:When every time to linear linked list insertion event node, need temporarily to system application memory headroom;Every time from linear When event is rejected in chained list, it is also desirable to discharge the memory headroom of event node occupancy.And the application and release of memory headroom are all By operating system control, it is necessary to which the system of progress is called and a series of kernel processes process could be completed, this process extremely consumes When.Because each cycle all produces and withered away a large amount of events, therefore, this frequently application/releasing memory in simulation process Operation will have a strong impact on simulator operational efficiency.
The implementation of the third event queue, it is to use heap or binary tree as event queue.
Although the performance of heapsort or binary tree sort algorithm is better than the search performance of above two methods, Heap or this structure of binary tree are not appropriate for being used to realize event queue.This is primarily due to have in each clock cycle Substantial amounts of event insertion event queue, while there is substantial amounts of event to be removed from event queue again.There are new events to insert every time When entering or rejecting, it is required for being adjusted heap or binary tree, to ensure the characteristic of heap or binary tree, this will serious shadow Ring the operational efficiency of simulator.This cost frequently adjusted, to be far longer than benefit caused by its high-performance searching algorithm. Therefore, although can use, realize that the application of event queue is not universal using heap or binary tree.
The content of the invention
The technical problems to be solved by the invention are to overcome the thing of the software simulator of microprocessor in the prior art The low deficiency of the efficiency of part queue.
In order to solve the above-mentioned technical problem, embodiments of the invention provide firstly a kind of software simulator of microprocessor Event queue management method, including:Event queue is stored in circulation array;Multiple tables are included in the circulation array , each list item corresponds to a clock cycle of the software simulator;By each list item in the circulation array with presetting Linear linked list correspond, the head pointer and tail pointer of each list item are respectively directed to the head element and tail member of corresponding linear linked list Element;Each linear linked list storage should be in the event of the clock cycle internal trigger representated by corresponding list item;By Global Periodic pointer Point to the list item corresponding to present clock period;After a clock cycle simulation terminates, the Global Periodic pointer is advanced One list item.
Preferably, it is true according to the maximum trigger delay clock cycle of the event generated in the software simulator simulation process The size of the fixed circulation array.
Preferably, this method includes:In searched events, the current entry that the Global Periodic pointer points to is detected;If The head pointer in current entry pointed by the Global Periodic pointer is not sky, then sequentially triggers the linear chain that head pointer points to All events in table.
Preferably, this method includes:When inserting new events, the new thing is determined according to the triggering cycle of the new events Target list item corresponding to part;The new events are inserted into the linear linked list corresponding to the target list item.
Preferably, this method includes:The event node rejected from the event queue is stored in default free pool.
Preferably, this method includes:When inserting new events, the free pool is checked;The free pool is space-time, application Internal memory and the target list item according to corresponding to the triggering cycle of the new events determines the new events, the new events are inserted Into the linear linked list corresponding to the target list item;The free pool is not space-time, is taken at the head pointer of the free pool Go out an idle event node and store the new events.
Preferably, this method includes:After the simulation of present clock period terminates, the present clock period is corresponded into list item Corresponding linear linked list is extractd from head and chain enters the afterbody of the free pool, and the present clock period is corresponded into list item Head pointer and tail pointer be set to sky.
Embodiments of the invention additionally provide a kind of management system of the event queue of the software simulator of microprocessor, bag Include:Memory cell, it is arranged to event queue being stored in circulation array;Multiple list items are included in the circulation array, each One clock cycle of the corresponding software simulator of list item;Corresponding unit, being arranged to will be every in the circulation array Individual list item corresponds with default linear linked list, and the head pointer and tail pointer of each list item are respectively directed to corresponding linear linked list Head element and tail element;Each linear linked list storage should be in the event of the clock cycle internal trigger representated by corresponding list item;Refer to To unit, it is arranged to pointing to Global Periodic pointer into the list item corresponding to present clock period;And when a clock cycle mould After plan terminates, by the Global Periodic pointer one list item of advance.
Preferably, the system includes:Culling unit, set and be stored in the event node rejected from the event queue In default free pool.
Preferably, the size for the circulation array that the array setting unit is set, according to the software simulator mould The maximum trigger delay clock cycle of the event generated during plan determines.
Compared with prior art, the event queue realization method and system of the software simulator of microprocessor of the invention Embodiment, all there is very high efficiency in terms of event insertion, event query and event rejecting, can effectively reduce for handling The time that event queue is spent.Moreover, the scale of the microprocessor of simulation and the requirement height of time sequence precision, not shadow Ring the speed and efficiency of simulation.
Search efficiency is high when in use for embodiments of the invention, it is not necessary to which special search operation can finds out a week All events that should be triggered in phase.Embodiments of the invention insert efficiency high when in use only to be needed according to indexing into line Property chained list insertion operation can complete event insertion.Overhead is small when in use for embodiments of the invention, it is not necessary to frequently Ground application/releasing memory space, can dramatically speed up analog rate.Embodiments of the invention are rejected using event delay when in use Technology, after each simulation cycle terminates, this cycle whole event linear linked list is disposably rejected, a thing is rejected compared to each For part, take less, it is more efficient.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification Obtain it is clear that or being understood by implementing technical scheme.The purpose of the present invention and other advantages can by Specifically noted structure and/or flow are realized and obtained in specification, claims and accompanying drawing.
Brief description of the drawings
Accompanying drawing is used for providing further understanding technical scheme or prior art, and constitution instruction A part.Wherein, the accompanying drawing for expressing the embodiment of the present invention is used for the technical side for explaining the present invention together with embodiments of the present invention Case, but do not form the limitation to technical solution of the present invention.
Fig. 1 is the schematic flow sheet of the management method of the event queue of the software simulator of the microprocessor of the present invention.
Fig. 2 is the principle schematic of the circulation array in embodiments of the invention.
Fig. 3 is the principle schematic of the free pool in embodiments of the invention.
Fig. 4 is the organigram of the management system of the event queue of the software simulator of the microprocessor of the present invention.
Embodiment
Embodiments of the present invention are described in detail below with reference to drawings and Examples, and how the present invention is applied whereby Technological means solves technical problem, and the implementation process for reaching relevant art effect can fully understand and implement according to this.This hair Each feature in bright embodiment and embodiment, can be combined with each other under the premise of not colliding, the technical scheme formed Within protection scope of the present invention.
The step of method of embodiments of the invention shown by accompanying drawing includes be able to can hold in such as one group of computer Performed in the computer system of row instruction.Also, although the method for embodiments of the invention shows that logic is suitable in flow charts Sequence, but in some cases, the method for embodiments of the invention can also be with different from shown in order shown in the drawings execution The step of going out or describing.
As shown in figure 1, the management method of the event queue of the software simulator of the microprocessor of the present invention, main to include such as Lower step.
Step S110, event queue is stored in circulation array.Multiple list items, each list item are included in the circulation array The clock cycle of one of corresponding software simulator.
Step S120, each list item in the circulation array and default linear linked list are corresponded.Each list item Head pointer and tail pointer are respectively directed to the head element and tail element of corresponding linear linked list.Each linear linked list storage should be corresponding The event of clock cycle internal trigger representated by list item.
Step S130, Global Periodic pointer is pointed into the list item corresponding to present clock period.
Step S140, after a clock cycle simulation terminates, by Global Periodic pointer one list item of advance.
As shown in Fig. 2 event queue is stored using circulation array.Embodiments of the invention, according to software simulator The maximum trigger delay clock cycle of event generated in simulation process, to determine the size of the circulation array.
Assuming that the maximum trigger delay of the event generated in simulation process is m clock cycle, then the array size is set to m +1;M is the integer more than or equal to 1.Each list item corresponds to a clock cycle of software simulator in the array, such as:Generation Table item index index=(n-1) mod (m+1) in table nth clock cycle, n are more than or equal to 1 and are less than or equal to m.
Each list item is also associated with a linear linked list, and the linear linked list is used for storage should be corresponding to the list item The event of clock cycle internal trigger.A head pointer (head) and tail pointer (tail) are also included in each list item, wherein head refers to Pin points to the head element of the linear linked list, and tail pointer points to the tail element of the linear linked list.
The event queue list item for representing the present day analog cycle is pointed to using Global Periodic pointer.Simulated when a clock cycle After end, Global Periodic pointer one list item of advance, the list item for representing the next cycle is pointed to.
Embodiments of the invention use free pool as shown in Figure 3, to store the event for rejecting to get off from event queue Node.When free pool not space-time, newly-generated event can utilize idle event node in free pool without to system weight New application storage allocation.
For embodiments of the invention in system initialization, allocated size is m+1 event queue array, and m is simulation process The quantity of the clock cycle of the maximum trigger delay of the event of middle generation.Global Periodic pointer is pointed to first of event queue List item.Free pool head pointer is set to sky.
Searched for event, (simulation cycle n), the event that Global Periodic pointer points to is detected first when simulating and starting Queue entry.If the head pointer in current entry pointed by Global Periodic pointer is not sky, it is signified sequentially to trigger head pointer To linear linked list in all events.If head pointer is sky, show there is no any event to be activated in the cycle.
Inserted for event, if generating new events E in simulation cycle n<P,T,A,C>, then first according to event E when Clock cycle A calculates the new events and should be inserted into the linear linked list in event queue pointed by which list item.
Event queue table item index index calculating is carried out according to following expression:
Index=(A-1) mod (m+1) formula (1)
Then new events E is inserted into the linear linked list pointed by the head pointer of calculated list item.
During insertion, free pool is first checked for.If free pool is sky, to system application storage allocation, new events are stored in, so The new events are inserted from chained list afterbody by the tail pointer of the list item calculated afterwards., can be with if free pool is not sky An idle event node is taken out directly at free pool head pointer to store new events, the tail for passing through calculated list item refers to Pin inserts new events from chained list afterbody.
For event reject, after clock cycle n simulation work all terminates, it is all should cycle n planted agent trigger Event, which is processed, to be finished, and now can directly extract down the linear linked list that the current entry head pointer points to from head Come, chain enters the afterbody of free pool.Then the pointer end to end for setting the list item is NULL (sky).It is this once to reject whole chained list Method is obvious more efficient than just being eliminated immediately after often one event of triggering, it is possible to reduce most pointer operations, shows Write the operational efficiency for improving simulator.
As shown in figure 4, the management system of the event queue of the software simulator of the microprocessor of the present invention, is mainly included Memory cell 410, corresponding unit 420 and sensing unit 430.
Memory cell 410, it is arranged to event queue being stored in circulation array;Multiple tables are included in the circulation array , a clock cycle of the corresponding software simulator of each list item;
Corresponding unit 420, it is connected with memory cell 410, is arranged to each list item in the circulation array with presetting Linear linked list correspond, the head pointer and tail pointer of each list item are respectively directed to the head element and tail member of corresponding linear linked list Element;Each linear linked list storage should be in the event of the clock cycle internal trigger representated by corresponding list item;
Unit 430 is pointed to, is connected with memory cell 410 and corresponding unit 420, is arranged to point on Global Periodic pointer and works as List item corresponding to the preceding clock cycle;And after a clock cycle simulation terminates, by Global Periodic pointer advance one Individual list item.
The size for the circulation array that the array setting unit is set, is mainly generated according in software simulator simulation process Maximum trigger delay clock cycle of event determine.Assuming that the maximum trigger delay of the event generated in simulation process is m The individual clock cycle, then the array size be set to m+1;M is the integer more than or equal to 1.
The management system of the event queue of the software simulator of the microprocessor of the present invention, can also include searching unit, It is arranged to detect the current entry that Global Periodic pointer points to.If the head in current entry pointed by Global Periodic pointer refers to Pin is not sky, then sequentially triggers all events in the linear linked list that head pointer points to.
The management system of the event queue of the software simulator of the microprocessor of the present invention, it can also include being used to insert newly The insertion unit of event.Unit is inserted when inserting new events, according to corresponding to the triggering cycle of new events determines the new events Target list item.Then the new events are inserted into the linear linked list corresponding to the target list item.
As shown in figure 4, the system can also include culling unit 440, it is connected with memory cell 410, setting will be from event The event node rejected in queue is stored in default free pool.
In the case of available free pond, insertion unit first checks for free pool when inserting new events.It is sky in free pool When, determine new events to system application internal memory and according to triggering cycles of new events corresponding to target list item, by the new thing Part is inserted into the linear linked list corresponding to target list item.If free pool is not sky, taken out at the head pointer of free pool One idle event node stores the new events.
After the simulation of present clock period terminates, the culling unit corresponds to present clock period linear corresponding to list item Chained list enters the afterbody of the free pool from head excision and chain, and present clock period is corresponded to the head pointer and tail pointer of list item It is set to sky.
Embodiments of the invention use circulation array to be touched as event queue according to the maximum of all events in simulation process Hair delay period m sets array size to be set to m+1, it is ensured that all events generated in simulation process can access place Reason.Therefore, event queue size of the invention can predefine.Size can not be predicted by overcoming event queue in the prior art Deficiency.
Embodiments of the invention insert it into the linear of corresponding list item for newly-generated event according to its trigger delay In chained list.In each cycle, only need to sequentially activate linear pointed by the event queue list item of Global Periodic pointer sensing Chained list can, it is not necessary to search all linear linked lists, significantly improve search efficiency.
Embodiments of the invention use event delay occluding technique, substantially increase rejecting efficiency.Specifically, in each mould After quasi-periodicity terminates, this cycle whole event linear linked list is disposably rejected, substantially increases the efficiency of event rejecting.
The event node that embodiments of the invention were once distributed using free pool caching, it is not necessary to continually apply/release Internal memory is put, the operation of application distribution/releasing memory block is greatly reduced, analog rate can be significantly increased.
Those skilled in the art should be understood that each part for the system that the above-mentioned embodiment of the present invention is provided, And each step in method, they can be concentrated on single computing device, or are distributed in multiple computing device institutes group Into network on.Alternatively, they can be realized with the program code that computing device can perform.It is thus possible to they are deposited Storage performed in the storage device by computing device, either they are fabricated to respectively each integrated circuit modules or by it In multiple modules or step be fabricated to single integrated circuit module to realize.So, the present invention is not restricted to any specific Hardware and software combine.
Although disclosed herein embodiment as above, described content be only readily appreciate technical solution of the present invention And the embodiment used, it is not limited to the present invention.Technical staff in any art of the present invention, this is not being departed from On the premise of the disclosed spirit and scope of invention, any modification and change can be carried out in the form and details of implementation, But the scope of patent protection of the present invention, still should be subject to the scope of the claims as defined in the appended claims.

Claims (6)

1. a kind of management method of the event queue of the software simulator of microprocessor, including:
Event queue is stored in circulation array;Multiple list items are included in the circulation array, each list item corresponds to described soft One clock cycle of part simulator;
Each list item in the circulation array is corresponded with default linear linked list, the head pointer and tail of each list item refer to Pin is respectively directed to the head element and tail element of corresponding linear linked list;Each linear linked list storage should be representated by corresponding list item The event of clock cycle internal trigger;
Global Periodic pointer is pointed into the list item corresponding to present clock period;
After a clock cycle simulation terminates, by the Global Periodic pointer one list item of advance;
The event node rejected from the event queue is stored in default free pool;
Wherein:According to determining the maximum trigger delay clock cycle of the event generated in the software simulator simulation process Circulate the size of array.
2. according to the method for claim 1, wherein, this method includes:
In searched events, the current entry that the Global Periodic pointer points to is detected;
If the head pointer in current entry pointed by the Global Periodic pointer is not sky, sequentially trigger what head pointer pointed to All events in linear linked list.
3. according to the method for claim 1, wherein, this method includes:
When inserting new events, the target list item according to corresponding to the triggering cycle of the new events determines the new events;Will The new events are inserted into the linear linked list corresponding to the target list item.
4. according to the method for claim 1, wherein, this method includes:
When inserting new events, the free pool is checked;
The free pool is space-time, applies for internal memory and according to corresponding to the triggering cycle of the new events determines the new events Target list item, the new events are inserted into the linear linked list corresponding to the target list item;
The free pool is not space-time, and an idle event node is taken out at the head pointer of the free pool and stores the new thing Part.
5. the method according to claim 1 or 4, wherein, this method includes:
After the simulation of present clock period terminates, the present clock period is corresponded into linear linked list corresponding to list item from head Extract and chain enters the afterbody of the free pool, and the present clock period is corresponded into the head pointer of list item and tail pointer is set to It is empty.
6. a kind of management system of the event queue of the software simulator of microprocessor, including:
Memory cell, it is arranged to event queue being stored in circulation array;Multiple list items are included in the circulation array, each One clock cycle of the corresponding software simulator of list item;
Corresponding unit, it is arranged to correspond each list item in the circulation array with default linear linked list, Mei Gebiao The head pointer and tail pointer of item are respectively directed to the head element and tail element of corresponding linear linked list;Each linear linked list storage should be The event of clock cycle internal trigger representated by corresponding list item;
Unit is pointed to, is arranged to pointing to Global Periodic pointer into the list item corresponding to present clock period;And when a clock After cycle simulation terminates, by the Global Periodic pointer one list item of advance;
Culling unit, it is arranged to the event node rejected from the event queue being stored in default free pool;And
Array setting unit, it is arranged to set the size of the circulation array, according to raw in the software simulator simulation process Into event the maximum trigger delay clock cycle determine.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0733984A1 (en) * 1995-03-24 1996-09-25 Sun Microsystems, Inc. Cycle-based event-driven simulator
CN102523030A (en) * 2011-11-25 2012-06-27 中国空间技术研究院 Communication satellite effective load test system simulation platform
CN102760176A (en) * 2011-04-29 2012-10-31 无锡江南计算技术研究所 Hardware transaction level simulation method, engine and system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8738350B2 (en) * 2010-03-04 2014-05-27 Synopsys, Inc. Mixed concurrent and serial logic simulation of hardware designs

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0733984A1 (en) * 1995-03-24 1996-09-25 Sun Microsystems, Inc. Cycle-based event-driven simulator
CN102760176A (en) * 2011-04-29 2012-10-31 无锡江南计算技术研究所 Hardware transaction level simulation method, engine and system
CN102523030A (en) * 2011-11-25 2012-06-27 中国空间技术研究院 Communication satellite effective load test system simulation platform

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