CN104638029A - Capacitor and manufacturing method thereof - Google Patents
Capacitor and manufacturing method thereof Download PDFInfo
- Publication number
- CN104638029A CN104638029A CN201310571314.2A CN201310571314A CN104638029A CN 104638029 A CN104638029 A CN 104638029A CN 201310571314 A CN201310571314 A CN 201310571314A CN 104638029 A CN104638029 A CN 104638029A
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- China
- Prior art keywords
- oxide layer
- electric capacity
- silicon
- silicon nitride
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
The invention discloses a capacitor. The capacitor is characterized in that a lower electrode plate is composed of a silicon substrate doped; a medium layer is composed of a bottom thermal oxide layer, a silicon nitride layer and a top thermal oxide layer; the top thermal oxide layer is made by thermally oxidizing the surface of the silicon nitride layer; the upper electrode plate is made of doped polycrystalline silicon formed on the surface of the top thermal oxide layer. The invention further discloses a manufacturing method of the capacitor. The capacitor and the manufacturing method thereof have the advantages that unit area capacitance is improved, high breakdown voltage is kept and the area of a capacitor device is reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of electric capacity; The invention still further relates to a kind of manufacture method of electric capacity.
Background technology
Reduce the power that circuit area is a kind of economy to microelectronic revolution, the current densities of integrated circuit or chip constantly increases because of reducing of size of circuit.Along with increasing element is designed within integrated circuit, the complexity of integrated circuit can increase gradually, therefore possess stronger functional, a kind of passive component be wherein included into gradually in many integrated circuits is capacitor, it generally includes the material of arranged stacked, the top of being made up of electric conducting material and bottom conductive electrode is at least comprised in material, and the intermediate insulating layer be made up of dielectric material.
The dielectric material of present electric capacity is generally divided into two kinds, and a kind of is the material of low-k, and as silicon dioxide, silicon dioxide generally adopts thermal oxidation technology to grow or adopts the growth of high temperature oxide deposition (HTO) technique; Another kind is the material of high-k, as silicon nitride.The general puncture voltage of electric capacity of advanced low-k materials is high, but capacitance is lower; The general capacitance of material electric capacity of high-k is high, but puncture voltage is lower.So high-breakdown-voltage, large capacitance capacitor just necessary enlarged-area will be realized.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of electric capacity, can improve unit-area capacitance value and keep high breakdown voltage simultaneously, can reduce capacitor element area.For this reason, the present invention also provides a kind of manufacture method of electric capacity.
For solving the problems of the technologies described above, electric capacity provided by the invention comprises:
Bottom crown, is made up of the silicon substrate adulterated, and the silicon of described silicon substrate is monocrystalline silicon.
Dielectric layer, be made up of Base Heat oxide layer, silicon nitride layer and top thermal oxide layer, described Base Heat oxide layer is formed by carrying out thermal oxidation to the surface of described silicon substrate, described silicon nitride layer is formed at described Base Heat oxide layer surface, and described top thermal oxide layer is formed by carrying out thermal oxidation to the surface of described silicon nitride layer.
Top crown, is made up of the doped polycrystalline silicon being formed at thermal oxide layer surface, described top.
Further improvement is, the adulterate body concentration of described bottom crown is 1E18cm
-3~ 1E20cm
-3.
Further improvement is, the thickness of described Base Heat oxide layer is 100 dust ~ 200 dusts.
Further improvement is, the thickness of described silicon nitride layer is more than 150 dusts, and the thickness of described top thermal oxide layer is 20 dust ~ 50 dusts.
For solving the problems of the technologies described above, the manufacture method of electric capacity provided by the invention comprises the steps:
Step one, carry out ion implantation in a silicon substrate and form the bottom crown of electric capacity, the silicon of described silicon substrate is monocrystalline silicon.
Step 2, described surface of silicon carried out to thermal oxidation and form Base Heat oxide layer.
Step 3, form silicon nitride layer on described Base Heat oxide layer surface.
Step 4, the surface of described silicon nitride layer carried out to thermal oxidation and form top thermal oxide layer; The dielectric layer of described electric capacity is made up of described Base Heat oxide layer, described silicon nitride layer and described top thermal oxide layer.
Step 5, at described top thermal oxide layer surface deposition polysilicon, and described polysilicon to be adulterated.
Step 6, to doping after described polysilicon carry out the top crown that chemical wet etching forms described electric capacity, form described electric capacity by described bottom crown, described dielectric layer and described top crown.
Further improvement is, the adulterate body concentration of the described bottom crown formed after the ion implantation in step one is 1E18cm
-3~ 1E20cm
-3; Carry out annealing after ion implantation to activate, or adopt the thermal process of the thermal oxidation technology in step 2 and step 4 to carry out annealing activation.
Further improvement is, the thermal oxidation in step 2 and step 4 is all carried out in boiler tube.
Further improvement is, the thickness of described Base Heat oxide layer is 100 dust ~ 200 dusts.
Further improvement is, the thickness of described silicon nitride layer is more than 150 dusts, and the thickness of described top thermal oxide layer is 20 dust ~ 50 dusts.
Further improvement is, the described polysilicon in step 5 be doped to doping in place; Or the doping of the described polysilicon in step 5 adopts ion implantation to adulterate, and adopts rapid thermal annealing to activate after the ion implantation of described polysilicon.
Top and the bottom of the dielectric layer of electric capacity of the present invention all adopt silica material, and silica material has lower dielectric constant, lower material stress and good and monocrystalline silicon or polysilicon adhesion, thus can improve the puncture voltage of electric capacity; The intermediate layer of the dielectric layer of electric capacity of the present invention adopts silicon nitride layer, silicon nitride has higher dielectric constant, the unit-area capacitance value of device can be improved, so the present invention can obtain higher puncture voltage while maintenance same units area capacitance value, or the capacitance of higher unit are is obtained when keeping same breakdown voltage, thus capacitor element area can be reduced, improve the integrated level of device.In addition, top of the present invention and bottom oxidization layer can be grown by the thermal oxidation technology of boiler tube, and the silicon oxide thickness consistency of formation is good, so the present invention can also improve the consistency of electric capacity.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of embodiment of the present invention electric capacity;
Fig. 2 A-Fig. 2 D is the capacitance structure schematic diagram in each step of embodiment of the present invention method.
Embodiment
As shown in Figure 1, be the structural representation of embodiment of the present invention electric capacity; Embodiment of the present invention electric capacity comprises:
Bottom crown 2, is made up of the silicon substrate 1 adulterated, also namely by the doped region in described silicon substrate 1 as well region 2 form as described in bottom crown 2.The silicon of described silicon substrate 1 is monocrystalline silicon.Be preferably, the adulterate body concentration of described bottom crown 2 is 1E18cm
-3~ 1E20cm
-3.
Dielectric layer, is made up of Base Heat oxide layer 3, silicon nitride layer 4 and top thermal oxide layer 5, and also namely described dielectric layer is an ONO layer.Described Base Heat oxide layer 3 is formed by carrying out thermal oxidation to the surface of described silicon substrate 1, and described silicon nitride layer 4 is formed at described Base Heat oxide layer 3 surface, and described top thermal oxide layer 5 is formed by carrying out thermal oxidation to the surface of described silicon nitride layer 4.Be preferably, the thickness of described Base Heat oxide layer 3 is 100 dust ~ 200 dusts.The thickness of described silicon nitride layer 4 is more than 150 dusts, and the thickness of described top thermal oxide layer 5 is 20 dust ~ 50 dusts.
Top crown 6, is made up of the doped polycrystalline silicon being formed at thermal oxide layer 5 surface, described top.
As shown in Fig. 2 A to Fig. 2 D, it is the capacitance structure schematic diagram in each step of embodiment of the present invention method.The manufacture method of embodiment of the present invention electric capacity comprises the steps:
Step one, as shown in Figure 2 A, in silicon substrate 1, carry out the bottom crown 2 that ion implantation forms electric capacity, the silicon of described silicon substrate 1 is monocrystalline silicon.Be preferably, the adulterate body concentration of the described bottom crown 2 formed after ion implantation is 1E18cm
-3~ 1E20cm
-3.Carry out annealing after ion implantation to activate; Or do not adopt separately annealing process to activate, but adopt the thermal process of the thermal oxidation technology in subsequent step two and step 4 to carry out annealing activation.
Step 2, as shown in Figure 2 B, carry out carrying out thermal oxidation to described silicon substrate 1 surface and form Base Heat oxide layer 3, thermal oxidation is carried out in boiler tube.The thickness of described Base Heat oxide layer 3 is 100 dust ~ 200 dusts.
Step 3, as shown in Figure 2 C, forms silicon nitride layer 4 on described Base Heat oxide layer 3 surface.The thickness of described silicon nitride layer 4 is more than 150 dusts.
Step 4, as shown in Figure 2 D, carry out thermal oxidation to the surface of described silicon nitride layer 4 and form top thermal oxide layer 5, thermal oxidation is carried out in boiler tube; The thickness of described top thermal oxide layer 5 is 20 dust ~ 50 dusts.Be made up of the dielectric layer of described electric capacity described Base Heat oxide layer 3, described silicon nitride layer 4 and described top thermal oxide layer 5, as can be seen from Fig. 2 D, described dielectric layer is ONO structure.
Step 5, as shown in Figure 1, at described top thermal oxide layer 5 surface deposition polysilicon, and described polysilicon to be adulterated.Described polysilicon be doped to doping in place; Or the doping of described polysilicon adopts ion implantation to adulterate, and adopts rapid thermal annealing to activate after the ion implantation of described polysilicon.Described polysilicon be doped to heavy doping, can make the top crown 6 of follow-up formation can and metal form good ohmic contact.
Step 6, as shown in Figure 1, carries out to the described polysilicon after doping the top crown 6 that chemical wet etching forms described electric capacity, forms described electric capacity by described bottom crown 2, described dielectric layer and described top crown 6.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. an electric capacity, is characterized in that, comprising:
Bottom crown, is made up of the silicon substrate adulterated, and the silicon of described silicon substrate is monocrystalline silicon;
Dielectric layer, be made up of Base Heat oxide layer, silicon nitride layer and top thermal oxide layer, described Base Heat oxide layer is formed by carrying out thermal oxidation to the surface of described silicon substrate, described silicon nitride layer is formed at described Base Heat oxide layer surface, and described top thermal oxide layer is formed by carrying out thermal oxidation to the surface of described silicon nitride layer;
Top crown, is made up of the doped polycrystalline silicon being formed at thermal oxide layer surface, described top.
2. electric capacity as claimed in claim 1, is characterized in that: the adulterate body concentration of described bottom crown is 1E18cm
-3~ 1E20cm
-3.
3. electric capacity as claimed in claim 1, is characterized in that: the thickness of described Base Heat oxide layer is 100 dust ~ 200 dusts.
4. electric capacity as claimed in claim 1, it is characterized in that: the thickness of described silicon nitride layer is more than 150 dusts, the thickness of described top thermal oxide layer is 20 dust ~ 50 dusts.
5. a manufacture method for electric capacity, is characterized in that, comprises the steps:
Step one, carry out ion implantation in a silicon substrate and form the bottom crown of electric capacity, the silicon of described silicon substrate is monocrystalline silicon;
Step 2, described surface of silicon carried out to thermal oxidation and form Base Heat oxide layer;
Step 3, form silicon nitride layer on described Base Heat oxide layer surface;
Step 4, the surface of described silicon nitride layer carried out to thermal oxidation and form top thermal oxide layer; The dielectric layer of described electric capacity is made up of described Base Heat oxide layer, described silicon nitride layer and described top thermal oxide layer;
Step 5, at described top thermal oxide layer surface deposition polysilicon, and described polysilicon to be adulterated;
Step 6, to doping after described polysilicon carry out the top crown that chemical wet etching forms described electric capacity, form described electric capacity by described bottom crown, described dielectric layer and described top crown.
6. method as claimed in claim 5, is characterized in that: the adulterate body concentration of the described bottom crown formed after the ion implantation in step one is 1E18cm
-3~ 1E20cm
-3; Carry out annealing after ion implantation to activate, or adopt the thermal process of the thermal oxidation technology in step 2 and step 4 to carry out annealing activation.
7. method as claimed in claim 5, is characterized in that: the thermal oxidation in step 2 and step 4 is all carried out in boiler tube.
8. method as claimed in claim 5, is characterized in that: the thickness of described Base Heat oxide layer is 100 dust ~ 200 dusts.
9. method as claimed in claim 5, it is characterized in that: the thickness of described silicon nitride layer is more than 150 dusts, the thickness of described top thermal oxide layer is 20 dust ~ 50 dusts.
10. method as claimed in claim 5, is characterized in that: the described polysilicon in step 5 be doped to doping in place; Or the doping of the described polysilicon in step 5 adopts ion implantation to adulterate, and adopts rapid thermal annealing to activate after the ion implantation of described polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310571314.2A CN104638029A (en) | 2013-11-13 | 2013-11-13 | Capacitor and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310571314.2A CN104638029A (en) | 2013-11-13 | 2013-11-13 | Capacitor and manufacturing method thereof |
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|---|---|
| CN104638029A true CN104638029A (en) | 2015-05-20 |
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|---|---|---|---|
| CN201310571314.2A Pending CN104638029A (en) | 2013-11-13 | 2013-11-13 | Capacitor and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020020890A1 (en) * | 2000-08-09 | 2002-02-21 | Josef Willer | Memory cell and production method |
| CN1909251A (en) * | 2005-08-04 | 2007-02-07 | 旺宏电子股份有限公司 | Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer |
| CN102097312A (en) * | 2010-11-16 | 2011-06-15 | 无锡中微晶园电子有限公司 | Process for growing ONO (oxide-nitride-oxide) capacitor structure |
| US20120223380A1 (en) * | 2000-08-14 | 2012-09-06 | Sandisk 3D Llc | Dense arrays and charge storage devices |
-
2013
- 2013-11-13 CN CN201310571314.2A patent/CN104638029A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020020890A1 (en) * | 2000-08-09 | 2002-02-21 | Josef Willer | Memory cell and production method |
| US20120223380A1 (en) * | 2000-08-14 | 2012-09-06 | Sandisk 3D Llc | Dense arrays and charge storage devices |
| CN1909251A (en) * | 2005-08-04 | 2007-02-07 | 旺宏电子股份有限公司 | Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer |
| CN102097312A (en) * | 2010-11-16 | 2011-06-15 | 无锡中微晶园电子有限公司 | Process for growing ONO (oxide-nitride-oxide) capacitor structure |
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Application publication date: 20150520 |