CN104636271A - Method for having access to data stored in instruction/address register device - Google Patents

Abstract

Data are transmitted to a device connected with a data bus through a cross-address bus, and the device connected to the data bus reads the data and then reads a register not connected to the data bus. The register resides in the register device which is connected to a storage device through the address bus, wherein the storage device is connected to an address bus and the data bus. A main processor triggers the register device to transmit information to the register in the storage device through the address bus, and then reads the information from the register of the storage device.

Description

The data stored in visit order/address register device

Technical field

In general, embodiments of the invention relate to storage arrangement, and more particularly, relate to the data of accessing in storage address or command line and storing in register setting.

Background technology

The disclosed part of patent document can comprise the data being subject to copyright protection.Copyright owner not reproduction by anyone's copy patent file or patent is open, this is because it appears at patent and trademark office patent file or in recording, in any case but still retain all literary propertys in other side.Copyright notice is applicable to following and all data described in accompanying drawing and the following stated any software: literary property 2011, and intel corporation, literary property owns, and must not reprint.

Some memory sub-system comprises register setting, and described register setting is connected to address or the command line of memory sub-system, to store to the order in memory sub-system or to configure relevant value.In a traditional way, there is not the good way of accessing this data.Therefore, data (data such as, stored in mode register) are in a register stored or in order to debug or other data in error detection object and the data (data stored in such as C/A register setting) that store or another this register can not be easy to access in order to configuration purpose.

An option of accessing described data is the connections of the data bus being included in memory sub-system.This option is very expensive in the wiring of hardware (additional pin) and trace.Another option makes device be in special state (such as management mode), temporarily to allow existing bus or other repurposing connected.This option causes slow connection, does not allow the ongoing operation of device, and still can require additional firmware.Another option is to provide the outer serial line interface of band on register setting, and this also increases hardware and wiring cost.Therefore, current do not exist the traditional mechanism allowing to require, adopt the data stored in the register of standard commands accessing memory subsystem with minimal hardware.

Support the accompanying information being provided for replacing at register setting place register and the logic verified in storage arrangement place execution bad parity compared with the memory sub-system increase of new standard of DDR (Double Data Rate) storer.Such as, DDR4 (standard when submitting to the application still in formulation) will allow command/address (C/A) bad parity outside DRAM (dynamic RAM) device to verify.But when not reading the mechanism of bad parity, order still will send to DRAM to perform, this can cause will hang up calculation element (such as " blue screen " situation).

Accompanying drawing explanation

The discussion comprised the accompanying drawing with the explanation provided as the realization example of embodiments of the invention is below described.Accompanying drawing should be understood to as an example instead of limits.Formulation to one or more " embodiment " used herein will be understood to the specific features, structure or the characteristic that comprise during describing at least one of the present invention realizes.Therefore, the word such as such as " in one embodiment " or " in an alternative embodiment " etc. occurred herein describes each embodiment of the present invention and realization, but differ establish a capital refer to same embodiment.But they also not necessarily repel mutually.

Fig. 1 is the block diagram of an embodiment of the system with memory sub-system, and described memory sub-system has via address or command line but not the addressable register of data bus.

Fig. 2 is the block diagram of an embodiment of the system with memory sub-system, and described memory sub-system has register between memory controller and DRAM device.

Fig. 3 is the block diagram of an embodiment of the system with memory sub-system, and described memory sub-system has via address or command line but not the addressable register of data bus and via address or command line and all addressable storage arrangement of data bus.

Fig. 4 is the block diagram of an embodiment of the system with memory sub-system, and described memory sub-system has register setting between memory controller and DRAM device, and wherein this register setting performs parity checking.

Fig. 5 is for the process flow diagram from an embodiment of the process of visit data via address or command line but not in the addressable register of data bus.

Fig. 6 is the block diagram of an embodiment of computing system, and the register of wherein said memory sub-system is accessed indirectly by primary processor.

Fig. 7 is the block diagram of an embodiment of mobile device, and the register of wherein said memory sub-system is accessed indirectly by primary processor.

Here is the description to some details and realization, and comprising the description to accompanying drawing, accompanying drawing can illustrate the part or all of of the embodiment of the following stated, and discusses other possible embodiment or the realization of inventive concept provided in this article.Thering is provided the general introduction to the embodiment of the present invention below, is the more detailed description of carrying out with reference to accompanying drawing afterwards.

Embodiment

As described herein, the register in memory sub-system is connected to address bus.Will be understood that, mention address bus and can represent the bus of only carrying address or the bus of carrying address and order.Many address buss are address or command line, this is because the combination of address, order or address and order is all sent by these buses.Mention " address bus " herein will be understood to represent address or command line.Therefore, register is via address or command line but not data bus is addressable.Data can be read in the following way: across address bus, data are passed to the device be connected with data bus from register, from described device, read described data (even if register is not connected to data bus) by data bus.Register resides in and is connected in the register setting of storage arrangement (described storage arrangement is not only connected to address bus but also is connected to data bus) via address bus.The register transmission of information that primary processor trigger register device is set up to memory device by address bus.Then primary processor reads information from the register of storage arrangement.By this reading mechanism, " indirectly " of register reads is possible.

This reading mechanism and any register setting (such as mode register or the bad parity check register device) cooperating being coupled to address bus.Therefore, specific memory is configured in the normal operating time run duration of master operating system is addressable.In addition, likely access the data relevant with the particular command or address that cause bad parity, this can prevent the fault of access to main system and main system.Therefore, read by described the Fault recovery that mechanism carrys out executive system when likely there is mistake in memory command.

Proposed DDR4 system is applicable to the indirect reading of register.DDR4 specifies and can perform the inspection of C/A bad parity and the register setting of memory error order.Therefore, in DDR4, this order can stop before runtime, and the mechanism accessing the order that makes mistakes helps accurately to point out the order that makes mistakes, and this helps Fault recovery again.

Fig. 1 is the block diagram of an embodiment of the system with memory sub-system, and described memory sub-system has via address bus but not the addressable register of data bus.System 100 represents calculation element or mobile device, wherein isolates register 130 and isolates with primary processor 110.The instruction stored in primary processor 110 run memory subsystem 120.Primary processor 110 sends the order of visit data in general manner.This order can comprise physical address or virtual address, and described physical address or virtual address point to the particular memory location in the storage arrangement of memory sub-system 120.

Isolation register 130 is not directly visited by primary processor 110.Therefore, even if register 130 is connected to element, the such as address bus (it is also connected to memory controller and storage arrangement (see following Fig. 2 and Fig. 3 to obtain more detailed example)) of memory sub-system 120, register 130 and the direct access undertaken by primary processor 110 are still " isolation ".System 100 comprises control gear as known in the art, with by data and code or instruction load to memory sub-system 120 to be run by processor 110.

In one embodiment, primary processor 110 sends and makes data be stored in order in register 130, and wherein 130, register directly can not be accessed by primary processor 110.Example comprises mode register value, some debugging value, parity error message or out of Memory.In such an embodiment, primary processor 110 is given an order, described in be forwarded to register 130, with the register making this register its content replication or the memory device that is delivered to memory sub-system 120 are set up.This storage arrangement is connected to data bus, and thus can by the order by Data import to the data bus that can be read by primary processor 110 responding host processor 110.

In one embodiment, BIOS (basic input/output) 140 comprises the code that can be run by primary processor 110 to trigger the reading to register 130, and processes the content wherein stored.Such as, primary processor 110 can be configured to debugging code or the error correcting code of accessing storage in BIOS 140 when some event occurs.Therefore, it is possible to make primary processor 110 run debugging mode or error correction state, it is by the content of access register 130, and determines what action responds the content read will take.

Fig. 2 is the block diagram of an embodiment of the system with memory sub-system, and described memory sub-system has register between memory controller and DRAM device.System 200 represents calculation element or mobile device, and can be an example of the system 100 of Fig. 1, and in described calculation element or mobile device, register-bit is between memory controller 220 and DRAM 240.The instruction stored in primary processor 210 run memory subsystem 202.Primary processor 210 can access in DRAM 240 store data or code so that operating instruction.In one embodiment, except DRAM 240, memory sub-system 202 also comprises other memory resource (not shown).

Primary processor 210, by generating it sends to memory controller 220 order or request by main bus 212, visits DRAM 240.Main bus 212 represents that primary processor 210 can provide any connection of the order relevant to memory access or request through it.In one embodiment, memory controller 220 through register 230, replace sending all request of access directly to DRAM 240.In another embodiment (see such as following Fig. 3), memory controller can directly access DRAM 240, and register 230 is positioned on memory controller and the connected address bus of DRAM.

In one embodiment, address bus 222 and address bus 224 all represent the address bus of memory sub-system 202, wherein address bus 222 is the address buss between memory controller 220 and register 230, and address bus 224 is the address buss between register 230 and DRAM 240.Register 230 can on the address bus between memory controller 220 and DRAM 240, with to the visit order executable operations being sent to DRAM 240 by memory controller 220.In one embodiment, memory controller 220 sends all orders through register 230 to DRAM 240.Such as, in one embodiment, register 230 provides bad parity to verify.When bad parity being detected, register 230 does not forward the order that makes mistakes.Therefore, register 230 is made can to prevent DRAM from operating bad order (its originally impel device 200 to become do not respond (that is, hanging up)) between memory controller 220 and DRAM 240.

During the one that register 230 provides bad parity to verify wherein realizes, register 230 records (log) information relevant with it when bad parity being detected.When bad parity being detected, except stoping order to arrive except DRAM 240, register 230 also triggers and detects bad parity by memory controller 220 and/or DRAM 240.But indicate bad parity in system 200, primary processor 210 detects bad parity, and the content reading register 230 can be attempted, to obtain bad parity record (log) information.Then, this register can respond reading order and by its delivery of content to DRAM 240, to realize the access of primary processor 210 pairs of error loggings, how proceed for determining.Primary processor 210 can visit by data bus 242 out of Memory that institute's transferring content of register 230 and DRAM 240 store.DRAM 240 is connected to data bus 242, and register 230 is not connected to data bus 242.

Fig. 3 is the block diagram of an embodiment of the system with memory sub-system, and described memory sub-system has via address bus but not the addressable register of data bus and via address bus and all addressable storage arrangement of data bus.System 300 represents calculation element, wherein primary processor 310 visit data from register 320 indirectly.System 300 can be an example of the system 100 of Fig. 1.

Although the register 230 of Fig. 2 is connected between memory controller and storage arrangement, register 320 is not connected between memory controller 340 and DRAM 330.On the contrary, register 320 is connected to memory controller 340 by address bus 302 concurrently with DRAM 330.Register 320 is not connected to data bus 304.DRAM 330 is connected to data bus 304.Memory controller 340 can be connected to data bus 304, or can be free of attachment to data bus 304.In one embodiment, memory controller 340 is coupled to primary processor 310 via command line 306, and command line 306 can be a part for data bus 304 or can not be the part of data bus 304.

Register 320 records the information of such as storer Configuration Values or debugging value and so on.When primary processor 310 runs the instruction of (one or more) value of record in instruction reading register 320, primary processor 310 is given an order to memory controller 340 by command line 306, and then memory controller 340 provides order on address bus 302.Primary processor 310 is not directly connected to address bus 302.Register 320 responds this order in the following way: by address bus 302, data are passed to DRAM 330.

In one embodiment, to the order of register 320, register 320 is transmitted to the ad-hoc location in DRAM 330.The position having and select code or the information of selection specified by this register.Therefore, that trigger command can indicate DRAM 330, recorded information should be write to it register is read.In one embodiment, DRAM 330 comprise multiple storage arrangement 332-0,332-1 ..., 332-N, wherein N be more than or equal to zero integer.In one embodiment, each device comprises one or more multi-usage register (MPR), and it shows for MPR [3:0] in device 332-0.Can exist more than four registers in each DRAM device or be less than four registers.

In one embodiment, memory controller 340, by selecting and/or write enable for the desired location chosen position in DRAM 330, comes mask register 320 writes its content position to it.Its delivery of content is triggered to the reading of DRAM 330 by register 320 and can comprise the selection code indicating specific MPR.In one embodiment, read the form instruction that the triggers register 320 as transmission source, it will write as MPR specified by destination.Therefore, reading triggering can be structurally similar to other standard commands in system 300 order.

In general, read to trigger and make register 320 recorded information be passed to register on DRAM 330, then this recorded information can be read by primary processor 310.Primary processor 310 sends and finally makes reading trigger the order being sent to register 320.In one embodiment, this order carrying out host processor 310 is considered to read triggering, and is forwarded by memory controller 340.In another embodiment, primary processor 310 sends and makes memory controller generate the order of reading and triggering, and then reading triggering is sent to register 320 by memory controller.

Fig. 4 is the block diagram of an embodiment of the system with memory sub-system, and described memory sub-system has register setting between memory controller and DRAM device, and wherein register setting performs parity checking.As described in the above example for Fig. 1 and Fig. 2, in one embodiment, the register setting be arranged between memory controller and storage arrangement can perform parity checking.In system 400, register setting 420 is between memory controller 410 and DRAM 430.

Register setting 420 comprises register 422, wherein its record parity information.Register 422 be known in the art, according to the register of any embodiment.In brief, register comprises the one group of volatibility digit order number kept in set of circuits element.In one embodiment, register setting 420 also comprises parity check logic 424, and its expression runs in process resource to perform hardware and/or the software of parity function.Parity checking is generally the quite simply logical operation checking that institute calculates parity and whether mates expectation parity, and can realize easily through simple digital circuitry.

Register setting 420 is connected to DRAM 430 via address bus 444.DRAM 430 is connected to primary processor via data bus 442.DRAM 430 comprises memory resource 432, and it stores the data in DRAM.DRAM 430 also comprises one or more MPR 434, and it can be used as the little working storage (scratch pad) of DRAM device substantially.In one embodiment, DRAM 430 comprises parity check logic 436, and the mode that parity check logic 436 can be similar according to the parity check logic 424 to register setting 420 realizes.In one embodiment, any one or both of parity check logic 424 and parity check logic 436 are enabled selectively.Therefore, parity checking can enable or disable at both register setting 420 and DRAM 430 place.In one embodiment, when parity checking is enabled at register setting 420 place, it is forbidden at DRAM 430 place.

Parity check logic 424 is enabled for following description supposition.If parity check logic 424 detects bad parity, then it parity error message is recorded in can be C/A register register 422 in.Register setting 420 transmits error logging information and wrong status information to DRAM 430.The same mechanism that register setting 420 is used for transmitting to DRAM 430 error logging information and wrong status information can be used for transmitting control word from register setting 420.

In one embodiment, register setting 420 is on DIMM (dual-inline memory module).System 400 is by sending from memory controller 410 position that address command arranges register 422.Based on this address, register setting 420 arranges the position in register 422.As described herein, normal address order then can be used for making register setting 420 that data are passed to MRP 434, to be read by data bus 442.Because register setting 420 and data bus 442 are isolated, so data can not directly be positioned on data bus so that by main processor accesses by it.

In one embodiment, set-up register device 420, to verify odd even (PAR) signal of a clock generation after chip select signal (CS#).In an alternative embodiment, parity signal can the clock period identical with CS#, replace in the clock period+1 generate.Register setting 420 checked parity not have mistake before forwarding the command to DRAM 430.In DRAM 430, no matter whether enable parity check logic 436 (that is, no matter whether DRAM verifies bad parity), work in an identical manner from the transmission of register setting 420 pairs of error loggings.

In one embodiment, for recording recorded information and as described below from the process of register setting 420 read-out recording information.This process allows to recover from bad parity, and by traditional approach, parity error misunderstanding causes the system failure.Bad parity in register setting 420 sense command or address.C/A (row/address) frame (RCW (register control word) position C0..FF) of register 422 misregistration.In one embodiment, the position of record is C2-C0, ACT_n, BG1-BG0, BA1-BA0, PAR, A17, A16/RAS_n, A15/CSA_n, A14/WE_n and A13:0,26 altogether.Bad parity mode bit is set to ' 1 ' by register setting 420, with the bad parity in indication mechanism 400.Be with remarkable a contrast of previous bad parity calibration technology, register setting 420 can replace it to be forwarded to DRAM 430 by keeping the C/A frame of mistake, prevents false command to be run.

In one embodiment, signal asserted by register setting 420 pairs of memory controllers 410, to indicate bad parity.This signal may be at the ALERT_n signal that the duration of tPAR_ALERT_PW_reg is asserted to memory controller after the delay of tPAR_ALERT_ON_reg.Register setting 420 forbids parity checking when bad parity being detected, and after bad parity mode bit is reset to ' 0 ' by memory controller 410, just will restart parity checking.

In one embodiment, MPR 434 comprises multiple MPR register, and it has different row.In one embodiment, MPR page 0 is readable and can writes register, and MPR page 1,2,3 is read-only.Therefore, memory controller 410 by arranging MR3 position A2=1 and A1:A0=00 (page 0), can enable ' the MPR page 0 ' pattern in DRAM 430 in row 0.Read and write and thus can be directed to page 0.

In one embodiment, the error logging register in RCW choice control word selected by memory controller 410, and initiates one or more orders of the content of register 422 being write MPR page 0.In one embodiment, memory controller 410, by writing four times to order space control word (address 3F), sends four and ' sends 8 RCW ' orders to MPR.This sequence can be transmitted to the page 0 of MPR0, MPR1, MPR2 and MPR3 32 (they can be the whole sizes of register 422) of error logging register.Row 0 on DIMM being used for MPR is written in when all DIMM have row 0 is easily.Other row can be used to replace row 0.

In one embodiment, for convenience's sake, replacement response can be continued to use the pattern identical with the replacement response in page 1 to page 0.Page 1 is used for error logging by DRAM, but can be only readable.If page 1 is read-only, then information can write the page write (such as page 0) with same map, makes same commands and process can be used for understanding error message.

In an example embodiment, to the write of page 0 (MPR1) be there is BA1:BA0=00 and the following address A7:A0 mapped write affairs:

In error logging and error condition from after register 422 passes to DRAM page 0, memory controller 410 can use reading order to read page 0.Therefore, primary processor can generate reading order, uses reading order to visit described data to make memory controller.

Memory controller 410 can forbid MPR operation by MR3 A2=0 being programmed into DRAM, and it initiates normal flow.Memory controller by resetting bad parity signal as mentioned above, again can also enable parity checking in register setting 420.

In one embodiment, following Register Specification details can be suitable for:

Table 1-RC3F: order space

The RCW of table 2-RC8x:8 position RCW selects control word definition

[1] ' sending 8 RCW ' order to MPRx makes address field automatically increase progressively 1 and make RCW select the MPR bit field in control word automatically to increase progressively 1.

The RCW of table 3-RC4x:4 position RCW selects control word definition

[1] ' sending two 4 RCW ' order to MPRx makes address field automatically increase progressively 1 and make RCW select the MPR bit field in control word automatically to increase progressively 1.

Will be understood that, register control word (RCW) is a part for register setting.DRAM device comprises mode register (MR), and register setting comprises RCW.RCW and MR has identity function for two different associated apparatus.First memory controller selects the RCW that will read, and then writes the expectating address (address that will read) as source.Then, memory controller can generate destination control word, with named place of destination (address to its write).Each selected bits in the control word of order space is used for definition command.Can exist and be retained or otherwise untapped position.

In order to realize the write of content of registers, in one embodiment, memory controller arranges source, arranges destination, and then setting command space control word, it generates and sends control word.This system can be arranged so that only arranging source and destination itself does not carry out any operation.

' sending 8 RCW ' to MPRx or ' writing RCW before sending two 4 RCW ' to MPRx and select control word.In one embodiment, register setting sends following position in QxA [7:0] output:

Table 4-to DRAM send 4 RCW RCW position assignment

Table 5-to DRAM send 8 RCW position assignment

In one embodiment, control word position C0..FF is used as 32 bit-errors record registers.In one embodiment, when there is bad parity, register setting records following sampling order and address bit in error logging register, and it can be passed to the page 0 of DRAM MPR by memory controller, it can be read by main system (via processor) there.

Table 6-RCC0..RCFF: error logging register

[1] register setting arranges this position when there is CA bad parity.Write this position as ' 0 ' and restarted parity checking.Although arrange this and device is in any one of two kinds of circulation N+1 parity modes, device can not assert any one that its QxCSy_n exports.

In one embodiment, be applied to DDR4 as described herein to the indirect reading of register setting, it can adopt the parity checking in register setting as above to realize.In the more specifically details for DDR4 MPR pattern, an embodiment of DDR4 DRAM comprises four pages of MPR register, and every page has four MPR positions.Page 0 has four 8 the MPR positions able to programme stored for DQ bit pattern.By arrange in MR3 mode register A2=1 with first make DRAM enter ' from/to the data stream of MPR ' pattern, write these MPR registers.This MPR page also uses the position A1:A0 in MR3 to arrange.

In this mode, MRS (mode register setting) order is used for programming to MPR.For MRS order, address bus is used for these data.Once through programming, the reading order in pattern that register just can adopt ' MPR operation ' visits, to be driven into MPR position in the DQ bus of memory controller or main frame.

DDR4 MPR pattern is enabled and is selected to be realized by mode register command as follows with page.

Table 7-MR3

As mentioned above, in DDR4 SDRAM, four MPR pages are provided.Page 0 is for read and write, and page 1,2 and 3 is read-only.It is readable that any MPR position (MPR0-3) in page 0 can be through any one of three kinds of readout modes (serial, parallel or staggered), but page 1,2 and 3 only supports series read-out pattern.

After being powered up, the content of MPR page 0 should have as to the predefined default value of DRAM device.When MPR write order is sent by memory controller, MPR page 0 can only can be write.Unless send MPR write order, otherwise DRAM for good and all must keep default value, and content should do not changed voluntarily in order to any object.

Table 8-MPR default value

Will be understood that, with reference to, even above be non-limiting example for the detailed reference described in the verification of DDR4 and DDR4 bad parity.As described herein, can work to isolating with data bus all registers being still coupled to the device be coupled with data bus to the indirect reading mechanism of register.

Fig. 5 is for the process flow diagram from an embodiment of the process of visit data via address bus but not in the addressable register of data bus.In one embodiment, memory controller sends order to register setting, and information stores or record in a register 502 by its trigger register device.This information can be parity error message, Debugging message, configuration information or the out of Memory that can store in the register of isolating with system data bus.

In one embodiment, the information that store in a register is configuration information, and triggering is for writing the order of configuration information from memory controller.In one embodiment, the information that store is parity error message, and triggering is the detection occurred about bad parity undertaken by register setting.In one embodiment, the information that store is Debugging message, and to trigger be from memory controller, response debugging software and data are write the order of register.Response triggers, and register setting to record the information in register 504.

Memory controller detects to read and triggers, to read the information 506 stored in register.Memory controller generally receives this triggering from the process run by primary processor.This process can be the program run on main frame, or it can be the code stored in device BIOS.In one embodiment, memory controller reads triggering by response and identifies source and destination 508, prepares to read register.In one embodiment, read that to trigger be the order of certain form, particular register location recognition is source and by for the purpose of the specific MPR location recognition of storage arrangement by it.Memory controller can to register setting and DRAM warning order, to identify ad-hoc location based on the mark of the information that will be read by main frame.

Respond the order from memory controller, its content (source) is write specified MPR position (destination) 510 by register setting.Then, main frame can pass through system data bus, adopt standard reading order to read information 512 from the destination storage arrangement.The main frame of solicited message based on reading information determine one or more action 514.These actions can relate to setting or Reconfigurations, store data in memory storage or send data by network, identification has the order of bad parity and sends the order or other action any corrected.

In one embodiment, BIOS controls at least certain order being sent to register setting.Such as, response bad parity, BIOS can see that mistake occurs, and then gets back to main frame to find particular error.By reading register setting as mentioned above, particular error is visible.In one embodiment, response mistake, BIOS can attempt each apparatus registers in reading system, with ascertainment error origin position and mistake specifically what.This software control is to the write of register and order and reading.Then BIOS determines to take what action based on particular error.

Fig. 6 is the block diagram of an embodiment of computing system, and wherein the register of memory sub-system is accessed indirectly by primary processor.System 600 represents the calculation element according to any embodiment as herein described, and can be laptop computer, desk-top computer, server, game or entertainment control system, scanner, duplicating machine, printer or other electronic installation.System 600 comprises processor 620, and it is provided for the process of system 600, operational administrative and instruction operation.Processor 620 can comprise the microprocessor of any type, central processing unit (CPU), process core or other processing hardware, to provide process for system 600.The integrated operation of processor 620 control system 600, and can be or comprise the combination of one or more general programmable or special microprocessor, digital signal processor (DSP), Programmable Logic Controller, special IC (ASIC), programmable logic device (PLD) etc. or this kind of device.

Memory sub-system 630 represents the primary memory of system 600, and for the code that will be run by processor 620 or the data value that use will provide temporary transient storage when running routine.Memory sub-system 630 comprises storer 632, it is expressed as follows one or more storage arrangement, and described one or more storage arrangement can comprise ROM (read-only memory) (ROM), flash memory, the random access memory (RAM) of one or more kind or the combination of other storage arrangement or this kind of device.In one embodiment, storer 632 comprises at least one DRAM device.Memory sub-system 630 comprises register 634, and its expression is not the register that directly be can read by processor 620.This register can be called isolation register, and can as described hereinly indirectly read.

In addition to other, memory sub-system 630 also stores and trustship operating system (OS) 636 etc., to provide software platform for the instruction operation in system 600.In addition, other instruction 638 is stored and runs from memory sub-system 630, to provide logic and the process of system 600.OS 636 and instruction 638 are run by processor 620.

Processor 620 and memory sub-system 630 are coupled to bus/bus system 610.Bus 610 is a kind of abstract terms, and it represents any one or multiple independent physical bus, communication line/interface and/or point to point connect that are connected by suitable bridge, adapter and/or controller.Therefore, what bus 610 can comprise in such as system bus, periphery component interconnection (PCI) bus, super transmission or Industry Standard Architecture (ISA) bus, small computer system interface (SCSI) bus, USB (universal serial bus) (USB) or Institute of Electrical and Electric Engineers (IEEE) standard 1394 bus (so-called " live wire ") is one or more.The bus of bus 610 can also correspond to the interface in network interface 650.

In one embodiment, bus 610 comprises data bus, and described data bus is the data bus comprised in memory sub-system 630, processor 630 by described data bus can from storer 632 read value.Processor 620 is linked to extension wire shown in memory sub-system 630 and represents command line, processor 620 provides order and address to access storer 632 by described command line.Register 634 is connected to the data bus of memory sub-system 630, but is not connected to the data bus of bus 610.

System 600 also comprises one or more I/O (I/O) interface 640, network interface 650, one or more internal mass memory storage 660 and is coupled to the peripheral interface 670 of bus 610.I/O interface 640 can comprise one or more interface module, and user carries out interface (such as video, audio frequency and/or alphanumeric interface) through described one or more interface module and system 600.Network interface 650 carries out by one or more network and remote-control device (such as server, other calculation element) ability that communicates for system 600 provides.Network interface 650 can comprise Ethernet Adaptation Unit, radio interconnected assembly, USB (USB (universal serial bus)) or other interface based on wired or wireless standard or proprietary interface.

Memory storage 660 can be or comprise for according to non-volatile mode to store any conventional media of mass data, such as one or more dish based on magnetic, solid-state or light or combination.Memory storage 660 preserves code or instruction and data 662 according to permanent state (although i.e., system 600 power breakdown, also keeping this value).Memory storage 660 can be generally considered to be " storer ", but storer 630 is the storeies running or operate, to provide instruction to processor 620.Although memory storage 660 is non-volatile, storer 632 also can comprise volatile memory (if that is, interrupt electric power to system 600, then the value of data or state are uncertain).

Peripheral interface 670 can comprise the above any hardware interface specifically do not mentioned.Peripheral hardware generally represents the device being connected to system 600 relatively.Relevant connection is a kind of connection, and wherein system 600 provides software and/or hardware platform, and operation runs on described software and/or hardware platform, and user and described software and/or hardware platform carry out alternately.

Fig. 7 is the block diagram of an embodiment of mobile device, and wherein the register of memory sub-system is accessed indirectly by primary processor.Device 700 represents mobile computing device, such as, calculate flat board, mobile phone or smart phone, the electronic reader of enabling wireless or other mobile device.Will be understood that, some assembly in these assemblies is shown in general manner, but all component of this device is not shown in device 700.

Device 700 comprises processor 710, the main process operation of processor 710 actuating unit 700.Processor 710 can comprise one or more physical unit, such as microprocessor, application processor, microcontroller, programmable logic device or other processing element.Process performed by processor 710 operates the operation comprising operating platform or operating system (running application and/or apparatus function thereon).Process operation comprises and human user or the operation relevant with the I/O (I/O) of other device, the operation of being correlated with power management and/or the operation relevant with device 700 being connected to another device.Process operation can also comprise to audio frequency I/O and/or show the relevant operation of I/O.

In one embodiment, device 700 comprises audio subsystem 720, and audio subsystem 720 represents and the hardware providing audio-frequency function to associate to calculation element (such as audio hardware and voicefrequency circuit) and software (such as driver, codec) assembly.Audio-frequency function can comprise loudspeaker and/or earphone exports and microphone input.Device for this kind of function can be integrated in device 700 or be connected to device 700.In one embodiment, user comes to carry out alternately with device 700 by providing voice command (it is received by processor 710 and processed).

Display subsystem 730 represents the hardware (such as display device) and software (such as driver) assembly that provide vision display and/or tactile display, carries out alternately for user and calculation element.Display subsystem 730 comprises display interface 732, and display interface 732 comprises concrete screen from display to user or hardware unit for providing.In one embodiment, display interface 732 comprises and being separated to processor 710, at least performing the logic with the relevant a certain process of display.In one embodiment, display subsystem 730 comprises touch panel device, and described touch panel device provides to user and exports and input.

I/O controller 740 represent with mutual the relevant hardware unit of user and component software.I/O controller 740 can carry out operating managing the hardware of the part as audio subsystem 720 and/or display subsystem 730.In addition, I/O controller 740 illustrates the tie point of the attachment device being connected to device 700, and user can be carried out with system by described tie point alternately.Such as, the device that can be attached to device 700 can comprise microphone device, loudspeaker or stereophonic sound system, video system or other display device, keyboard or keypad device or other I/O device, so as with the application-specific of such as card reader or other device and so on the use of.

As mentioned above, I/O controller 740 can carry out with audio subsystem 720 and/or display subsystem 730 alternately.Such as, the input through microphone or other audio devices can provide input or order for one or more application of device 700 or function.In addition, audio frequency can be provided to export, as substituting or supplementing display translation.In another example, if display subsystem comprises touch-screen, then display device also serves as input media, and it can be managed by I/O controller 740 at least partly.Additional buttons or switch can also be there is in device 700, to provide the I/O managed by I/O controller 740 function.

In one embodiment, I/O controller 740 management devices, such as accelerometer, video camera, optical sensor or other environmental sensor, gyroscope, GPS (GPS) or other hardware that can be included in device 700.This input can be the mutual part of end user, and to system provide environment input with affect its operation (such as to the filtering of noise, adjust brightness is detected display, to camera application flash of light or further feature).

In one embodiment, device 700 comprises power management portion 750, the charging of its management battery electric power use, battery and the feature relevant to power-save operation.Memory sub-system 760 comprises the storage arrangement for the information in memory storage 700.Storer can comprise non-volatile memory device (state does not change when the electric power of storage arrangement is sent in interruption) and/or volatile memory devices (state is uncertain when the electric power of storage arrangement is sent in interruption).The memory resource of memory sub-system 760 can storing applied data, user data, music, photo, document or other data and the system data relevant with the operation of function to the application of system 700 (no matter being long-term or temporary transient).

In one embodiment, at least one storage arrangement 762 comprises by the direct addressable register of processor 710.The register setting 764 of memory sub-system 760 is external memory devices 762, and is not directly addressable by processor 710, but is coupled to storage arrangement 762 via address bus in communication, as mentioned above.The data stored in register setting 764 can pass to the register of storage arrangement 762, to be read by processor 710.

Interconnecting part 770 comprises hardware unit (such as wireless and/or wired connector and communication hardware) and component software (such as driver, protocol stack), to make device 700 can communicate with external device (ED).Device may be the isolated system of such as other calculation element, WAP or base station and so on and the peripheral hardware of such as earphone, printer or other device and so on.

Interconnecting part 770 can comprise multiple dissimilar interconnecting part.In general, device 700 shows for having honeycomb interconnecting part 772 and wireless communications portion 774.The cellular network interconnecting part that honeycomb interconnecting part 772 generally represents to be provided by cellular carrier institute, such as provide via GSM (global system for mobile communications) or change or derivative, CDMA (CDMA) or change or derivative, TDM (time division multiplex) or change or derive or other cellular service standard.Wireless communications portion 774 represents it is not the wireless communications portion of honeycomb, and can comprise personal area network's (such as bluetooth), LAN (Local Area Network) (such as WiFi) and/or wide area network (such as WiMax) or other radio communication.Radio communication represent by use transmit data through the brewed electromagnetic radiation of non-solid medium.Wire communication is carried out through solid-state communication media.

Peripheral connect 780 and comprise hardware interface and connector and component software (such as driver, protocol stack), to carry out periphery connection.Will be understood that, device 700 may be the peripheral unit (" extremely " 782) of other calculation element and have connected peripheral unit (" certainly " 784).Device 700 has " docking " connector usually, to be connected to other calculation element, for such as managing the object of content on (such as download and/or upload, change, synchronously) device 700 and so on.In addition, butt connector can allow device 700 to be connected to some peripheral hardware, and it allows device 700 to control such as to export to the content of audiovisual system or other system.

Except proprietary butt connector or other proprietary connection hardware, device 700 can also carry out periphery via ordinary connector or measured connector and connect 780.General type can comprise USB (universal serial bus) (USB) connector (it can comprise any one in several different hardware interface), the display port comprising mini display port (MDP), HDMI (High Definition Multimedia Interface) (HDMI), live wire or other type.

Process flow diagram shown in this article provides the example of the sequence of various process action.Although illustrate with particular sequence or order, unless otherwise noted, otherwise the order of action can be passed through amendment.Therefore, illustrated embodiment only should be understood to an example, and process can perform according to different order, and partial act can executed in parallel.In addition, in various embodiments, one or more action can be omitted; Therefore, not whole action is all required in each example.Other process flow is possible.

With regard to various operation described herein or function, they can describe or be defined as software code, instruction, configuration and/or data.Content can be directly to perform (" object " or " can perform " form), source code or difference code (" increment " or " patch " code).The software content of embodiment described herein can utilize on it and store manufacturing a product or utilizing operation communication interface to provide with the method sending data via communication interface of content.Machinable medium can make machine perform described in function or operation, and comprising storage takes machine (such as calculation element, electronic system etc.) to may have access to any mechanism of the information of form, such as, can record/and can not recording media (such as ROM (read-only memory) (ROM), random access memory (RAM), magnetic disk storage medium, optical storage media, flash memory device etc.).Communication interface comprises carries out interface with any one in the media such as hardwired, wireless, light such as, to carry out any mechanism of communicating, memory bus interface, processor bus interface, Internet connection, disk controller etc. with another device.Configuration communication interface can be carried out in the following way: configuration parameter is provided and/or sends signal to prepare communication interface, thus provide a description the data-signal of software content.Communication interface can utilize and send to one or more order of communication interface or signal to visit.

Various assembly as herein described can be the parts for performing described operation or function.Each assembly as herein described comprises software, hardware or their combination.These assemblies can be embodied as software module, hardware module, specialized hardware (such as applying specific hardware, special IC (ASIC), digital signal processor (DSP) etc.), embedded controller, hard-wired circuit etc.

Except content described herein, various amendment can be carried out to disclosed embodiment of the present invention and realization, and not deviate from its scope.Therefore, explanation herein and example should be considered to illustrative instead of restrictive, sense.Range size of the present invention should only with reference to following claims.

Claims (13)

1., for receiving an equipment of control word (CW), described equipment comprises:

Comprise the dynamic RAM (DRAM) of at least one page, at least one page described has at least one multi-usage register (MPR), and described dynamic RAM (DRAM) also comprises:

First interface, will be used for when described first interface is operationally coupled to address bus receiving CW and described CW being supplied to concrete MPR; And

Second interface, described in described second interface is coupled in communication, at least one has the page of at least one MRP, wherein:

Described first interface to be used during described first interface is coupled to described address bus to write at least one page with at least one MRP described, and described second interface will be used during described second interface coupling to described data bus to read at least one page with at least one MRP described.

2. equipment as claimed in claim 1, wherein, described CW comprises 4 CW or 8 CW.

3. equipment as claimed in claim 1, wherein, described concrete MPR comprises the MPR 0(MPR0 of page 0) and described CW be associated with ordering CMD4.

4. equipment as claimed in claim 1, wherein,

Described CW is associated with read operation,

Described read operation with there is position [7:0] and at least in position 6, there is MPR position 1 and 8 place values in position 5 with MPR position 0 are associated, and

The combination of MPR position 1 and position 0 is for selecting concrete No. MPR.

5. equipment as claimed in claim 1, wherein,

Described CW is associated with the read operation automatically increased progressively with address field,

Automatically the read operation increased progressively with address field with there is position [7:0] and at least in position 6, there is MPR position 1 and 8 place values in position 5 with MPR position 0 are associated, and

The combination of MPR position 1 and position 0 is for selecting concrete No. MPR.

6. equipment as claimed in claim 1, also comprises:

Communication is coupled to the address bus of described first interface;

Communication is coupled to the register of described address bus; And

Communication is coupled to the memory controller of described register, and described memory controller is used for:

Described CW is supplied to described register,

Select page and in selected page, select MPR to be used for receiving described CW, and

There is provided one or more order to impel described CW to be written to selected page and MPR.

7. equipment as claimed in claim 6, also comprises:

Communication is coupled to the data bus of described second interface; And

Communication is coupled to the processor of described data bus; Wherein:

Described data bus interface will be used for, via described data bus, the content from MPR is supplied to described processor.

8. equipment as claimed in claim 6, wherein, described register will be used for performing parity checking.

9., for receiving a computer implemented method of control word (CW), described method comprises:

Receive CW at multi-usage register (MPR) place from address bus interface, wherein said MPR is associated with dynamic RAM (DRAM); And

Usage data bus interface transmits content from described MPR.

10. method as claimed in claim 9, wherein, described CW comprises 4 CW or 8 CW.

11. methods as claimed in claim 9, wherein, described MPR comprises the MPR 0(MPR0 of page 0) and described CW be associated with order CMD4.

12. methods as claimed in claim 9, wherein,

Described CW is associated with read operation,

Described read operation with there is position [7:0] and at least in position 6, there is MPR position 1 and 8 place values in position 5 with MPR position 0 are associated, and

The combination of MPR position 1 and position 0 is for selecting concrete No. MPR.

13. methods as claimed in claim 9, wherein:

Described CW is associated with the read operation automatically increased progressively with address field,

Automatically the read operation increased progressively with address field with there is position [7:0] and at least in position 6, there is MPR position 1 and 8 place values in position 5 with MPR position 0 are associated, and

The combination of MPR position 1 and position 0 is for selecting concrete No. MPR.