CN104576385A - FinFET structure and manufacturing method thereof - Google Patents
FinFET structure and manufacturing method thereof Download PDFInfo
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- CN104576385A CN104576385A CN201310478725.7A CN201310478725A CN104576385A CN 104576385 A CN104576385 A CN 104576385A CN 201310478725 A CN201310478725 A CN 201310478725A CN 104576385 A CN104576385 A CN 104576385A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a FinFET structure and a manufacturing method thereof. The method comprises the following steps of providing a substrate; forming a fin on the substrate, wherein the width of the fin is greater than an expected channel width; performing shallow channel isolation; forming a pseudo gate stack above a channel, and forming source and drain areas; depositing interlayer dielectric layers, and performing flattening to expose the pseudo gate stack; removing the pseudo gate stack to expose the channel part; forming an etching stop layer at the top of the channel; thinning the channel in a direction perpendicular to the lateral surface of the channel along the two sides of the channel until a required width is obtained; removing the etching stop layer. According to the FinFET structure and the manufacturing method thereof, the short-channel effect of the device is effectively inhibited, and meanwhile, the influence of source and drain parasitic resistors is reduced; compared with the prior art, the FinFET structure and the manufacturing method thereof have the advantages that the performance of the device is effectively improved, and process complexity is lowered.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly, relate to a kind of FinFET structure and manufacture method thereof.
Technical background
Along with the dimensions scale downward of semiconductor device, occur that threshold voltage reduces and the problem of decline with channel length, also, created short-channel effect in the semiconductor device.Relate to the challenge with manufacture view in order to tackle from semiconductor, result in FinFET, i.e. the development of FinFET.
Having realized that in FinFET structure, in order to strengthen the control ability of grid to raceway groove, better suppressing short-channel effect, wish that Fin channel part is more narrow better.But in source/drain region, narrow Fin structure will cause large dead resistance, affects device property.In order to reduce source-drain area dead resistance, existing technology first makes a very thin Fin structure usually, after completing rhythmic structure of the fence and source-drain area ion implantation, carries out epitaxial growth to increase source-drain area width to source-drain area.The device performance that this method improves preferably, but needed for epitaxial growth, process conditions are complicated, add process complexity to a certain extent.
In order to better address this problem, the invention provides a kind of FinFET manufacture method, adopt the Fin structure that first making one is thicker, again by carrying out the narrow raceway groove of thinning formation to channel part, effectively inhibit the short-channel effect of device, reduce the impact of source and drain dead resistance, compared with prior art simultaneously, effectively improve device performance, reduce process complexity.
Summary of the invention
The invention provides a kind of FinFET manufacture method, effectively inhibit the short-channel effect of device, reduce the impact of source and drain dead resistance simultaneously.Particularly, the present invention includes following steps:
A. substrate is provided;
B. form fin over the substrate, the width of this fin is greater than expection channel width;
C. carry out shallow trench isolation from;
D. above the raceway groove in the middle part of described fin and side forms pseudo-gate stack, forms source-drain area respectively at fin two ends;
E. deposit interlayer dielectric layer is to cover described pseudo-gate stack and described source-drain area, carries out planarization, exposes pseudo-gate stack;
F. remove pseudo-gate stack, expose channel part;
G. etching stop layer is formed at channel top;
H. carry out thinning perpendicular to raceway groove side face directions to raceway groove along raceway groove both sides, until obtain required width;
I. etching stop layer is removed.
Wherein, in stepb, the width of described fin is 30 ~ 50nm.
Wherein, in step g, the generation type of described etching stop layer can be form P type heavily doped region at channel top, and the generation type of described heavily doped region is ion implantation, and the element of described ion implantation is BF
2, doping content is 1e19cm
-3~ 5e19cm
-3.
Wherein, in step h, required channel width is for being less than 20nm, and described raceway groove thining method can be isotropic etching or oxidation.
Wherein, after step I, also comprise step j: deposit gate dielectric material, work function regulate material and gate metal material successively.
Present invention also offers a kind of FinFET manufacture method, comprising:
A. substrate is provided;
B. raceway groove place forms etching stop layer over the substrate;
C. form fin over the substrate, the width of this fin is greater than expection channel width;
D. carry out shallow trench isolation from;
E. above the raceway groove in the middle part of described fin and side forms pseudo-gate stack, forms source-drain area respectively at fin two ends;
F. deposit interlayer dielectric layer is to cover described pseudo-gate stack and described source-drain area, carries out planarization, exposes pseudo-gate stack;
G. remove pseudo-gate stack, expose channel part;
H. carry out thinning perpendicular to raceway groove side face directions to raceway groove along raceway groove both sides, until obtain required width;
I. etching stop layer is removed.
Wherein, in step c, the width of described fin 102 is 30 ~ 50nm.
Wherein, in stepb, the generation type of described etching stop layer 106 can be deposit mask plate.
Accordingly, the invention provides a kind of FinFET structure, comprising:
Semiconductor substrate;
Be positioned at the fin on described substrate;
Be positioned at described types of flexure, the shallow trench isolation of fin both sides from;
Cover described shallow trench isolation from interlayer dielectric layer;
Cover the gate stack in the middle part of described fin;
Be positioned at the source-drain area at described fin two ends;
And be positioned in the middle part of described fin, the raceway groove below described gate stack, wherein, described channel width is narrower than source-drain area width, and the source-drain area of described semiconductor structure and the fin region be positioned at below side wall is of similar shape and size.
Wherein, described channel width is 1/5 to 2/3 of source-drain area width.
The present invention adopts the Fin structure that first making one is thicker, then by carrying out the narrow raceway groove of thinning formation to channel part, effectively inhibits the short-channel effect of device, reduce the impact of source and drain dead resistance simultaneously, compared with prior art, effectively improve device performance, reduce process complexity.
Accompanying drawing explanation
Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 6, Fig. 8 and Figure 11 schematically show the three-dimensional equiangular figure formed according to each stage semiconductor structure of the method for manufacture semiconductor fin of the present invention.
Fig. 5, Fig. 7, Fig. 9 and Figure 11 schematically show the profile formed according to each stage semiconductor structure of the method for manufacture semiconductor fin of the present invention.
Figure 10 is the corresponding vertical view of semiconductor fin structures in Fig. 9.
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
The invention provides a kind of FinFET structure, comprising:
Semiconductor substrate 101;
Be positioned at the fin 102 on described substrate 101;
Be positioned at above described substrate 101, the shallow trench isolation of fin 102 both sides is from 103;
Cover the interlayer dielectric layer 105 of described shallow trench isolation from 103;
Cover the gate stack in the middle part of described fin 102;
Be positioned at the source-drain area at described fin 102 two ends;
And, be positioned in the middle part of described fin 102, the raceway groove 300 below described gate stack, wherein, described channel width is 1/5 to 2/3 of source-drain area width, and source-drain area and fin 102 region be positioned at below side wall of described semiconductor structure are of similar shape and size.
Structure of the present invention has thicker source-drain area and narrower raceway groove, effectively inhibits the short-channel effect of device, reduces the impact of source and drain dead resistance simultaneously, compared with prior art, effectively improves device performance, reduces process complexity.
Substrate 101 comprises silicon substrate such as silicon wafer.Wherein, substrate 101 can comprise various doping configuration.In other embodiments, substrate 101 can also comprise other basic semiconductors, such as germanium or compound semiconductor, such as carborundum, GaAs, indium arsenide or indium phosphide.Typically, substrate 101 can have but be not limited to the thickness of about hundreds of micron, such as can in the thickness range of 400um-800um.
Fin 102 is formed by etched substrate 101, has identical material and crystal orientation with substrate 101, and usually, the length of fin 102 is 80nm ~ 200nm, and thickness is 30nm ~ 50nm.Source-drain area is positioned at fin 102 two ends, has identical length.Raceway groove is positioned in the middle part of fin 102, and between source-drain area, length is 30 ~ 50nm.In the present invention, the thickness of channel part is for being less than 20nm.
Gate dielectric layer 107 preferred material is silicon oxynitride, also can be silica or hafnium.Its equivalent oxide thickness is 0.5nm ~ 5nm.
Grid structure comprises the gate stack of conduction and is positioned at the insulating medium sidewall 201 of these gate stack both sides for a pair.Gate stack can be only metal gates, also can be metal/Polysilicon Composite Structures grid, wherein polysilicon upper surface have silicide.
Hereinafter with reference to accompanying drawing, the invention of this reality is described in more detail.In various figures, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.
Be to be understood that, when the structure of outlines device, when one deck, region are called be positioned at another layer, another region " above " or " top " time, can refer to be located immediately at another layer, another over, or itself and another layer, also comprise other layer or region between another region.Further, if overturn by device, this one deck, a region will be positioned at another layer, another region " below " or " below ".
If in order to describe the situation being located immediately at another layer, another over, will adopt herein " directly exist ... above " or " ... above and adjoin with it " form of presentation.
Describe hereinafter many specific details of the present invention, the structure of such as device, material, size, treatment process and technology, more clearly to understand the present invention.But just as the skilled person will understand like that, the present invention can be realized not in accordance with these specific details.Such as, the semi-conducting material of substrate and fin can be selected from IV race semiconductor, as Si or Ge, or Group III-V semiconductor, as GaAs, InP, GaN, SiC, or the lamination of above-mentioned semi-conducting material.
In this article, term " etching stop layer " refers to that its etching speed is less than the layer of the etching speed of the semiconductor layer etched away.Utilize the difference of etching speed between etching stop layer and semiconductor layer, optionally can remove semiconductor layer.Etching stop layer can (such as doping content be higher than 5e19cm by highly doped
-3) P type semiconductor or SiGe composition, wherein dopant can be at least one be selected from by the group that B, Al, Ga, In, T1 are formed.
Below in conjunction with accompanying drawing, embodiments of the invention one are described in detail.It should be noted that, the accompanying drawing of each embodiment of the present invention is only the object in order to illustrate, so there is no necessity and draws in proportion.
See Fig. 1, the invention is intended to make the semiconductor fin 102 be positioned at above Semiconductor substrate 101.As just example, Semiconductor substrate 101 and fin 102 are all made up of silicon.By etching this semiconductor layer and form fin 102 at the surperficial epitaxial semiconductor layer of Semiconductor substrate 101, described epitaxial growth method can be molecular beam epitaxy MBE) or additive method, described lithographic method can be dry etching or dry/wet etching.Wherein, described fin 102 width is greater than expection channel width, and in the present embodiment, this channel width can be 30 ~ 50nm, as 35nm, 40nm or 45nm.
After fin 102 has grown, to Semiconductor substrate 101 carry out shallow trench isolation from.Preferably, first to other regions except fin 102 of Semiconductor substrate 101 being formed silicon nitride and buffering silicon dioxide figure, as the mask of trench etching.Next in Semiconductor substrate 101, the groove with certain depth and sidewall angle is eroded away.Then grow with silica film with the drift angle of round and smooth groove and the damage removed in silicon face introducing in etching process.Trench fill and annealing after oxidation.Following use CMP carries out planarization to semiconductor substrate surface, and silicon nitride is as the barrier layer of CMP.After CMP, the phosphoric acid of heat is used to take out the silicon nitride exposed.Finally grow one deck sacrificial oxide layer at silicon face and rinse, to remove defect and the damage of silicon face further.Complete shallow trench isolation from after semiconductor structure as shown in Figure 2.
Next, above raceway groove, form pseudo-gate stack 200, and form source-drain area.Described pseudo-gate stack 200 can be individual layer, also can be multilayer.Pseudo-gate stack 200 can comprise polymeric material, amorphous silicon, polysilicon or TiN, and thickness can be 10-100nm.Thermal oxidation, chemical vapour deposition (CVD) CVD can be adopted), ald ALD) etc. technique to form pseudo-gate stack 200.Described source-drain area formation method can be that then ion implantation anneals active ions, in-situ doped extension and/or the combination of the two.
Alternatively, the sidewall of gate stack forms side wall 201 and 202, for being separated by grid.Side wall 201 and 202 can by silicon nitride, silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials are formed.Side wall 201 and 202 can have sandwich construction.Side wall 201 and 202 can be formed by comprising deposition-etch technique, and its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
Next, deposit interlayer dielectric layer 105, and parallel flat, expose pseudo-gate stack 200.Concrete, interlayer dielectric layer 105 can pass through CVD, high-density plasma CVD, spin coating or other suitable methods and be formed.The material of interlayer dielectric layer 105 can adopt and comprise SiO
2, carbon doping SiO
2, BPSG, PSG, UGS, silicon oxynitride, low-k materials or its combination.The thickness range of interlayer dielectric layer 105 can be 40nm-150nm, as 80nm, 100nm or 120nm.As shown in Figure 3, perform planarization, pseudo-gate stack 200 is come out, and the term flushed in the present invention " flushes " difference in height that refers between the two in the scope that fabrication error allows with interlayer dielectric layer 105).
Next, remove pseudo-gate stack, expose channel part, as shown in Figure 4.Concrete, remove pseudo-grid structure 220 and wet etching and/or dry quarter can be adopted to remove.In one embodiment, using plasma etching.Fig. 5 be in Fig. 4 semiconductor structure along with the profile in cross section, channel vertical direction.
Next, etching stop layer 106 is formed at channel top.Concrete, the generation type of described etching stop layer 106 can be form certain thickness P type heavily doped region at channel top.Ion implantation or additive method can be adopted to form described heavily doped region, as injected BF at channel top by ion implantation
2formed, wherein, BF2 doping content is 1e19cm
-3~ 5e19cm
-3, as 3e19cm
-3, the injection degree of depth is 6nm ~ 15nm, as 8nm, 10nm or 12nm.Form the semiconductor structure after etching stop layer 106 as shown in Figure 6, Fig. 7 be in Fig. 6 semiconductor structure along the profile with cross section, channel vertical direction.
Next, carry out thinning perpendicular to raceway groove side face directions to raceway groove along raceway groove both sides, until obtain desired thickness, preferably, required channel width is less than 20nm.Wherein, described raceway groove thining method can be isotropic etching, and in the present embodiment, wet etching and/or dry method of carving can be adopted thinning for raceway groove both sides, and thickness thinning can be 8nm ~ 15nm, as 10nm.
Optionally, described raceway groove thining method can be oxidation, carries out thinning by the method silicon in the certain thickness of raceway groove both sides being oxidized into silicon dioxide to raceway groove, preferably, described method for oxidation is dry-oxygen oxidation, and oxide thickness can be 8nm ~ 15nm, as 10nm.
Next, etching stop layer 106 is removed.Etching stop layer 106 can adopt wet etching and/or dry quarter to remove.Wet-etching technique comprise adopt hydrogen-oxygen to comprise solution such as ammonium hydroxide), deionized water or other suitable etchant solution; Dry carving technology such as comprises plasma etching etc.Remove the semiconductor structure after etching stop layer 106 as shown in Figure 8, in order to clearer illustrate thinning after raceway groove, Fig. 9 and Figure 10 schematically show semiconductor structure corresponding to Fig. 8 along and the profile in channel vertical direction and the vertical view of this semiconductor structure.Can find out, through thinning, the thickness of channel part is significantly less than original depth.
Next, deposit gate dielectric layer 107, work function regulating course 108 and gate metal layer 109 successively in pseudo-grid room, as shown in figure 11.Concrete, described gate dielectric layer 107 can be thermal oxide layer, comprises silica, silicon oxynitride; Also can be high K dielectric, such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al
2o
3, La
2o
3, ZrO
2, one in LaAlO or its combination, the thickness of gate dielectric layer 107 can be 1nm-10nm, such as 3nm, 5nm or 8nm.Described work function regulating course 108 can adopt the materials such as TiN, TaN to make, and its thickness range is 3nm ~ 15nm.Described gate metal layer 109 can be one deck or sandwich construction.Its material can be TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
xin one or its combination.Its thickness range can be such as 10nm-40nm, as 20nm or 30nm.
Next brief description is carried out to embodiments of the invention two, that is, substrate 101 is provided; Form fin 102 over the substrate, the width of this fin 102 is greater than expection channel width; Etching stop layer 106 is formed at channel top; Carry out shallow trench isolation from; Above raceway groove, form pseudo-gate stack, form source-drain area; Deposit interlayer dielectric layer, carries out planarization, exposes pseudo-gate stack; Remove pseudo-gate stack, expose channel part; Carry out thinning perpendicular to raceway groove side face directions to raceway groove along raceway groove both sides, until obtain required width; Remove etching stop layer 106; Deposit gate dielectric material, work function regulate material and gate metal material successively.
Compared with embodiment one, the difference of embodiment two is, etching stop layer 106 is formed after formation fin 102, instead of is formed after removing pseudo-gate stack and exposing channel part.Particularly, formation fin 102 after, above the channel part of fin 102, form etching stop layer 106, carry out again afterwards shallow trench isolation from.Particularly, after fin 102 is formed, deposit photoresist on semiconductor structure, utilizes mask plate to be removed by the photoresist in fin 102 channel part, exposes channel part, afterwards, forms etching stop layer 106 at the channel top exposed.Concrete, can adopt the methods such as LPCVD or ALD, etching stopping layer material can be silicon dioxide or silicon nitride, is originally being in example, adopts silicon nitride as etching stop layer.
The technique of all the other steps can reference example one, does not repeat them here.
Method according to embodiment two, etching stop layer 106 just exists after removing pseudo-gate stack, can directly carry out thinning to channel part.
According to embodiments of the invention, adopt manufacture method of the present invention, can not need that epitaxial growth is carried out to source-drain area and just can obtain the FinFET that source-drain area is thicker and channel region is thinner, compared with prior art, effectively improve device performance, source-drain area shape and structure specification, is convenient to the carrying out of the techniques such as later stage ILD, reduces process complexity simultaneously.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (12)
1. a FinFET manufacture method, comprising:
A., substrate (101) is provided;
B. form fin (102) over the substrate, the width of this fin (102) is greater than expection channel width;
C. carry out shallow trench isolation from;
D. above the raceway groove in the middle part of described fin and side forms pseudo-gate stack, forms source-drain area respectively at fin two ends;
E. deposit interlayer dielectric layer is to cover described pseudo-gate stack and described source-drain area, carries out planarization, exposes pseudo-gate stack;
F. remove pseudo-gate stack, expose channel part;
G. etching stop layer (106) is formed at channel top;
H. carry out thinning perpendicular to raceway groove side face directions to raceway groove along raceway groove both sides, until obtain required width;
I. etching stop layer (106) is removed.
2. FinFET manufacture method according to claim 1, is characterized in that, in step g, the generation type of described etching stop layer (106) forms P type heavily doped region at channel top.
3. FinFET manufacture method according to claim 2, is characterized in that, the generation type of described heavily doped region is ion implantation.
4. FinFET manufacture method according to claim 3, is characterized in that, the element of described ion implantation is BF
2, doping content is 1e19cm
-3~ 5e19cm
-3, the injection degree of depth is 6nm ~ 15nm.
5. a FinFET manufacture method, comprising:
A., substrate (101) is provided;
B. raceway groove place forms etching stop layer (106) over the substrate;
C. form fin (102) over the substrate, the width of this fin (102) is greater than expection channel width;
D. carry out shallow trench isolation from;
E. above the raceway groove in the middle part of described fin and side forms pseudo-gate stack, forms source-drain area respectively at fin two ends;
F. deposit interlayer dielectric layer is to cover described pseudo-gate stack and described source-drain area, carries out planarization, exposes pseudo-gate stack;
G. remove pseudo-gate stack, expose channel part;
H. carry out thinning perpendicular to raceway groove side face directions to raceway groove along raceway groove both sides, until obtain required width;
I. etching stop layer (106) is removed.
6. FinFET manufacture method according to claim 5, is characterized in that, in stepb, the generation type of described etching stop layer (106) is deposit mask plate.
7. FinFET manufacture method according to claim 1 or 5, it is characterized in that, the width of described fin (102) is 30 ~ 50nm before thinning.
8. FinFET manufacture method according to claim 1 or 5, it is characterized in that, in step h, required channel width is for being less than 20nm.
9. FinFET manufacture method according to claim 1 or 5, it is characterized in that, in step h, described raceway groove thining method is isotropic etching or method for oxidation.
10. FinFET manufacture method according to claim 1 or 5, is characterized in that, after step I, also comprise: j. successively deposit gate dielectric material, work function regulates material and gate metal material.
11. 1 kinds of FinFET structure, comprising:
Semiconductor substrate (101);
Be positioned at the fin (102) on described substrate (101);
Be positioned at described substrate (101) top, the shallow trench isolation of fin (102) both sides is from (103);
Cover the interlayer dielectric layer (105) of described shallow trench isolation from (103);
Cover the gate stack at described fin (102) middle part;
Be positioned at the source-drain area at described fin (102) two ends;
And, be positioned at described fin (102) middle part, raceway groove (300) below described gate stack, wherein, described channel width is narrower than source-drain area width, and the source-drain area of described semiconductor structure and fin (102) region be positioned at below side wall are of similar shape and size.
12. FinFET structure according to claim 11, comprising:
Described channel width is 1/5 to 2/3 of source-drain area width.
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| CN201310478725.7A CN104576385A (en) | 2013-10-14 | 2013-10-14 | FinFET structure and manufacturing method thereof |
| PCT/CN2013/085533 WO2015054913A1 (en) | 2013-10-14 | 2013-10-21 | Finfet structure and method of manufacturing same |
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