CN104572423A - Debugging system and debugging device and method thereof - Google Patents
Debugging system and debugging device and method thereof Download PDFInfo
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- CN104572423A CN104572423A CN201310468038.7A CN201310468038A CN104572423A CN 104572423 A CN104572423 A CN 104572423A CN 201310468038 A CN201310468038 A CN 201310468038A CN 104572423 A CN104572423 A CN 104572423A
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Abstract
The invention discloses a debugging system, a debugging device and a debugging method. The debugging system comprises a mother board, the debugging device and a terminal, wherein the mother board comprises a basic input and output system and a system management bus; the basic input and output system is used for initializing a computer system and generating multiple pieces of debugging information in the process of initializing the computer system; the debugging device comprises a receiving interface, a microprocessor and a serial output interface; the receiving interface is used for receiving the debugging information from the system management bus; the microprocessor is used for decoding the debugging information into multiple pieces of serial information; each piece of serial information includes a debugging code and a text string used for describing the initialization state of the computer system; the terminal is used for receiving the serial information from the serial output interface and displaying the debugging codes and the text strings of the serial information.
Description
Technical field
The present invention relates to a kind of debug system and debugging apparatus thereof and method, particularly relate to text string in a kind of fechtable Debugging message and the debug system shown and debugging apparatus thereof and method.
Background technology
Along with computer industry level constantly progressive the and mankind computer dependency is increased day by day, user is more and more high to the requirement of the reliability of computer system.For example in computer monitor and control system, enterprise assets planning field such as (ERP) system, computer fault diagnosis etc., usually need Power-On Self-Test (the Power On Self Test of supervisory computer system, POST) process, whether smooth to understand POST process, and when the problem of generation, immediately know the origin cause of formation of problem, to take suitable countermeasure.
In addition, at motherboard now in design, to manufacture or in maintenance process, often need present the current functioning condition of the Basic Input or Output System (BIOS) (BIOS) of motherboard by the seven segment digital tubes of test chart (Debugcard) (Seven-segment display).In general, in the POST process of computer system, the BIOS on motherboard can send hexadecimal debugging code (Debug code) to 80 interfaces (80Port), and different debugging code represents different POST information.When after the debugging code that test chart receives from 80 interfaces, the seven segment digital tubes of test chart can show the debugging code that above-mentioned BIOS is exported by 80 interfaces.Afterwards, carry out motherboard design, the personnel of manufacture or maintenance can according to the debugging code shown by seven segment digital tubes, the meaning of inquiry debugging representated by code, to take suitable countermeasure, gets rid of the problem that motherboard produces.But, because test chart that test chart is traditional can only transmit the information of a byte (byte) at every turn, seven segment digital tubes directly cannot show the meaning of debugging representated by code, thus such debud mode for design, to manufacture or inconvenient maintenance personal.
In addition, the test chart of part is also had to be receive debugging code by the serial line interface (serial port) on motherboard from BIOS.But, because modern computer system moves towards compact trend, many motherboards can't be provided with serial line interface.Thus, test chart namely because being connected with motherboard, and cannot be debugged.Moreover, even motherboard is provided with serial line interface, but show debugging code because test chart is still by its seven segment digital tubes, thus such debud mode for design, to manufacture or still inconvenient maintenance personal.Summary of the invention
One embodiment of the invention provide a kind of debug system.Debug system comprises motherboard, debugging apparatus and terminating machine.Motherboard comprises Basic Input or Output System (BIOS) (BIOS) and System Management Bus (SMBUS).Basic Input or Output System (BIOS) in order to initializing computer system, and produces multiple Debugging message in the process of initializing computer system.System Management Bus is in order to export above-mentioned multiple Debugging message.Debugging apparatus comprises receiving interface, microprocessor and serial output interface.Receiving interface is coupled to System Management Bus, in order to receive above-mentioned multiple Debugging message from System Management Bus.Microprocessor is coupled to receiving interface, in order to above-mentioned multiple Debugging message is decoded into multiple serial information.Each serial information has debugging code and text string (text string), and text string is in order to describe the state of computer system when the initialization.Serial output interface is coupled to microprocessor, in order to export above-mentioned multiple serial information serially.Terminating machine is coupled to serial output interface, in order to show debugging code and the text string of above-mentioned multiple Debugging message.
One embodiment of the invention provide a kind of adjustment method.Adjustment method comprises the Basic Input or Output System (BIOS) (BIOS) by motherboard, initializing computer system, and in the process of initializing computer system, produce multiple Debugging message; By the receiving interface of debugging apparatus, receive above-mentioned multiple Debugging message from the System Management Bus (SMBUS) of motherboard; By the microprocessor of debugging apparatus, above-mentioned multiple Debugging message is decoded into multiple serial information, wherein each serial information has debugging code and text string, and text string is in order to describe the state of computer system when the initialization.By the serial output interface of debugging apparatus, export above-mentioned multiple serial information; And terminating machine receives above-mentioned multiple serial information from serial output interface, and show debugging code and the text string of above-mentioned multiple serial information.
One embodiment of the invention provide a kind of debugging apparatus.Debugging apparatus comprises receiving interface, microprocessor and serial output interface.Receiving interface is in order to receive multiple Debugging message from System Management Bus (SMBUS).Described microprocessor is coupled to receiving interface, in order to above-mentioned multiple Debugging message is decoded into multiple serial information.Each serial information has debugging code and text string, and text string is in order to describe the state of computer system when the initialization.Serial output interface is coupled to microprocessor, in order to export above-mentioned multiple serial information serially.
By the debug system of the embodiment of the present invention and debugging apparatus thereof and method, the Debugging message produced in computer system initialization procedure is decoded into serial information, and the debugging code in serial information and text string are shown in terminating machine, and the system mistake that computer system occurs clearly is described due to shown text string, therefore carry out the design of computer system or motherboard, the personnel of manufacture or maintenance must not inquire about the meaning of debugging representated by code again, clearly can understand which type of system mistake the system mistake that computer system produces is.Therefore, compared to the debud mode of prior art, the present invention can improve efficiency when debugging computer system significantly.In addition, under the trend that computing machine size is done less and less, on the motherboard that size is less, serial line interface (Serial port) is not shown in again, and due to this case be, by System Management Bus (SMBUS), Debugging message is sent to debugging apparatus from motherboard, and existing motherboard most on the market includes DIMM (the Dual In-line MemoryModule be connected with System Management Bus (SMBUS), DIMM), the interfaces such as PCI-E interface or Mini PCIE interface, therefore the present invention is applicable to debug the motherboard of existing many miniaturizations on the market.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of one embodiment of the invention debug system.
Fig. 2 is the process flow diagram of one embodiment of the invention adjustment method.
Wherein, description of reference numerals is as follows:
100 debug systems
200 computer systems
210 motherboards
220 Basic Input or Output System (BIOS)s
230 System Management Buss
232 serial clock pulse lines
234 serial data lines
240 device interfaces
242,244 pins
300 debugging apparatus
310 receiving interfaces
320 microprocessors
330 serial output interface
340 firmwares
400 terminating machines
410 display screens
420 input interfaces
430 hyper terminal machine programs
C
1to C
ndebugging code
SE
1to SE
ndebugging message
ST
1to ST
nserial information
T
1to T
ntext string
S210 to S250 step
Embodiment
Please refer to Fig. 1, Fig. 1 is the functional block diagram of one embodiment of the invention debug system 100.Debug system 100 comprises motherboard 210, debugging apparatus 300 and terminating machine 400.Motherboard 210 includes Basic Input or Output System (BIOS) (Basic Input Output System, BIOS) 220 and System Management Bus (SystemManagement Bus, SMBUS) 230.Basic Input or Output System (BIOS) 220 is in order to initializing computer system 200, and multiple Debugging message (Debugmessage) SE for producing in the process of initializing computer system 200
1to SE
n.The operation of above-mentioned initializing computer system 200 can comprise Power-On Self-Test (PowerOn Self Test, POST).In an embodiment of the present invention, Basic Input or Output System (BIOS) 220 is the Basic Input or Output System (BIOS) of unified Extensible Firmware Interface (Unified Extensible Firmware Interface, UEFI), but the present invention is not as limit.
When computer system 200 starts, the procedure code of Basic Input or Output System (BIOS) 220 can be loaded into and perform, with initializing computer system 200 by motherboard 210.In the process of initializing computer system 200, by performing the procedure code of input-output system 220, motherboard 210 can by above-mentioned multiple Debugging message SE
1to SE
nbe sent to System Management Bus 230, then by System Management Bus 230 by above-mentioned multiple Debugging message SE
1to SE
nbe sent to debugging apparatus 300.Therefore, by performing the procedure code of input-output system 220, tradition can be exported the mode of debugging code by 80 interfaces (80Port), changing and export Debugging message SE by System Management Bus 230
1to SE
n.In addition, System Management Bus 230 comprises serial clock pulse line (SerialClock line, SCL) 232 and serial data line (Serial Data line, SDA) 234.Motherboard 210 by south bridge wafer SMBUS controller and by the serial clock pulse line 232 of System Management Bus 230 and serial data line 234 by above-mentioned multiple Debugging message SE
1to SE
nbe sent to debugging apparatus 300.
Debugging apparatus 300 can be a test chart (debug card) or the device be integrated in computer system 200.Debugging apparatus 300 comprises receiving interface 310, microprocessor 320, serial output interface 330 and firmware (firmware) 340.Receiving interface 310 is coupled to System Management Bus 230, in order to receive above-mentioned multiple Debugging message SE from System Management Bus 230 for System Management Bus slave unit (SMBUSSlave Device)
1to SE
n.Microprocessor 320 is coupled to receiving interface 310, in order to the procedure code that performs firmware 340 with by above-mentioned multiple Debugging message SE
1to SE
nbe decoded into multiple serial information ST
1to ST
n.Each serial information ST
1to ST
nthere is debugging code (as C
1to C
none of them debugs code) and text string (as T
1to T
none of them text string), and text string T
1to T
nrespectively in order to describe the state of computer system 200 in initialization procedure.Different debugging code C
1to C
nand the text string T of correspondence
1to T
nthe described state of computer system 200 in initialization procedure is not identical.Serial output interface 330 is coupled to microprocessor 320, in order to export the serial information ST that microprocessor 320 produces
1to ST
n.In an embodiment of the present invention, serial output interface 330 adopts the mode of serial (serial) to transmit above-mentioned multiple serial information ST
1to ST
nto terminating machine 400.Wherein, serial output interface 330 can be the serial line interfaces such as USB (universal serial bus) (Universal Serial Bus, USB) output interface, com interface (COM port), but the present invention is not as limit.
In addition, terminating machine 400 has input interface 410 and display screen 420.Input interface 410 is coupled to the serial output interface 330 of debugging apparatus 300, and terminating machine 400 receives above-mentioned multiple serial information ST by input interface 410 from serial output interface 330
1to ST
n.When terminating machine 400 receives above-mentioned multiple serial information ST
1to ST
nafterwards, terminating machine 400 can by above-mentioned multiple serial information ST
1to ST
ndebugging code C
1to C
nand text string T
1to T
nbe shown in display screen 420.Thus, in the initialized process of computer system 200, terminating machine 400 can immediately show Debugging message S
ein text string S
t, and the personnel of the design of computer system 200, manufacture or maintenance are by the text string S shown by display screen 420
tunderstand computer system 200 and whether produce system mistake in initialization procedure, and when computer system 200 generation systems mistake, can understand which type of system mistake the system mistake that computer system 200 produces is immediately, and carry out follow-up debugging.In addition, terminating machine 400 can be a personal computer and comprises hyper terminal machine (Hyper terminal) program 430, and terminating machine 400 is by performing hyper terminal machine program 430 to receive and the above-mentioned multiple serial information ST of identification
1to ST
n, and control display screen 420 display debugging code C
1to C
nand text string T
1to T
n.
In an embodiment of the present invention, computer system 200 separately comprises device interface 240, and device interface 240 can be DIMM (Dual In-line Memory Module, DIMM), PCI-E interface or Mini PCIE interface.Wherein two pins 242 and 244 of device interface 240 are respectively coupled to serial clock pulse line 232 and the serial data line 234 of System Management Bus 230, the receiving interface 310 of debugging apparatus 300 is then coupled to above-mentioned two pins 242 and 244, the Debugging message SE exported with receiving system management bus 230
1to SE
n.Because current most computing machine motherboard is provided with DIMM, PCI-E interface or Mini PCIE interface, and DIMM, PCI-E interface or Mini PCIE interface all can comprise the above-mentioned two pins 242 and 244 being coupled to System Management Bus 230, therefore debugging apparatus 300 of the present invention is by being connected to the mode of the two pins 242 and 244 of device interface 240, the current most computing machine motherboard on the market of test, therefore the unmatched problem of interface between debugging apparatus 300 and computer system 200 can not be produced.
Please refer to Fig. 2 also simultaneously with reference to the process flow diagram that Fig. 1, Fig. 2 are one embodiment of the invention adjustment method.In this embodiment, above-mentioned adjustment method comprises the following steps:
Step S210: by the Basic Input or Output System (BIOS) 220 of motherboard 210, initializing computer system 200, and in the process of initializing computer system 200, produce multiple Debugging message SE
1to SE
n;
Step S220: by the receiving interface 310 of debugging apparatus 300, receives above-mentioned multiple Debugging message SE from the System Management Bus 230 of motherboard 210
1to SE
n;
Step S230: by the microprocessor 320 of debugging apparatus 300, by above-mentioned multiple Debugging message SE
1to SE
nbe decoded into multiple serial information ST
1to ST
n;
Step S240: by the serial output interface 330 of debugging apparatus 300, exports above-mentioned multiple serial information ST
1to ST
n; And
Step S250: terminating machine 400 receives above-mentioned multiple serial information ST from serial output interface 330
1to ST
n, and show above-mentioned multiple serial information ST
1to ST
nin debugging code C
1to C
nand text string T
1to T
n.
In sum, by debug system and the debugging apparatus thereof of the embodiment of the present invention, debugging code in Debugging message and the information of text string can be captured, decipher out and shown, and the system mistake that computer system occurs clearly is described due to shown text string, therefore carry out the design of computer system or motherboard, the personnel of manufacture or maintenance must not inquire about the meaning of debugging representated by code again, clearly can understand which type of system mistake the system mistake that computer system produces is.Therefore, compared to the debud mode of prior art, the present invention can improve efficiency when debugging computer system significantly; And for small size now and without serial line interface motherboard for, provide debug system and a method easily.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a debug system, is characterized in that: comprise motherboard, debugging apparatus and terminating machine;
Described motherboard comprises Basic Input or Output System (BIOS) and System Management Bus, described Basic Input or Output System (BIOS), in order to initialization one computer system, and in the process of this computer system of initialization, produces multiple Debugging message; Described System Management Bus is in order to export described multiple Debugging message;
Described debugging apparatus comprises receiving interface, microprocessor and serial output interface, and described receiving interface is coupled to this System Management Bus, in order to receive described multiple Debugging message from described System Management Bus; Described microprocessor is coupled to this receiving interface, and in order to described multiple Debugging message is decoded into multiple serial information, serial information described in each has a debugging code and a text string, and text string is in order to describe state during this computer system initialization; Described serial output interface is coupled to described microprocessor, in order to export described multiple serial information serially;
Described terminating machine is coupled to this serial output interface, in order to show debugging code and the text string of described multiple Debugging message.
2. debug system as claimed in claim 1, it is characterized in that, this System Management Bus comprises a serial clock pulse line and a serial data line, and this receiving interface receives the described multiple Debugging message of transmission from this serial clock pulse line and this serial data line.
3. debug system as claimed in claim 2, it is characterized in that, this serial clock pulse line and this serial data line are coupled to two pins of a DIMM of this motherboard, PCI-E interface or Mini PCIE interface, and this receiving interface of this debugging apparatus is coupled to this two pins.
4. debug system as claimed in claim 1, is characterized in that, this Basic Input or Output System (BIOS) is the Basic Input or Output System (BIOS) of a unified Extensible Firmware Interface.
5. debug system as claimed in claim 1, is characterized in that, this terminating machine is by multiple serial information described in execution one hyper terminal machine process accepts and identification.
6. an adjustment method, comprising:
By a Basic Input or Output System (BIOS) of a motherboard, initialization one computer system, and in the process of this computer system of initialization, produce multiple Debugging message;
By a receiving interface of a debugging apparatus, receive described multiple Debugging message from a System Management Bus of this motherboard;
By a microprocessor of this debugging apparatus, described multiple Debugging message is decoded into multiple serial information, wherein serial information described in each has a debugging code and a text string, and text string is in order to describe state during this computer system initialization;
By a serial output interface of this debugging apparatus, export described multiple serial information; And
One terminating machine receives described multiple serial information from this serial output interface, and shows debugging code and the text string of described multiple serial information.
7. adjustment method as claimed in claim 6, it is characterized in that, this System Management Bus comprises a serial clock pulse line and a serial data line, and this receiving interface receives the described multiple Debugging message of transmission from this serial clock pulse line and this serial data line.
8. adjustment method as claimed in claim 7, it is characterized in that, this serial clock pulse line and this serial data line are coupled to two pins of a DIMM of this motherboard, PCI-E interface or Mini PCIE interface, and this receiving interface of this debugging apparatus is coupled to this two pins.
9. adjustment method as claimed in claim 6, is characterized in that, this Basic Input or Output System (BIOS) is the Basic Input or Output System (BIOS) of a unified Extensible Firmware Interface.
10. a debugging apparatus, comprising:
One receiving interface, in order to receive multiple Debugging message from a System Management Bus;
One microprocessor, is coupled to this receiving interface, and in order to described multiple Debugging message is decoded into multiple serial information, serial information described in each has a debugging code and a text string, and text string is in order to describe the state of a computer system when the initialization; And
One serial output interface, is coupled to this microprocessor, in order to export described multiple serial information serially.
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| CN201310468038.7A CN104572423A (en) | 2013-10-09 | 2013-10-09 | Debugging system and debugging device and method thereof |
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Application publication date: 20150429 |