Embodiment
(embodiment from mutual tolerance testing circuit and capacitance type touch-control panel)
Please refer to Fig. 2, Fig. 2 is the circuit diagram from mutual tolerance testing circuit that the embodiment of the present invention provides.The first electrode 111, second electrode 112, commutation circuit 13, first capacitive detection circuit 14 and the second capacitive detection circuit 15 is comprised from mutual tolerance testing circuit 1.In fig. 2, the first electrode 111 and the second electrode 112 represent with node in circuit diagram, and actual first electrode 111 and the second electrode 112 are the electrodes as the wire form in Fig. 1.In addition, the noble potential 19 in Fig. 2 is independently high voltage levels (level), and not identical with supply voltage VDD, earthing potential represents with GND.
First electrode 111 has first from holding C
bR.Second electrode 112 capacitive coupling first electrode 111 and form mutual tolerance Cu, and the second electrode 112 has second from holding C
bL.Commutation circuit 13 couples the first electrode 111 and the second electrode 112.First capacitive detection circuit 14 and the second capacitive detection circuit 15 couple the first electrode 111 and the second electrode 112 respectively by commutation circuit 13.
In order to do mutual tolerance to the first electrode 111 and the second electrode 112 and from the detection held, commutation circuit 13 is in order to the flow direction of control signal and electric current.In detail, certainly C is held in order to what detect the first electrode 111 and the second electrode 112
bR, C
bLwith mutual tolerance Cu, the first capacitive detection circuit 14 and the second capacitive detection circuit 15 can different operator schemes detect.
In mutual tolerance context of detection, one of them of the first electrode 111 and the second electrode 112 is scan electrode, provides drive singal Vdrv, and another in the first electrode 111 and the second electrode 112 is sensing electrode, with reference to follow-up Fig. 3 embodiment.Certainly holding context of detection, as shown in Figure 2, what the first capacitive detection circuit 14 detected the first electrode 111 holds C certainly
bR, what the second capacitive detection circuit 15 detected the second electrode 112 holds C certainly
bL.In detection from holding C
bL, C
bRtime, the mutual tolerance Cu between the first electrode 111 and the second electrode 112 will not affect the detection from holding as far as possible.Next the detection of mutual tolerance is first described.
Referring to Fig. 2 and Fig. 3, Fig. 3 be the embodiment of the present invention provide operate in the current lens unit and the circuit diagram of reverse circuit that mutual tolerance detects.From mutual tolerance testing circuit 1 when carrying out mutual tolerance and detecting, the current lens unit 141 that can utilize Fig. 3 and the reverse circuit 142 being connected current lens unit 141 are to detect mutual tolerance value.The current lens unit 141 of Fig. 3 can be current lens unit 141 or the current lens unit 151 of Fig. 2.In the present embodiment, provide scanning drive signal Vdrv by the second electrode 112, the first electrode 111 is sensing electrode, but therefore the present invention does not limit.
Current lens unit 141 comprises P-type crystal pipe P1, P2, P3 and N-type transistor N1, N2, N3.Current lens unit 141 is made up of two current mirrors, and the two ends of two current mirrors are connected to each other, and the other two ends of two current mirrors connect supply voltage VDD and ground connection GND respectively.One of them current mirror above-mentioned is made up of P-type crystal pipe P1, P2 and N-type transistor N1 and is applied in bias voltage biasa, and another current mirror above-mentioned is then made up of P-type crystal pipe P3 and N-type transistor N2, N3 and is applied in bias voltage biasb.
Then, the detailed construction of current lens unit 141 is described further.The source electrode of P-type crystal pipe P1, P2 connects supply voltage VDD, and the grid of P-type crystal pipe P1, P2 is connected to each other.The drain electrode of N-type transistor N1 connects grid and the drain electrode of P-type crystal pipe P1, and the source electrode of N-type transistor N1 and the drain electrode of P-type crystal pipe P2 are connected first end A and the second end B respectively, wherein first end A is in order to receive input current Iin, and the second end B is in order to export output voltage Vout to follow-up signal sampling circuit (not shown).
The source electrode of N-type transistor N2, N3 connects ground connection GND, and the grid of N-type transistor N2, N3 is connected to each other.The drain electrode of P-type crystal pipe P3 connects grid and the drain electrode of N-type transistor N2, and the source electrode of P-type crystal pipe P3 and the drain electrode of N-type transistor N3 are connected first end A and the second end B respectively.
Then, the detailed construction of reverse circuit 142 is described further.Reverse circuit 142 comprises electric capacity Cint and multiple interrupteur SW 1, SW2, SW3, SW4.Interrupteur SW 1, SW2, SW3, SW4 are controlled by electric discharge reset signal Φ respectively
dCRST, charging reset signal Φ
cRST, discharge signal Φ
dCwith charging signals Φ
c.The two ends of interrupteur SW 1 connect the electric discharge reset voltage V of three level respectively
rST1with the second end B, and the two ends of interrupteur SW 2 connect the electric discharge reset voltage V of the first level respectively
rST2with the second end B.The two ends of interrupteur SW 3 connect one end of supply voltage VDD and electric capacity Cint respectively, and the two ends of interrupteur SW 4 connect one end of ground connection GND and electric capacity Cint respectively.The other end of electric capacity Cint connects the second end B.
In embodiments of the present invention, discharge signal Φ
dCwith electric discharge reset signal Φ
dCRSTfor group control signal of a during for discharging to electric capacity Cint, in addition, charging signals Φ
cwith charging reset signal Φ
cRSTfor group control signal of a during for charging to electric capacity Cint.When the input current Iin corresponding to drive singal Vdrv is negative electric current, interrupteur SW 1 and SW3 can disconnect, and (namely also discharge reset signal Φ
dCRSTwith discharge signal Φ
dCfor logic low), interrupteur SW 4 can conducting (also be charging signals Φ
cfor logic high), and only have input current Iin corresponding to drive singal Vdrv from a period of time temporary transient conducting before positive electric current becomes negative electric current in interrupteur SW 2.By above-mentioned description, current lens unit 141 and reverse circuit 142 are at charging signals Φ
cduring for logic high voltage level, output voltage Vout can rise to second electrical level by the first level.
When the input current Iin corresponding to drive singal Vdrv is positive electric current, interrupteur SW 2 and SW4 can disconnect, and (namely also charge reset signal Φ
cRSTwith charging signals Φ
cfor logic low), interrupteur SW 3 can conducting (also be discharge signal Φ
dCfor logic high), and only have input current Iin corresponding to drive singal Vdrv from a period of time temporary transient conducting before the electric current born becomes positive electric current in interrupteur SW 1.By above-mentioned description, current lens unit 141 and reverse circuit 142 are at discharge signal Φ
dCduring for logic high voltage level, output voltage Vout can drop to the 4th level by three level.
Please then with reference to Fig. 3 and Fig. 4, Fig. 4 be the part signal of the reverse circuit of Fig. 3 oscillogram.Before drive singal Vdrv becomes logic high by logic low, discharge signal Φ
dChigh level (interrupteur SW 3 meeting conducting) can be become, charging signals Φ from low level
clow level (interrupteur SW 4 can disconnect) can be maintained, and electric discharge reset signal Φ
dCRSTalso high level (interrupteur SW 1 meeting conducting) can be become, first output voltage Vout is reset to reset voltage V from low level
rST1.Then, drive singal Vdrv becomes logic high by logic low, and electric discharge reset signal Φ
dCRSTalso low level (interrupteur SW 1 can disconnect) can be become from high level.Now, discharge signal Φ
dCmaintain logic high (interrupteur SW 3 meeting conducting), to make amplified current discharge to electric capacity Cint, and export the output voltage Vout between three level and the 4th level.Then, discharge signal Φ
dCmeeting is sampled and keep, and output voltage Vout also can be carried out sampling, keep or overturning.
Then, discharge signal Φ
dClow level (interrupteur SW 3 can disconnect) can be become from high level, and charging signals Φ
cwith charging reset signal Φ
cRSTand then become high level (interrupteur SW 2 and SW4 meeting conducting) from low level, with before drive singal Vdrv becomes logic low by logic high, first output voltage Vout is reset to reset voltage V
rST2.Afterwards, drive singal Vdrv becomes logic high by logic low, and charging reset signal Φ
cRSTalso low level (interrupteur SW 2 can disconnect) can be become from high level.Now, charging signals Φ
cmaintain logic high (interrupteur SW 4 meeting conducting), to make amplified current charge to electric capacity Cint, and export the output voltage Vout between the first level and second electrical level.Then, charging signals Φ
cmeeting is sampled and keep, and output voltage Vout also can be carried out sampling, keep or overturning.
Foregoing describe the operation carrying out mutual tolerance detection from mutual tolerance testing circuit 1 of the embodiment of the present invention, next the operation carrying out certainly holding detection from mutual tolerance testing circuit 1 is described.
Carrying out in time holding detection, in the first operational phase, be called that commutation circuit 13 makes the first electrode 111 and the second electrode 112 be connected to noble potential 19 from holding reset phase (reset phase) in the present embodiment.Noble potential 19 is independently high voltage levels, not identical with supply voltage VDD, but, in the present embodiment, the voltage of noble potential 19 is supply voltage VDD, and the present embodiment is only a kind of implementation of noble potential 19, and the present invention does not limit the implementation of noble potential 19.Then, in the second operational phase, be called from discharge capacitor stage (discharge phase) in the present embodiment, commutation circuit 13 makes the first electrode 111 and the second electrode 112 disconnect with noble potential 19, and makes the first electrode 111 and the second electrode 112 be connected to the first capacitive detection circuit 14 and the second capacitive detection circuit 15 respectively.First capacitive detection circuit 14 and the second capacitive detection circuit 15 hold C certainly in order to what detect the first electrode 111 and the second electrode 112 respectively
bR, C
bL, the first capacitive detection circuit 14 is identical with the second capacitive detection circuit 15.
Again simultaneously with reference to Fig. 2 and Fig. 3, based on the describing of current lens unit 141 above for Fig. 3.First capacitive detection circuit 14 comprises current lens unit 141 and electric capacity Cint.Current lens unit 141 has first end A and the second end B, first end A is in order to be coupled to the first electrode 111, current lens unit 141 does phase reversal to the sensing signal received by the first electrode 111, and producing mirror image sensing signal at the second end B of current lens unit 141, mirror image sensing signal is in order to represent certainly holding of the first electrode 111.The first end of electric capacity Cint connects noble potential, and second end of electric capacity Cint connects the second end B of current lens unit 141.
Because the first capacitive detection circuit 14 is identical with the second capacitive detection circuit 15, so the second capacitive detection circuit 15 comprises current lens unit 151 and electric capacity Cint.Current lens unit 151 has first end A and the second end B, first end A is in order to be coupled to the second electrode 112, current lens unit 151 does phase reversal to the sensing signal received by the second electrode 112, and producing mirror image sensing signal at the second end B of current lens unit 151, mirror image sensing signal is in order to represent certainly holding of the second electrode 112.The first end of electric capacity Cint connects the second end B of the second end connection current lens unit 151 of supply voltage VDD, electric capacity Cint.
As above for Fig. 3 current lens unit 141 describe, briefly, current lens unit 141 has the first current mirror (be made up of P-type crystal pipe P1, P2), the first bias transistor (i.e. N-type transistor N1), the second bias transistor (i.e. P-type crystal pipe P3) and the second current mirror (be made up of N-type transistor N2, N3).First current mirror and the second current mirror are connected to supply voltage VDD and ground connection GND respectively.The input end of the first current mirror and the input end of the second current mirror are connected to the first end A of current lens unit 141 respectively by the first bias transistor (N-type transistor N1) and the second bias transistor (P-type crystal pipe P3).The output terminal of the first current mirror and the output terminal of the second current mirror are connected to the second end B of current lens unit 141.Current lens unit 151 is identical with current lens unit 141, repeats no more.
Referring again to Fig. 2, in order to reach the operation of the first operational phase and the second operational phase, commutation circuit 13 comprises the first switch 131, second switch 132, the 3rd switch 133, the 4th switch 134 and interrupteur SW 5 in the present embodiment.When carrying out from appearance detection, interrupteur SW 5 is also the part belonging to commutation circuit 13, and one end of interrupteur SW 5 connects the second end B of the first capacitive detection circuit 14 or the second capacitive detection circuit 15, and the other end of interrupteur SW 5 connects reset voltage V
rST1.Interrupteur SW 5 is all controlled by from holding reset signal Φ
rST, and certainly hold reset signal Φ
rSTelectric discharge reset signal Φ
dCRSTwith charging reset signal Φ
cRSTunion (OR), namely also from holding reset signal Φ
rST=(Φ
dCRSToR Φ
cRST).It is worth mentioning that, the present invention does not limit the enforcement aspect of commutation circuit 13, detects as long as commutation circuit 13 can complete mutual tolerance, and completes the above-mentioned operation from holding the first operational phase and the second operational phase detected.
Such as: with regard to the circuit of Fig. 2, the first switch 131 is controlled by from holding reset signal, and its two ends connect the first electrode 111 and noble potential 19 respectively.Second switch 132 is controlled by from holding reset signal Φ
rST, its two ends connect the second electrode 112 and noble potential 19 respectively.3rd switch 133 is controlled by from discharge capacitor signal
its two ends connect the first electrode 111 and the first capacitive detection circuit 14 respectively.4th switch 134 is controlled by from discharge capacitor signal
its two ends connect the second electrode 112 and the second capacitive detection circuit 15 respectively.Described from holding reset signal Φ
rSTwith from discharge capacitor signal
inverting each other.
Please refer to Fig. 5 A, Fig. 5 A be example of the present invention provide from the circuit diagram of mutual tolerance detection circuit operation in the first stage.In the first operational phase, high level is become from low level from appearance reset signal, first switch 131 and second switch 132 can conductings, the 3rd switch 133 and the 4th switch 134(Fig. 5 A not shown) can disconnect, be connected to noble potential 19 to make the first electrode 111 and the second electrode 112.Now, because from holding reset signal Φ
rSTbecome high level from low level, make interrupteur SW 5 meeting conducting, first output voltage Vout is reset to reset voltage V
rST1.
Please refer to Fig. 5 B, Fig. 5 B be example of the present invention provide from the circuit diagram of mutual tolerance detection circuit operation in subordinate phase.In the second operational phase, from holding reset signal Φ
rSTlow level is become from high level, first switch 131 and second switch 132 can disconnect, 3rd switch 133 and the 4th switch 134(Fig. 5 B not shown) can conducting, be connected respectively to make the first electrode 111 and the second electrode 112 side that first capacitive detection circuit 14 and second capacitive detection circuit 15(Fig. 5 B only illustrate the first capacitive detection circuit 14).Now, because from holding reset signal Φ
rSTbecome low level from high level, interrupteur SW 5 can be disconnected.As shown in Figure 5 B, the first electrode 111 certainly hold C
bRthe sensing signal produced can be passed to the first end A of the first capacitive detection circuit 14, and the second end B of the first capacitive detection circuit 14 produces mirror image sensing signal, and mirror image sensing signal becomes output voltage Vout, for follow-up sample of signal and maintenance.Because the first capacitive detection circuit 14 is identical with the second capacitive detection circuit 15, so certainly hold C at detection first electrode 111
bRtime (or detect the second electrode 112 certainly hold C
bLtime), the potential change of the second electrode 112 can be roughly the same with the potential change of the first electrode 111.So, mutual tolerance Cu is then not easy impact from holding C
bR(or certainly hold C
bL) detection.
From the above, the part that can form capacitance type touch-control panel from mutual tolerance testing circuit 1 of the present embodiment, appearance and the mutual tolerance certainly of each touch control electrode of described capacitance type touch-control panel can utilize above-mentioned detecting from mutual tolerance testing circuit 1.Described capacitance type touch-control panel comprises multiple electrode and multiple from mutual tolerance testing circuit 1.Wherein, any two adjacent described electrodes are respectively the first electrode and the second electrode.Multiple from mutual tolerance testing circuit 1 in order to detect respectively the first electrode and the second electrode from holding, and detect the first adjacent electrode and the mutual tolerance of the second electrode.
(another embodiment from mutual tolerance testing circuit and capacitance type touch-control panel)
Please refer to Fig. 6, Fig. 6 is the circuit diagram from mutual tolerance testing circuit that another embodiment of the present invention provides.Roughly the same from mutual tolerance testing circuit 1 from mutual tolerance testing circuit 1 ' and Fig. 2 of the present embodiment, its difference is mainly the second capacitive detection circuit 15 to replace with artificial circuit 18.Please refer to detailed description below.
The first electrode 111, second electrode 112 and commutation circuit 113 is comprised from mutual tolerance testing circuit 1 '.Second electrode 112 capacitive coupling first electrode 111 and form mutual tolerance.Commutation circuit 13 couples the first electrode 111 and the second electrode 112.The detection of mutual tolerance as described in Fig. 3 of previous embodiment, therefore can repeat no more.About the detection from appearance, in the first operational phase, commutation circuit 13 makes the first electrode 111 and the second electrode 112 be connected to noble potential 19.Then, in the second operational phase, commutation circuit 13 makes the first electrode 111 and the second electrode 112 disconnect with noble potential 19, and makes the first electrode 111 be connected to capacitive detection circuit 14, make the second electrode 112 be connected to artificial circuit 18, capacitive detection circuit 14 holds C certainly in order to what detect the first electrode 111
bR.Artificial circuit 18 has the charge-discharge characteristic of artificial capacitor testing circuit 14 to the first electrode 111, and what make to detect the first electrode 111 when capacitive detection circuit 14 holds C certainly
bRtime, the voltage differences of the second electrode 112 and the first electrode 111 minimizes.
In more detail, identical with previous embodiment, in order to reach the operation of the first operational phase and the second operational phase, commutation circuit 13 comprises the first switch 131, second switch 132, the 3rd switch 133 and the 4th switch 134 in the present embodiment.When carrying out from appearance detection, interrupteur SW 1 is also the part belonging to commutation circuit 13, and one end of interrupteur SW 5 connects the second end B of the first capacitive detection circuit 145, and the other end of interrupteur SW 5 connects reset voltage V
rST1, interrupteur SW 5 is controlled by from holding reset signal Φ
rST.It is worth mentioning that, the present invention does not limit the enforcement aspect of commutation circuit 13, detects as long as commutation circuit 13 can complete mutual tolerance, and completes the above-mentioned operation from holding the first operational phase and the second operational phase detected.
First switch 131 is controlled by from holding reset signal Φ
rST, its two ends connect the first electrode 111 and noble potential 19 respectively.Second switch 132 is controlled by from holding reset signal Φ
rST, its two ends connect the second electrode 112 and noble potential 19 respectively.3rd switch 133 is controlled by from discharge capacitor signal
its two ends connect the first electrode 111 and capacitive detection circuit 14 respectively.4th switch 134 is controlled by from discharge capacitor signal
its two ends connect the second electrode 112 and artificial circuit 18 respectively.Described from holding reset signal Φ
rSTwith from discharge capacitor signal
inverting each other.
Capacitive detection circuit 14 comprises current lens unit 141 and electric capacity Cint.Current lens unit 141 tool is by first end A and the second end B, first end A is in order to be coupled to the first electrode 111, in order to do phase reversal to the sensing signal received by the first electrode 111, and producing mirror image sensing signal at the second end B of current lens unit 141, mirror image sensing signal is in order to represent certainly holding of the first electrode 111.The first end of electric capacity Cint connects the second end B of the second end connection current lens unit 151 of supply voltage VDD, electric capacity Cint.
As describing for the current lens unit 141 of Fig. 3 in preceding embodiment, current lens unit 141 has the first current mirror (be made up of P-type crystal pipe P1, P2), the first bias transistor (i.e. N-type transistor N1), the second bias transistor (i.e. P-type crystal pipe P3) and the second current mirror (be made up of N-type transistor N2, N3).First current mirror and the second current mirror are connected to supply voltage VDD and ground connection GND respectively.The input end of the first current mirror and the input end of the second current mirror are connected to the first end A of current lens unit 141 respectively by the first bias transistor (N-type transistor N1) and the second bias transistor (P-type crystal pipe P3).The output terminal of the first current mirror and the output terminal of the second current mirror are connected to the second end B of current lens unit 141.
Artificial circuit 18 comprises the first transistor P1 ', the 3rd bias transistor N1 ' of the connection of diode form, the transistor seconds N2 ' of diode type of attachment and the 4th bias transistor P3 '.The first transistor P1 ' that diode form connects is connected to supply voltage VDD.Between the first transistor P1 ' that 3rd bias transistor N1 ' is connected to the connection of diode form and the second electrode 112.The transistor seconds N2 ' of diode type of attachment is connected to ground connection GND.Between the transistor seconds N2 ' that 4th bias transistor P3 ' is connected to the connection of diode form and the second electrode 112.
The first transistor P1 ', the 3rd bias transistor N1 ' that diode form connects, the transistor seconds N2 ' of diode type of attachment and the 4th bias transistor P3 ' are identical with the P-type crystal pipe P1 of current lens unit 141, N-type transistor N1, N-type transistor N2 and P-type crystal pipe P3 respectively.In other words, artificial circuit 18 has the importation identical with current lens unit 141, certainly holds C at detection first electrode 111
bRtime, the potential change of the second electrode 112 can be roughly the same with the potential change of the first electrode 111.So, mutual tolerance Cu is then not easy impact from holding C
bRdetection.
It should be noted that artificial circuit 18 is only a part for current lens unit 141.Therefore, compared to the embodiment of Fig. 2, in order to reduce the area of testing circuit, the electrode of capacitance type touch-control panel and the connection of capacitive detection circuit can be realized by multiplexer (not shown).By the control of multiplexer, will detected Electrode connection be needed to testing circuit 14, the adjacent electrode (or other electrodes) of detected electrode then can connect artificial circuit 18.Therefore, do not need the same with Fig. 2 embodiment, do not need all electrodes all to connect a capacitive detection circuit, reduce circuit area by this.
Please refer to Fig. 7 A to Fig. 7 C, Fig. 7 A to Fig. 7 C is the detection schematic diagram of capacitance type touch-control panel when capacitive detection circuit is less than number of active lanes that another embodiment of the present invention provides.As Fig. 7 A, there is for capacitance type touch-control panel the touch control electrode of 14x8, suppose that the number of capacitive detection circuit is ten, once only detect certainly holding of ten electrodes simultaneously, electrode #1 is connected to capacitive detection circuit to electrode #10, represent with AFE#1 to AFE#10 in fig. 7, other electrodes #11 to #22 then connects artificial circuit, represents in fig. 7 with Dummy#11 to Dummy#22.Then, as Fig. 7 B, the while of for the second time again, detecting electrode #11 is to electrode #20, represent with AFE#11 to AFE#20 in figure 7b, other electrodes #1 to electrode #10, electrode #21 and electrode #22 then connect artificial circuit, represent in figure 7b with Dummy#1 to Dummy#10 and Dummy#21, Dummy#22.Then, as Fig. 7 C, detect not yet detected electrode #21 and electrode #22 simultaneously, represent with AFE#21 and AFE#22 in fig. 7 c.In addition, electrode #1 to electrode #8 connects capacitive detection circuit, and electrode #9 then connects artificial circuit to electrode #20, represents in fig. 7 c with AFE#1 to AFE#8 and Dummy#9 to Dummy#20.
From the above, the part that can form capacitance type touch-control panel from mutual tolerance testing circuit 1 ' of the present embodiment, appearance and the mutual tolerance certainly of each touch control electrode of described capacitance type touch-control panel can utilize above-mentioned detecting from mutual tolerance testing circuit 1 '.Described capacitance type touch-control panel comprises multiple electrode and multiple from mutual tolerance testing circuit 1 '.Wherein, any two adjacent described electrodes are respectively the first above-mentioned electrode and the second electrode.Multiple from mutual tolerance testing circuit 1 ' in order to detect respectively the first electrode and the second electrode from holding, and detect the first adjacent electrode and the mutual tolerance of the second electrode.
(the possible effect of embodiment)
In sum, the embodiment of the present invention provide from mutual tolerance testing circuit and the capacitance type touch-control panel that has from mutual tolerance testing circuit, it utilizes Electrode connection to noble potential, make adjacent electrode equipotential, in detection in the process of capacitance, the capacitive detection circuit that two adjacent Electrode connection are identical or be connected to artificial circuit, makes the voltage differences of the second electrode and the first electrode minimize, and the mutual tolerance value of two adjacent electrodes can reduce to minimum to from holding the impact detected by this.In addition, artificial circuit, because have identical input circuit part with capacitive detection circuit, makes artificial circuit artificial capacitor testing circuit to the charge-discharge characteristic of this first electrode.And when the quantity of capacitive detection circuit reduces, artificial circuit also can substitute complete capacitive detection circuit, to reduce the usable floor area of circuit.
The foregoing is only embodiments of the invention, it is also not used to limit to the scope of the claims of the present invention.