CN104484497A - High-precision thermometric chip layout structure realized by using PNP (Plug-N-Play) transistors - Google Patents
High-precision thermometric chip layout structure realized by using PNP (Plug-N-Play) transistors Download PDFInfo
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- CN104484497A CN104484497A CN201410653753.2A CN201410653753A CN104484497A CN 104484497 A CN104484497 A CN 104484497A CN 201410653753 A CN201410653753 A CN 201410653753A CN 104484497 A CN104484497 A CN 104484497A
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Abstract
The invention discloses a high-precision thermometric chip layout structure realized by using PNP transistors (shown in 1) and belongs to the field of the integrated circuit design technology. The thermometric chip layout is composed of a first layout zone, a second layout zone, a third layout zone, a fourth layout zone, a fifth layout zone, a sixth layout zone, a seventh layout zone, an eighth layout zone and a ninth layout zone; the first layout zone is connected with the second, fifth and ninth layout zones; the second layout zone is connected with the first, third and fifth layout zones; the third layout zone is connected with the second and fifth layout zones; the fourth layout zone is connected with the fifth, sixth and seventh layout zones; the fifth layout zone is connected with the first, second, third, fourth, sixth, eighth and ninth layout zones; the sixth layout zone is connected with the fourth, fifth, seventh and eighth layout zones; the seventh layout zone is connected with the fourth, sixth and eighth layout zones; the eighth layout zone is connected with the fifth, sixth, seventh and ninth layout zones; and the ninth layout zone is connected with the first, fifth and eighth layout zones. According to the high-precision thermometric chip layout structure realized by using the PNP transistors, the positions of the layout zones with thermometric chips are fixed and the design of the high-precision thermometric chip layout with the PNP transistors is optimized.
Description
Technical field
The present invention relates to integrated circuit (IC) design technical field, particularly adopt the high precision measuring temperature chip layout structure that PNP transistor realizes
Background technology
In the temperature test occasion of the various non-ultimate temperatures such as temperature control system, industrial system, thermometer, the consumer goods, heat sensing system, often need wear-resisting resistance toly to touch, volume is little, and cabling is simple, easy to use, is applicable to the Digital Measurement of Temperature equipment of various small space.At present, market there is many moneys high precision measuring temperature chip to provide this kind of function.High precision measuring temperature chip adopts PNP transistor as temperature element, and reduce the restriction of technique, saved cost, high precision measuring temperature chip communication port is few, and minimum two lines that can adopt connect.The precision of thermometric and the interference of anti-power supply can be improve by layout design described in this patent, these advantages of high precision measuring temperature chip, make it be widely used in needing the occasion of thermometric.
Summary of the invention
In order to solve because layout design is unreasonable, cause the problem adopting the chip design of PNP transistor high precision measuring temperature, the invention provides a kind of temperature compensation high precision measuring temperature chip layout structure, described temperature compensation high precision measuring temperature chip layout is made up of the 1st domain district, the 2nd domain district, the 3rd domain district, the 4th domain district, the 5th domain district, the 6th domain district, the 7th domain district, the 8th domain district and the 9th domain district;
Described 1st domain district is high precision change-over circuit domain district, specifically comprises Current mirror layout strategies, reference voltage source domain and ADC domain.
Described 2nd domain district is strong ESD domain district, and described strong ESD domain district is made up of ESD and ESD intensifier circuit.
Described 3rd domain district is interface circuit domain district.
Described 4th domain district is digital control circuit domain district.
Described 5th domain district is novel backoff algorithm circuit layout district, devises the novel backoff algorithm digital circuit with independent intellectual property right.
Described 6th domain district is digital processing circuit domain district, has independently protection ring.
Described 7th domain district is electric power management circuit domain district, and described electric power management circuit domain district is made up of control circuit, electric capacity, and each part has independently protection ring.
Described 8th domain district is memory circuit domain district, and described memory circuit domain district is made up of digital working storage domain and nonvolatile memory domain.
Described 9th domain district is high precision measuring temperature circuit layout district, and described high precision measuring temperature circuit layout district trims domain by PNP temperature measurement circuit domain, amplifier domain, source of stable pressure domain and resistance and forms, temperature measurement circuit domain common centroid.
Accompanying drawing explanation
Fig. 1 chip layout
Fig. 2 PNP transistor high precision measuring temperature chip layout structural representation
Embodiment
The quality with its layout design is depended in a kind of success or not of chip to a great extent, the PNP thermometric chip of this patent design is adopted successfully to achieve high precision, it is characterized in that, described employing PNP transistor high precision measuring temperature chip layout is by high precision change-over circuit domain district part 1, strong ESD domain district part 2, interface circuit domain district part 3, digital control circuit domain district part 4, novel backoff algorithm circuit layout district part 5, digital processing circuit domain district part 6, electric power management circuit domain district part 7, memory circuit domain district part 8 and high precision measuring temperature circuit layout district part 9 form, 1st domain district is all connected with 2,5,9 domain districts, 2nd domain district is all connected with 1,3,5 domain districts, 3rd domain district is all connected with 2,5 domain districts, 4th domain district is all connected with 5,6,7 domain districts, 5th domain district is all connected with 1,2,3,4,6,8,9 domain districts, and the 6th domain district is all connected with 4,5,7,8 domain districts, and the 7th domain district is all connected with 4,6,8 domain districts, 8th domain district is all connected with 5,6,7,9, and the 9th domain district is all connected with 1,5,8 domain districts.
Technology contents of the present invention and technical characteristic disclose as above, but those of ordinary skill in the art may do based on the present invention the change and modification that do not deviate from spirit of the present invention.Therefore the present invention can not be limited to these embodiments shown in this article, but will meet the most wide region consistent with principle disclosed herein and features of novelty.
Claims (6)
1. one kind adopts PNP transistor high precision measuring temperature chip layout structure, it is characterized in that, described employing PNP transistor high precision measuring temperature chip layout is made up of the 1st domain district, the 2nd domain district, the 3rd domain district, the 4th domain district, the 5th domain district, the 6th domain district, the 7th domain district, the 8th domain district and the 9th domain district; 1st domain district is all connected with 2,5,9 domain districts, 2nd domain district is all connected with 1,3,5 domain districts, 3rd domain district is all connected with 2,5 domain districts, 4th domain district is all connected with 5,6,7 domain districts, 5th domain district is all connected with 1,2,3,4,6,8,9 domain districts, and the 6th domain district is all connected with 4,5,7,8 domain districts, and the 7th domain district is all connected with 4,6,8 domain districts, 8th domain district is all connected with 5,6,7,9, and the 9th domain district is all connected with 1,5,8 domain districts.
2. the high precision measuring temperature chip layout structure adopting PNP transistor to realize as claimed in claim 1, is characterized in that, described 1st domain district high precision change-over circuit.
3. the high precision measuring temperature chip layout structure adopting PNP transistor to realize as claimed in claim 1, it is characterized in that, described 2nd domain district is strong ESD domain district.
4. the high precision measuring temperature chip layout structure adopting PNP transistor to realize as claimed in claim 1, it is characterized in that, described 3rd domain district is interface circuit, for communicating with peripheral circuit.
5. the high precision measuring temperature chip layout structure adopting PNP transistor to realize as claimed in claim 1, it is characterized in that, described 4th domain district is digital control circuit, the simulation in coordination chip and the work of numerical portion.
6. the high precision measuring temperature chip layout structure adopting PNP transistor to realize as claimed in claim 1, it is characterized in that, described 5th, 6,7,8,9 domain districts are respectively novel backoff algorithm circuit, digital processing circuit, electric power management circuit, memory circuit, high precision PNP transistor temperature measurement circuit, realize the detection of temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410653753.2A CN104484497A (en) | 2014-11-18 | 2014-11-18 | High-precision thermometric chip layout structure realized by using PNP (Plug-N-Play) transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410653753.2A CN104484497A (en) | 2014-11-18 | 2014-11-18 | High-precision thermometric chip layout structure realized by using PNP (Plug-N-Play) transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104484497A true CN104484497A (en) | 2015-04-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410653753.2A Pending CN104484497A (en) | 2014-11-18 | 2014-11-18 | High-precision thermometric chip layout structure realized by using PNP (Plug-N-Play) transistors |
Country Status (1)
| Country | Link |
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| CN (1) | CN104484497A (en) |
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2014
- 2014-11-18 CN CN201410653753.2A patent/CN104484497A/en active Pending
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Addressee: Beijing 7Q Technology Co., Ltd. Document name: Notification of Publication and of Entering the Substantive Examination Stage of the Application for Invention |
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| CB02 | Change of applicant information |
Address after: 100029, room 5, building 98, 702 West Lake Road, Mentougou District, Beijing Applicant after: Beijing 7Q Technology Co., Ltd. Address before: 100029, A, block 69, mount, No. 202, Beichen West Road, Beijing, Chaoyang District Applicant before: Beijing 7Q Technology Co., Ltd. |
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Application publication date: 20150401 |